Page 1 8-Bit XC886/888CLM 8-Bit Single Chip Microcontroller User’s Manual V1.3 2010-02 M i c ro c o n t r o ll e rs...
Page 2 Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life.
Page 3 8-Bit XC886/888CLM 8-Bit Single Chip Microcontroller User’s Manual V1.3 2010-02 M i c ro c o n t r o ll e rs...
Page 4 Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com User’s Manual V1.3, 2010-02...
Page 5: Table Of Contents
XC886/888CLM Table of Contents Page Introduction ..........1-1 Feature Summary .
Page 6 XC886/888CLM Table of Contents Page 3.5.5.5 WDT Registers ........3-26 3.5.5.6 Port Registers .
Page 7 XC886/888CLM Table of Contents Page 5.6.1 Interrupt Node Enable Registers ......5-17 5.6.2 External Interrupt Control Registers .
Page 8 XC886/888CLM Table of Contents Page 7.2.2 Module Reset Behavior ........7-7 7.2.3 Booting Scheme .
Page 9 XC886/888CLM Table of Contents Page 11.2.3 Normalized Result Data ........11-4 11.2.4 CORDIC Coprocessor Operating Modes .
Page 10 XC886/888CLM Table of Contents Page 12.3.1.4 Continuous Transfers ........12-37 12.3.1.5 Port Control .
Page 11 XC886/888CLM Table of Contents Page 14.1.1.3 Switching Rules ........14-5 14.1.1.4 Compare Mode of T12 .
Page 12 XC886/888CLM Table of Contents Page 15.1.4.1 Basics ..........15-13 15.1.4.2 List of Unallocated Elements .
Page 13 XC886/888CLM Table of Contents Page 16.4.3 Channel Control ......... 16-10 16.4.4 Sequential Request Source .
Page 14 XC886/888CLM Table of Contents Page 17.3.2.1 Call the Monitor Program ....... . . 17-6 17.3.2.2 Activate the MBC pin .
Page 15: Introduction
The XC886/888 is a member of the high-performance XC800 family of 8-bit microcontrollers. It is based on the XC800 Core that is compatible with the industry standard 8051 processor. Furthermore, the XC886/888 is a superset of the Infineon XC866 8-bit microcontroller, thus offering an easy upgrade path for XC866 users.
Page 16 XC886/888CLM Introduction Figure 1-1 shows the functional units of the XC886/888. Flash or ROM On-Chip Debug Support UART Port 0 8-bit Digital I/O 24K/32K x 8 Boot ROM Capture/Compare Unit Port 1 8-bit Digital I/O 12K x 8 16-bit XC800 Core XRAM Compare Unit 8-bit Digital/...
Page 17 XC886/888CLM Introduction Note: For variants with LIN BSL support, only LIN BSL is available regardless of the availability of the CAN module and UART BSL. From these 10 different combinations of configuration and package type, each are further made available in many sales types, which are grouped according to device type, program memory sizes, power supply voltage, temperature and quality profile (Automotive or Industrial), as shown in Table...
Page 18: Feature Summary
XC886/888CLM Introduction Feature Summary The following list summarizes the main features of the XC886/888: • High-performance XC800 Core – compatible with standard 8051 processor – two clocks per machine cycle architecture (for memory access without wait state) – two data pointers •...
Page 19 XC886/888CLM Introduction – 64 bytes of monitor RAM • PG-TQFP-48 or PG-TQFP-64 pin packages • Temperature range – SAF (-40 to 85 °C) – SAK (-40 to 125 °C) – SAA (-40 to 140 °C) The block diagram of the XC886/888 is shown in Figure 1-2.
Page 20: Pin Configuration
XC886/888CLM Introduction Pin Configuration The pin configuration of the XC886, which is based on the PG-TQFP-48 package, is shown in Figure 1-3, while that of the XC888, which is based on the PG-TQFP-64 package, is shown in Figure 1-4. 36 35 34 33 32 31 30 29 28 27 26 25 P3.2 AREF P3.3...
Page 21 XC886/888CLM Introduction 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P3.2 AREF P3.3 AGND P3.4 P2.6 P3.5 P2.5 RESET P2.4 P2.3 XC888 P2.2 P4.0 P2.0 P4.1 P4.2 P5.7 P0.7 P5.6 P0.3 P0.2 P0.4 P0.0 10 11 12 13 14 15 16...
Page 22: Pin Definitions And Functions
XC886/888CLM Introduction Pin Definitions and Functions After reset, all pins are configured as input with one of the following: • Pull-up device enabled only (PU) • Pull-down device enabled only (PD) • High impedance with both pull-up and pull-down devices disabled (Hi-Z) The functions and default states of the XC886/888 external pins are provided in Table 1-3.
Page 23 XC886/888CLM Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pin Number Type Reset Function (TQFP-48/64) State P0.3 48/63 Hi-Z SCK_1 SSC Clock Input/Output COUT63_1 Output of Capture/Compare channel 3 RXDO1_0 UART1 Transmit Data Output P0.4 1/64 Hi-Z MTSR_1 SSC Master Transmit Output/ Slave Receive Input CC62_1 Input/Output of...
Page 24 XC886/888CLM Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pin Number Type Reset Function (TQFP-48/64) State Port 1 Port 1 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, Timer 0, Timer 1, Timer 2, Timer 21, MultiCAN and SSC.
Page 25 XC886/888CLM Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pin Number Type Reset Function (TQFP-48/64) State P1.6 8/10 CCPOS1_1 CCU6 Hall Input 1 T12HR_0 CCU6 Timer 12 Hardware Run Input EXINT6_0 External Interrupt Input 6 RXDC0_2 MultiCAN Node 0 Receiver Input T21_1 Timer 21 Input P1.7...
Page 26 XC886/888CLM Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pin Number Type Reset Function (TQFP-48/64) State Port 2 Port 2 is an 8-bit general purpose input-only port. It can be used as alternate functions for the digital inputs of the JTAG and CCU6. It is also used as the analog inputs for the ADC.
Page 27 XC886/888CLM Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pin Number Type Reset Function (TQFP-48/64) State Port 3 Port 3 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for CCU6, UART1, Timer 21 and MultiCAN. P3.0 35/43 Hi-Z...
Page 28 XC886/888CLM Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pin Number Type Reset Function (TQFP-48/64) State P3.7 34/42 Hi-Z EXINT4 External Interrupt Input 4 COUT63_0 Output of Capture/Compare channel 3 User’s Manual 1-14 V1.3, 2010-02 Introduction, V 1.1...
Page 29 XC886/888CLM Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pin Number Type Reset Function (TQFP-48/64) State Port 4 Port 4 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for CCU6, Timer 0, Timer 1, Timer 21 and MultiCAN.
Page 30 XC886/888CLM Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pin Number Type Reset Function (TQFP-48/64) State Port 5 Port 5 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for UART, UART1 and JTAG. P5.0 –/8 EXINT1_1...
Page 31: Chip Identification Number
XC886/888CLM Introduction Table 1-3 Pin Definitions and Functions (cont’d) Symbol Pin Number Type Reset Function (TQFP-48/64) State 7, 17, 43/ – – I/O Port Supply (3.3 or 5.0 V) 7, 25, 55 Also used by EVR and analog modules. All pins must be connected.
Page 32: Text Conventions
XC886/888CLM Introduction Text Conventions This document uses the following text conventions for named components of the XC886/888: • Functional units of the XC886/888 are shown in upper case. For example: “The SSC can be used to communicate with shift registers.” •...
Page 33: Reserved, Undefined And Unimplemented Terminology
XC886/888CLM Introduction Reserved, Undefined and Unimplemented Terminology In tables where register bit fields are defined, the following conventions are used to indicate undefined and unimplemented function. Further, types of bits and bit fields are defined using the abbreviations shown in Table 1-4.
Page 34 XC886/888CLM Introduction Table 1-5 Acronyms (cont’d) Acronym Description Controller Area Network CCU6 Capture/Compare Unit 6 Clock Generation Unit CORDIC Cordinate Rotation Digital Computer Central Processing Unit Error Correction Code Embedded Voltage Regulator Fractional Divider GPIO General Purpose I/O In-Application Programming Input/Output In-System Programming JTAG...
Page 35: Processor Architecture
XC886/888CLM Processor Architecture Processor Architecture The XC886/888 is based on a high-performance 8-bit Central Processing Unit (CPU) that is compatible with the standard 8051 processor. While the standard 8051 processor is designed around a 12-clock machine cycle, the XC886/888 CPU uses a 2-clock machine cycle.
Page 36 XC886/888CLM Processor Architecture Internal Data Memory Core SFRs Register Interface External Data Memory External SFRs 16-bit Registers & Memory Interface Program Memory Opcode & Immediate Multiplier / Divider Registers Opcode Decoder Timer 0 / Timer 1 CCLK State Machine & Memory Wait UART Power Saving...
Page 37: Cpu Register Description
XC886/888CLM Processor Architecture The program control section controls the sequence in which the instructions stored in program memory are executed. The 16-bit Program Counter (PC) holds the address of the next instruction to be executed. The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence.
Page 38: Program Status Word
XC886/888CLM Processor Architecture 2.2.5 Program Status Word The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU. Program Status Word Register Reset Value: 00 Field Bits Type Description Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of “one”...
Page 39: Extended Operation (Eo)
XC886/888CLM Processor Architecture 2.2.6 Extended Operation (EO) The instruction set includes an additional instruction MOVC @(DPTR++),A which allows program memory to be written. This instruction may be used to download code into the program memory when the CPU is initialized and subsequently, also to provide software updates.
Page 40: Power Control (Pcon)
XC886/888CLM Processor Architecture 2.2.7 Power Control (PCON) The CPU has two power-saving modes: idle mode and power-down mode. The idle mode can be entered via the PCON register. In idle mode, the clock to the CPU is stopped while the timers, serial port and interrupt controller continue to run using a half-speed clock.
Page 41 XC886/888CLM Processor Architecture (a) shows two timing diagrams for a 1-byte, 1-cycle (1 × machine cycle) Figure 2-2 instruction. The first diagram shows the instruction being executed within one machine cycle since the opcode (C1P2) is fetched from a memory without wait state. The second diagram shows the corresponding states of the same instruction being executed over two machine cycles (instruction time extended), with one wait state inserted for opcode fetching from the Flash memory.
Page 42 XC886/888CLM Processor Architecture CCLK Read next opcode (without wait state) C1P1 C1P2 next instruction Read next opcode (one wait state) C1P1 C1P2 WAIT WAIT next instruction (a) 1-byte, 1-cycle instruction, e.g. INC A Read 2 byte Read next opcode (without wait state) (without wait state) C1P1 C1P2...
Page 43 XC886/888CLM Processor Architecture Note: The XC886/888 CPU fetches the opcode of the next instruction while executing the current instruction. Table 2-1 provides a reference for the number of clock cycles required by each instruction. The first value applies to fetching operand(s) and opcode from fast program memory (e.g., Boot ROM and XRAM) without wait state.
Page 44 XC886/888CLM Processor Architecture Table 2-1 CPU Instruction Timing (cont’d) Mnemonic Hex Code Bytes Number of Cycles CCLK XC886/888 8051 no ws 1 ws 1 ws (with parallel read) DEC Rn 18-1F 2 or 4 DEC dir DEC @Ri 16-17 2 or 4 INC DPTR MUL AB DIV AB...
Page 45 XC886/888CLM Processor Architecture Table 2-1 CPU Instruction Timing (cont’d) Mnemonic Hex Code Bytes Number of Cycles CCLK XC886/888 8051 no ws 1 ws 1 ws (with parallel read) SWAP A 2 or 4 RL A 2 or 4 RLC A 2 or 4 RR A 2 or 4...
Page 46 XC886/888CLM Processor Architecture Table 2-1 CPU Instruction Timing (cont’d) Mnemonic Hex Code Bytes Number of Cycles CCLK XC886/888 8051 no ws 1 ws 1 ws (with parallel read) MOVX @DPTR,A 4 or 6 PUSH dir POP dir XCH A,Rn C8-CF 2 or 4 XCH A,dir XCH A,@Ri...
Page 47 XC886/888CLM Processor Architecture Table 2-1 CPU Instruction Timing (cont’d) Mnemonic Hex Code Bytes Number of Cycles CCLK XC886/888 8051 no ws 1 ws 1 ws (with parallel read) JC rel 6 or 8 JNC rel 6 or 8 JB bit,rel 6 or 8 JNB bit,rel 6 or 8...
Page 48: Memory Organization
XC886/888CLM Memory Organization Memory Organization The XC886/888 CPU operates in the following five address spaces: • 12 Kbytes of Boot ROM program memory • 256 bytes of internal RAM data memory • 1.5 Kbytes of XRAM memory (XRAM can be read/written as program memory or external data memory) •...
Page 49 XC886/888CLM Memory Organization Figure 3-2 illustrates the memory address spaces of the 32-Kbyte ROM devices. For the 24-Kbyte ROM devices, the shaded address regions are not available. For both 24-Kbyte and 32-Kbyte ROM devices, the last four bytes of the ROM from 7FFC to 7FFF are reserved for the ROM signature and cannot be used to store user...
Page 50: Compatibility Between Flash And Rom Devices
XC886/888CLM Memory Organization Compatibility between Flash and ROM devices Each Flash device consists of P-Flash and D-Flash banks. As shown in Figure 3-3, each physical D-Flash bank is mapped to two program memory address spaces: • D-Flash Bank 0 is mapped to 7000 –...
Page 51: Program Memory
XC886/888CLM Memory Organization D-Flash banks need to be used for program code based on address spaces 6000 – 6FFF and 7000 – 7FFB . This allows program code developed using the Flash device to be migrated to the ROM device without any changes. In the case that only 28 Kbytes of program code (later stored in 32-Kbyte ROM memory) is required for the ROM device with the available D-Flash bank (in the ROM device) used for data, then D-Flash Bank 1 in the Flash device should be used for program code...
Page 52: External Data Memory
XC886/888CLM Memory Organization 3.3.2 External Data Memory The 1.5-Kbyte XRAM is mapped to both the external data memory area and the program memory area. It can be accessed using both ‘MOVX’ and ‘MOVC’ instructions. The ‘MOVX’ instructions for XRAM access use either 8-bit or 16-bit indirect addresses. While the DPTR register is used for 16-bit addressing, either register R0 or R1 is used to form the 8-bit address.
Page 53: Memory Protection Strategy
XC886/888CLM Memory Organization Memory Protection Strategy The XC886/888 memory protection strategy includes: • Read-out protection: The user is able to protect the contents in the Flash (for Flash devices) and ROM (for ROM devices) memory from being read. – Flash protection is enabled by programming a valid password (8-bit non-zero value) via BSL mode 6.
Page 54 XC886/888CLM Memory Organization Table 3-1 Flash Protection Modes (cont’d) Flash Protection Without hardware With hardware protection protection D-Flash Read instructions in Read instructions in Read instructions in contents can be any program memory any program memory the P-Flash or D- read by Flash External access...
Page 55 XC886/888CLM Memory Organization Table 3-2 User Programmable Password Bit Fields Bits Size Usage Value 1-bit Flash hardware Flash hardware protection mode 0 is protection mode selected. selection bit Flash hardware protection mode 1 is selected. 2-bit Select field for Flash Only P-Flash banks are erased during banks to be erased unprotection.
Page 56: Miscellaneous Control Register
XC886/888CLM Memory Organization Although no protection scheme can be considered infallible, the XC886/888 memory protection strategy provides a very high level of protection for a general purpose microcontroller. 3.4.2 Miscellaneous Control Register The MISC_CON register contains the DFLASHEN bit to enable the erase of a D-Flash bank.
Page 57: Special Function Registers
XC886/888CLM Memory Organization Special Function Registers The Special Function Registers (SFRs) occupy direct internal data memory space in the range 80 to FF . All registers, except the program counter, reside in the SFR area. The SFRs include pointers and registers that provide an interface between the CPU and the on-chip peripherals.
Page 58 XC886/888CLM Memory Organization Standard Area (RMAP = 0) Module 1 SFRs SYSCON0.RMAP Module 2 SFRs Module n SFRs SFR Data (to/from CPU) Mapped Area (RMAP = 1) Module (n+1) SFRs Module (n+2) SFRs Module m SFRs Direct Internal Data Memory Address Figure 3-4 Address Extension by Mapping User’s Manual...
Page 59: System Control Register 0
XC886/888CLM Memory Organization 3.5.1.1 System Control Register 0 The SYSCON0 register contains bits to select the SFR mapping and interrupt structure 2 mode. SYSCON0 System Control Register 0 Reset Value: 04 IMODE RMAP Field Bits Type Description RMAP Special Function Register Map Control The access to the standard SFR area is enabled.
Page 60: Address Extension By Paging
XC886/888CLM Memory Organization 3.5.2 Address Extension by Paging Address extension is further performed at the module level by paging. With the address extension by mapping, the XC886/888 has a 256-SFR address range. However, this is still less than the total number of SFRs needed by the on-chip peripherals. To meet this requirement, some peripherals have a built-in local address extension mechanism for increasing the number of addressable SFRs.
Page 61 XC886/888CLM Memory Organization In order to access a register located in a page other than the current one, the current page must be exited. This is done by reprogramming the bit field PAGE in the page register. Only then can the desired access be performed. If an interrupt routine is initiated between the page register access and the module register access, and the interrupt needs to access a register located in another page, the current page setting can be saved, the new one programmed, and the old page setting...
Page 62: Page Register
XC886/888CLM Memory Organization 3.5.2.1 Page Register The page register has the following definition: MOD_PAGE Page Register for module MOD Reset Value: 00 STNR PAGE Field Bits Type Description PAGE [2:0] Page Bits When written, the value indicates the new page. When read, the value indicates the currently active page.
Page 63: Bit-Addressing
XC886/888CLM Memory Organization Field Bits Type Description [7:6] Operation Manual page mode. The value of STNR is ignored and PAGE is directly written. New page programming with automatic page saving. The value written to the bit positions of PAGE is stored. In parallel, the previous contents of PAGE are saved in the storage bit field STx indicated by STNR.
Page 64: System Control Registers
XC886/888CLM Memory Organization 3.5.4 System Control Registers The system control SFRs are used to control the overall system functionalities, such as interrupts, variable baud rate generation, clock management, bit protection scheme, oscillator and PLL control. The SFRs are located in the standard memory area (RMAP = 0) and are organized into 2 pages.
Page 65 XC886/888CLM Memory Organization Field Bits Type Description [7:6] Operation Manual page mode. The value of STNR is ignored and PAGE is directly written. New page programming with automatic page saving. The value written to the bit positions of PAGE is stored. In parallel, the previous contents of PAGE are saved in the storage bit field STx indicated by STNR.
Page 66: Bit Protection Scheme
XC886/888CLM Memory Organization 3.5.4.1 Bit Protection Scheme The bit protection scheme prevents direct software writing of selected bits (i.e., protected bits) using the PASSWD register. When the bit field MODE is 11 , writing 10011 to the bit field PASS opens access to writing of all protected bits, and writing 10101 to the bit field PASS closes access to writing of all protected bits.
Page 67 XC886/888CLM Memory Organization Field Bits Type Description PASS [7:3] Password bits The Bit Protection Scheme only recognizes three patterns. 11000 Enables writing of the bit field MODE. 10011 Opens access to writing of all protected bits. 10101 Closes access to writing of all protected bits. User’s Manual 3-20 V1.3, 2010-02...
Page 68: Xc886/888 Register Overview
XC886/888CLM Memory Organization 3.5.5 XC886/888 Register Overview The SFRs of the XC886/888 are organized into groups according to their functional units. The contents (bits) of the SFRs are summarized in Chapter 3.5.5.1 Chapter 3.5.5.14. Note: The addresses of the bitaddressable SFRs appear in bold typeface. 3.5.5.1 CPU Registers The CPU SFRs can be accessed in both the standard and mapped memory areas...
Page 69: Mdu Registers
XC886/888CLM Memory Organization Table 3-3 CPU Register Overview (cont’d) Addr Register Name A8 H IEN0 Reset: 00 H Bit Field Interrupt Enable Register 0 Type B8 H Reset: 00 H Bit Field Interrupt Priority Register Type B9 H Reset: 00 H Bit Field PT2H PT1H...
Page 70: Cordic Registers
XC886/888CLM Memory Organization Table 3-4 MDU Register Overview (cont’d) Addr Register Name B3 H Reset: 00 H Bit Field DATA MDU Result Register 1 Type B4 H Reset: 00 H Bit Field DATA MDU Operand Register 2 Type B4 H Reset: 00 H Bit Field DATA...
Page 71: System Control Registers
XC886/888CLM Memory Organization Table 3-5 CORDIC Register Overview (cont’d) Addr Register Name A0 H CD_STATC Reset: 00 H Bit Field KEEP KEEP KEEP DMAP INT_E ERRO CORDIC Status and Data Control Register Type A1 H CD_CON Reset: 00 H Bit Field X_USI ST_M ROTV...
Page 72 XC886/888CLM Memory Organization Table 3-6 SCU Register Overview (cont’d) Addr Register Name BC H NMISR Reset: 00 H Bit Field FNMI FNMI FNMI FNMI FNMI FNMI FNMI NMI Status Register VDDP OCDS FLASH Type BD H BCON Reset: 00 H Bit Field BGSEL BRDIS...
Page 73: Wdt Registers
XC886/888CLM Memory Organization Table 3-6 SCU Register Overview (cont’d) Addr Register Name BE H COCON Reset: 00 H Bit Field TLEN COUT COREL Clock Output Control Register Type E9 H MISC_CON Reset: 00 H Bit Field DFLAS Miscellaneous Control Register Type RMAP = 0, PAGE 3 B3 H...
Page 74: Port Registers
XC886/888CLM Memory Organization Table 3-7 WDT Register Overview (cont’d) Addr Register Name BE H WDTL Reset: 00 H Bit Field Watchdog Timer Register Low Type BF H WDTH Reset: 00 H Bit Field Watchdog Timer Register High Type 3.5.5.6 Port Registers The Port SFRs can be accessed in the standard memory area (RMAP = 0).
Page 75 XC886/888CLM Memory Organization Table 3-8 Port Register Overview (cont’d) Addr Register Name RMAP = 0, PAGE 1 80 H P0_PUDSEL Reset: FF H Bit Field P0 Pull-Up/Pull-Down Select Type Register 86 H P0_PUDEN Reset: C4 H Bit Field P0 Pull-Up/Pull-Down Enable Type Register 90 H...
Page 76: Adc Registers
XC886/888CLM Memory Organization Table 3-8 Port Register Overview (cont’d) Addr Register Name 93 H P5_ALTSEL1 Reset: 00 H Bit Field P5 Alternate Select 1 Register Type B0 H P3_ALTSEL0 Reset: 00 H Bit Field P3 Alternate Select 0 Register Type B1 H P3_ALTSEL1 Reset: 00 H...
Page 77 XC886/888CLM Memory Organization Table 3-9 ADC Register Overview (cont’d) Addr Register Name CD H ADC_LCBR Reset: B7 H Bit Field BOUND1 BOUND0 Limit Check Boundary Register Type CE H ADC_INPCR0 Reset: 00 H Bit Field Input Class 0 Register Type CF H ADC_ETRCR Reset: 00 H...
Page 78 XC886/888CLM Memory Organization Table 3-9 ADC Register Overview (cont’d) Addr Register Name D3 H ADC_RESR3H Reset: 00 H Bit Field RESULT Result Register 3 High Type RMAP = 0, PAGE 3 CA H ADC_RESRA0L Reset: 00 H Bit Field RESULT CHNR Result Register 0, View A Low Type...
Page 79 XC886/888CLM Memory Organization Table 3-9 ADC Register Overview (cont’d) Addr Register Name CC H ADC_CHINSR Reset: 00 H Bit Field CHINS CHINS CHINS CHINS CHINS CHINS CHINS CHINS Channel Interrupt Set Register Type CD H ADC_CHINPR Reset: 00 H Bit Field CHINP CHINP CHINP...
Page 80: Timer 2 Registers
XC886/888CLM Memory Organization 3.5.5.8 Timer 2 Registers The Timer 2 SFRs can be accessed in the standard memory area (RMAP = 0). Table 3-10 T2 Register Overview Addr Register Name RMAP = 0 C0 H T2_T2CON Reset: 00 H Bit Field EXF2 EXEN C/T2...
Page 81: Ccu6 Registers
XC886/888CLM Memory Organization Table 3-11 T21 Register Overview (cont’d) Addr Register Name C5 H T21_T2H Reset: 00 H Bit Field THL2 Timer 2 Register High Type 3.5.5.10 CCU6 Registers The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0). Table 3-12 CCU6 Register Overview Addr Register Name...
Page 82 XC886/888CLM Memory Organization Table 3-12 CCU6 Register Overview (cont’d) Addr Register Name FA H CCU6_CC60SRL Reset: 00 H Bit Field CC60SL Capture/Compare Shadow Register Type for Channel CC60 Low FB H CCU6_CC60SRH Reset: 00 H Bit Field CC60SH Capture/Compare Shadow Register Type for Channel CC60 High FC H...
Page 83 XC886/888CLM Memory Organization Table 3-12 CCU6 Register Overview (cont’d) Addr Register Name FB H CCU6_CC60RH Reset: 00 H Bit Field CC60VH Capture/Compare Register for Type Channel CC60 High FC H CCU6_CC61RL Reset: 00 H Bit Field CC61VL Capture/Compare Register for Type Channel CC61 Low FD H...
Page 84 XC886/888CLM Memory Organization Table 3-12 CCU6 Register Overview (cont’d) Addr Register Name FB H CCU6_TCTR2H Reset: 00 H Bit Field T13RSEL T12RSEL Timer Control Register 2 High Type FC H CCU6_MODCTRL Reset: 00 H Bit Field T12MODEN Modulation Control Register Low Type FD H CCU6_MODCTRH...
Page 85: Uart1 Registers
XC886/888CLM Memory Organization Table 3-12 CCU6 Register Overview (cont’d) Addr Register Name FE H CCU6_CMPSTATL Reset: 00 H Bit Field CC63 CC62 CC61 CC60 Compare State Register Low POS2 POS1 POS0 Type FF H CCU6_CMPSTATH Reset: 00 H Bit Field T13IM COUT COUT...
Page 86: Ssc Registers
XC886/888CLM Memory Organization 3.5.5.12 SSC Registers The SSC SFRs can be accessed in the standard memory area (RMAP = 0). Table 3-14 SSC Register Overview Addr Register Name RMAP = 0 A9 H SSC_PISEL Reset: 00 H Bit Field Port Input Select Register Type AA H SSC_CONL...
Page 87: Ocds Registers
XC886/888CLM Memory Organization Table 3-15 CAN Register Overview (cont’d) Addr Register Name DB H DATA0 Reset: 00 H Bit Field CAN Data Register 0 Type DC H DATA1 Reset: 00 H Bit Field CAN Data Register 1 Type DD H DATA2 Reset: 00 H Bit Field...
Page 88: Boot Rom Operating Mode
XC886/888CLM Memory Organization Table 3-16 OCDS Register Overview (cont’d) Addr Register Name EC H MMWR2 Reset: 00 H Bit Field MMWR2 Monitor Work Register 2 Type Boot ROM Operating Mode After a reset, the CPU will always start by executing the Boot ROM code in active memory map 0.
Page 89: User Mode
XC886/888CLM Memory Organization FFFF FFFF Select F600 active XRAM F000 F000 memory map 1 Boot ROM Boot ROM C000 C000 D-Flash Banks (as data) A000 Jump to 8000 C00X D-Flash Banks (as program) 3000 6000 Boot ROM P-Flash Banks CPU starts 0000 0000 execution...
Page 90: Ocds Mode
XC886/888CLM Memory Organization 3.6.3 OCDS Mode If (MBC, TMS, P0.0) = (0, 1, 0), the OCDS mode will be entered for debugging program code. The OCDS hardware is initialized and a jump to program memory address 0000 is performed next. The user code in the Flash or ROM memory is executed and the debugging process may be started.
Page 91: Flash Memory
XC886/888CLM Flash Memory Flash Memory The XC886/888 has an embedded user-programmable non-volatile Flash memory that allows for fast and reliable storage of user code and data. It is operated with a single 2.5 V supply from the Embedded Voltage Regulator (EVR) and does not require additional programming or erasing voltage.
Page 92: Flash Memory Map
XC886/888CLM Flash Memory Flash Memory Map The XC886/888 product family offers Flash devices with either 24 Kbytes or 32 Kbytes of embedded Flash memory. Each Flash device consists of Program Flash (P-Flash) and Data Flash (D-Flash) bank(s). The 32-Kbyte Flash device consists of 6 P-Flash and 2 D-Flash banks, while the 24-Kbyte Flash device consists of also of 6 P-Flash banks but with the upper 2 banks only 2 Kbytes each, and only 1 D-Flash bank.
Page 93: Flash Bank Sectorization
XC886/888CLM Flash Memory • P-Flash pair bank 1 occupies 2000 – 3FFF • P-Flash pair bank 2 occupies 4000 – 5FFF for 32-Kbyte device or 4000 – 4FFF for 24-Kbyte device The D-Flash bank(s) in the XC886/888 Flash devices are mapped to two program memory address spaces: •...
Page 94 XC886/888CLM Flash Memory Sector Partitioning in P-Flash: • One 3.75-Kbyte sector • Two 128-byte sectors Note: In 24-Kbyte Flash variants, P-Flash banks 4 and 5 have only a single 2-Kbyte sector (Sector 0) available. Each sector in a P-Flash bank is grouped with the corresponding sector from the other bank within a bank pair to form a P-Flash bank pair sector.
Page 95: Parallel Read Access Of P-Flash
XC886/888CLM Flash Memory For example, the user’s program can implement a buffer mechanism for each sector. Double copies of each data set can be stored in separate sectors of similar size to ensure that a backup copy of the data set is available in the event the actual data set is corrupted or erased.
Page 96 XC886/888CLM Flash Memory Wordline Address The wordline (WL) addresses of the P-Flash and D-Flash banks, used as program code and as data, are given in Figure 4-4, Figure 4-5 Figure 4-6 respectively. Byte 63 Byte 2 Byte 1 Byte 0 5FFF ……………………………..
Page 97 XC886/888CLM Flash Memory Byte 31 Byte 2 Byte 1 Byte 0 Byte 31 Byte 2 Byte 1 Byte 0 7FFF …………………………….. 7FE2 7FE1 7FE0 6FFF …………………………….. 6FE2 6FE1 6FE0 7F9F …………………………….. 7F82 7F81 7F80 6F9F …………………………….. 6F82 6F81 6F80 7F7F ……………………………..
Page 98 XC886/888CLM Flash Memory Byte 31 Byte 2 Byte 1 Byte 0 Byte 31 Byte 2 Byte 1 Byte 0 BFFF …………………………….. BFE2 BFE1 BFE0 AFFF …………………………….. AFE2 AFE1 AFE0 BF9F …………………………….. BF82 BF81 BF80 AF9F …………………………….. AF82 AF81 AF80 BF7F ……………………………..
Page 99 XC886/888CLM Flash Memory A WL address can be calculated as follow: × n, with 0 ≤ n ≤ 127 for P-Flash Pair 0 0000 + 40 (4.1) × n, with 0 ≤ n ≤ 127 for P-Flash Pair 1 2000 + 40 (4.2) ×...
Page 100 XC886/888CLM Flash Memory 32 bytes (1 WL) 16 bytes 16 bytes 0000 ….. 0000 0000 ….. 0000 Program 1 0000 ….. 0000 1111 ….. 1111 0000 ….. 0000 1111 ….. 1111 Program 2 1111 ….. 0000 0000 ….. 0000 Note: A Flash memory cell can be programmed 1111 …..
Page 101: Operating Modes
XC886/888CLM Flash Memory Operating Modes The Flash operating modes for each bank are shown in Figure 4-8. Sector(s) Erase Ready-to-Read Program Call of Call of FLASH_ERASE routine FLASH_PROG routine or by BSL or by BSL Power-Down System Power-Down Figure 4-8 Flash Operating Modes In general, the Flash operating modes are controlled by the BSL and Flash program/erase subroutines (see...
Page 102: Error Detection And Correction
XC886/888CLM Flash Memory Error Detection and Correction The 8-bit data from the CPU is encoded with an Error Correction Code (ECC) before being stored in the Flash memory. During a read access, data is retrieved from the Flash memory and decoded for dynamic error detection and correction. The correction algorithm (hamming code) has the capability to: •...
Page 103: Flash Error Address Register
XC886/888CLM Flash Memory 4.6.1 Flash Error Address Register The FEAL and FEAH registers together store the 16-bit Flash address at which the ECC error occurs. FEAL Flash Error Address Register Low Reset Value: 00 ECCERRADDR Field Bits Type Description ECCERRADDR [7:0] ECC Error Address Value [7:0] FEAH...
Page 104: In-System Programming
XC886/888CLM Flash Memory In-System Programming In-System Programming (ISP) of the Flash memory is supported via the Boot ROM- based Bootstrap Loader (BSL), allowing a blank microcontroller device mounted onto an application board to be programmed with the user code, and also a previously programmed device to be erased then reprogrammed without removal from the board.
Page 105: In-Application Programming
XC886/888CLM Flash Memory In-Application Programming In some applications, the Flash contents may need to be modified during program execution. In-Application Programming (IAP) is supported so that users can program or erase the Flash memory from their Flash user program by calling some subroutines in the Boot ROM (see Figure 4-9).
Page 106: Flash Programming
XC886/888CLM Flash Memory 4.8.1 Flash Programming Each call of the Flash program subroutine allows the programming of 64 and 32 bytes of data into the selected wordline (WL) of the P-Flash and D-Flash bank respectively. Before calling this subroutine, the Flash NMI can be enabled via bit NMIFLASH in register NMICON so that the Flash NMI service routine is entered once programming of the selected WL is completed.
Page 107: Flash Erasing
XC886/888CLM Flash Memory For P-Flash programming,the last 6 LSB of the DPL is 0 for aligned WL address, for e.g. 40 , 80 . As for the D-Flash programming, the last 5 LSB of the DPL is 0 for an aligned WL address, for e.g. 00 , 40 , 60 , 80...
Page 108: Aborting Flash Erase
XC886/888CLM Flash Memory Table 4-2 Flash Erase Subroutine (cont’d) Select sector(s) to be erased for P-Flash Bank Pair 1. LSB represents sector 0, bit 2 represents sector 2. Select sector(s) to be erased for P-Flash Bank Pair 2. LSB represents sector 0, bit 2 represents sector 2. Flash NMI (NMICON.NMIFLASH) is enabled (1) or disabled (0) MISC_CON.DFLASHEN bit = 1...
Page 109 XC886/888CLM Flash Memory • For the specified cycling time , each aborted erase constitutes one program/erase cycling. • Maximum allowable number of aborted erase for each D-Flash sector during lifetime is 2500. The Flash erase abort subroutine call (see Table 4-3) cannot be performed anytime within 5 ms after the erase operation has started.
Page 110: Flash Bank Read Status
XC886/888CLM Flash Memory 4.8.4 Flash Bank Read Status Each call of the Flash bank read status subroutine allows the checking of ready-to-read status of the Flash bank. Before calling this subroutine, the user must ensure that the ACC SFR is set accordingly (see Table 4-4).
Page 111: Get Chip Information
XC886/888CLM Flash Memory 4.8.6 Get Chip Information This subroutine reads out a 4-byte data that contains chip related information. In the XC886/888, it reads out the 4-byte chip identification number, which is used to identify the particular device variant. Table 4-6 Get Chip Information Subroutine Subroutine DFE1...
Page 112: Interrupt System
XC886/888CLM Interrupt System Interrupt System The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt requests. In addition to the standard interrupt functions supported by the core, e.g., configurable interrupt priority and interrupt masking, the XC886/888 interrupt system provides extended interrupt support capabilities such as the mapping of each interrupt vector to several interrupt sources to increase the number of interrupt sources supported, and additional status registers for detecting and identifying the interrupt...
Page 113 XC886/888CLM Interrupt System Highest Timer 0 Lowest Overflow Priority Level TCON.5 000B IP.1/ IPH.1 IEN0.1 Timer 1 Overflow TCON.7 001B IP.3/ IEN0.3 IPH.3 UART Receive SCON.0 >=1 UART 0023 Transmit IP.4/ IEN0.4 SCON.1 IPH.4 EINT0 TCON.1 0003 IP.0/ IEN0.0 IPH.0 TCON.0 EXINT0 EXICON0.0/1...
Page 114 XC886/888CLM Interrupt System Highest Timer 2 Overflow Lowest T2_T2CON.7 Priority Level >=1 T2EX EXF2 T2_T2CON.6 EXEN2 T2_T2CON.3 EDGES Normal Divider NDOV T2_T2MOD.5 Overflow >=1 FDCON.2 End of 002B EOFSYN Synch Byte IP.5/ >=1 FDCON.4 IEN0.5 IPH.5 Synch Byte ERRSYN Error SYNEN FDCON.5 MultiCAN_0...
Page 115 XC886/888CLM Interrupt System Highest Lowest Priority Level SSC_EIR IRCON1.0 SSC_TIR >=1 003B IRCON1.1 ESSC IP1.1/ SSC_RIR IEN1.1 IPH1.1 IRCON1.2 EXINT2 EINT2 IRCON0.2 EXINT2 EXICON0.4/5 UART1_SCON.0 >=1 UART1 UART1_SCON.1 Timer 21 Overflow >=1 0043 T21_T2CON.7 IP1.2/ >=1 IEN1.2 IPH1.2 T21EX EXF2 T21_T2CON.6 EXEN2 T21_T2CON.3...
Page 116 XC886/888CLM Interrupt System Highest Lowest Priority Level EXINT3 EINT3 IRCON0.3 EXINT3 EXICON0.6/7 EXINT4 EINT4 IRCON0.4 EXINT3 EXICON1.0/1 >=1 EXINT5 EINT5 004B IRCON0.5 IP1.3/ IEN1.3 IPH1.3 EXINT5 EXICON1.2/3 EXINT6 EINT6 IRCON0.6 EXINT6 EXICON1.4/5 MultiCAN_3 CANSRC3 IRCON2.4 IEN0.7 Bit-addressable Request flag is cleared by hardware Figure 5-4 Interrupt Request Sources (Part 4) User’s Manual...
Page 117 XC886/888CLM Interrupt System Highest Lowest CCU6 interrupt node 0 CCU6SR0 Priority Level IRCON3.0 >=1 MultiCAN_4 CANSRC4 0053 ECCIP0 IP1.4/ IRCON3.1 IEN1.4 IPH1.4 CCU6 interrupt node 1 CCU6SR1 >=1 IRCON3.4 MultiCAN_5 005B CANSRC5 ECCIP1 IP1.5/ IRCON3.5 IEN1.5 IPH1.5 CCU6 interrupt node 2 CCU6SR2 IRCON4.0 >=1...
Page 118 XC886/888CLM Interrupt System WDT Overflow NMIWDT NMIISR.0 NMIWDT NMICON.0 PLL Loss of Lock NMIPLL NMIISR.1 NMIPLL NMICON.1 Flash NMI NMIFLASH NMIISR.2 NMIFLASH NMICON.2 >=1 0073 Maskable NMIVDD VDD Pre-Warning Interrupt NMIISR.4 NMIVDD NMICON.4 NMIVDDP VDDP Pre-Warning NMIISR.5 NMIVDDP NMICON.5 NMIECC Flash ECC Error NMIISR.6 NMIECC...
Page 119: Interrupt Structure
XC886/888CLM Interrupt System Interrupt Structure An interrupt event source may be generated from the on-chip peripherals or from external. Detection of interrupt events is controlled by the respective on-chip peripherals. Interrupt status flags are available for determining which interrupt event has occurred, especially useful for an interrupt node which is shared by several event sources.
Page 120: Interrupt Structure 2
XC886/888CLM Interrupt System disabled (e.g., software polling is used), its interrupt status flag must be cleared by software since the core will not be interrupted (and therefore the interrupt acknowledge is not generated). For the UART module, interrupt status flags RI and TI in register SCON will not be cleared by the core even when its pending interrupt request is serviced.
Page 121: System Control Register 0
XC886/888CLM Interrupt System where the pending interrupt request is cleared directly by resetting the node’s interrupt status flags. If IMODE = 0, only on clearing the interrupt node enable bit will indirectly clear its pending interrupt request. Hence when IMODE = 0, the interrupt node enable bit additionally serves a dual function: to enable/disable the generation of pending interrupt request, and to clear an already generated pending interrupt request (by resetting enable bit to 0).
Page 122: Interrupt Source And Vector
XC886/888CLM Interrupt System Interrupt Source and Vector Each interrupt event source has an associated interrupt vector address for the interrupt node it belongs to. This vector is accessed to service the corresponding interrupt node request. The interrupt service of each interrupt node can be individually enabled or disabled via an enable bit.
Page 123 XC886/888CLM Interrupt System Table 5-1 Interrupt Vector Addresses (cont’d) Interrupt Vector Assignment for Enable Bit Node Address XC886/888 XINTR6 0033 MultiCAN Nodes 1 and 2 EADC IEN1 ADC[1:0] XINTR7 003B ESSC XINTR8 0043 External Interrupt 2 CORDIC UART1 UART1 Fractional Divider (Normal Divider Overflow) MDU[1:0] XINTR9...
Page 124: Interrupt Priority
XC886/888CLM Interrupt System Interrupt Priority An interrupt that is currently being serviced can only be interrupted by a higher-priority interrupt, but not by another interrupt of the same or lower priority. Hence, an interrupt of the highest priority cannot be interrupted by any other interrupt request. If two or more requests of different priority levels are received simultaneously, the request with the highest priority is serviced first.
Page 125: Interrupt Handling
XC886/888CLM Interrupt System Interrupt Handling The interrupt request signals are sampled at phase 2 in each machine cycle. The sampled requests are then polled during the following machine cycle. If one interrupt node request was active at phase 2 of the preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL to the appropriate service routine, provided this hardware-generated LCALL is not blocked by any of the following conditions:...
Page 126: Interrupt Response Time
XC886/888CLM Interrupt System Interrupt Response Time Due to an interrupt event of (the various sources of) an interrupt node, its corresponding request signal will be sampled active at phase 2 in every machine cycle. The value is not polled by the circuitry until the next machine cycle. If the request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed.
Page 127 XC886/888CLM Interrupt System CCLK 4-cycle current instruction Interrupt (MUL or DIV) request sampled active Interrupt instruction at request LCALL Interrupt interrupt vector polled request (last cycle of sampled current instruction) Interrupt response time = 6 x machine cycle Figure 5-10 Interrupt Response Time for Condition 2 CCLK Interrupt 2-cycle current instruction...
Page 128: Interrupt Registers
XC886/888CLM Interrupt System Interrupt Registers Interrupt registers are used for interrupt node enable, external interrupt control, interrupt flags and interrupt priority setting. 5.6.1 Interrupt Node Enable Registers Each interrupt node can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt enable registers IEN0 or IEN1.
Page 129 XC886/888CLM Interrupt System Field Bits Type Description Interrupt Node XINTR4 Enable XINTR4 is disabled XINTR4 is enabled Interrupt Node XINTR5 Enable XINTR5 is disabled XINTR5 is enabled Global Interrupt Mask All pending interrupt requests (except NMI) are blocked from the core. Pending interrupt requests are not blocked from the core.
Page 130 XC886/888CLM Interrupt System Field Bits Type Description ECCIP0 Interrupt Node XINTR10 Enable XINTR10 is disabled XINTR10 is enabled ECCIP1 Interrupt Node XINTR11 Enable XINTR11 is disabled XINTR11 is enabled ECCIP2 Interrupt Node XINTR12 Enable XINTR12 is disabled XINTR12 is enabled ECCIP3 Interrupt Node XINTR13 Enable XINTR13 is disabled...
Page 131 XC886/888CLM Interrupt System Field Bits Type Description NMIVDDP VDDP Prewarning NMI Enable VDDP NMI is disabled. VDDP NMI is enabled. Note: When the external power supply is 3.3 V, the user must disable NMIVDDP. NMIECC ECC NMI Enable ECC NMI is disabled. ECC NMI is enabled.
Page 132: External Interrupt Control Registers
XC886/888CLM Interrupt System 5.6.2 External Interrupt Control Registers The seven external interrupts, EXT_INT[6:0], are driven into the XC886/888 from the ports. External interrupts can be positive, negative, or double edge triggered. Registers EXICON0 and EXICON1 specify the active edge for the external interrupt. Among the external interrupts, external interrupt 0 and external interrupt 1 can be selected to bypass edge detection for direct feed-through to the core.
Page 133 XC886/888CLM Interrupt System Field Bits Type Description EXINT2 [5:4] External Interrupt 2 Trigger Select Interrupt on falling edge Interrupt on rising edge Interrupt on both rising and falling edges External interrupt 2 is disabled EXINT3 [7:6] External Interrupt 3 Trigger Select Interrupt on falling edge Interrupt on rising edge Interrupt on both rising and falling edges...
Page 134 XC886/888CLM Interrupt System MODPISEL Peripheral Input Select Register Reset Value: 00 JTAGTCK URRISH JTAGTDIS EXINT2IS EXINT1IS EXINT0IS URRIS Field Bits Type Description EXINT0IS External Interrupt 0 Input Select External Interrupt Input EXINT0_0 is selected. External Interrupt Input EXINT0_1 is selected. EXINT1IS External Interrupt 1 Input Select External Interrupt Input EXINT1_0 is selected.
Page 135 XC886/888CLM Interrupt System TCON Timer and Counter Control/Status Register Reset Value: 00 Field Bits Type Description External Interrupt 0 Level/Edge Trigger Control Flag Low-level triggered external interrupt 0 is selected. Falling edge triggered external interrupt 0 is selected. External Interrupt 1 Level/Edge Trigger Control Flag Low-level triggered external interrupt 1 is selected.
Page 136: Interrupt Flag Registers
XC886/888CLM Interrupt System 5.6.3 Interrupt Flag Registers The interrupt flags for the different interrupt sources are located in several Special Function Registers (SFRs). In case of software and hardware access to a flag bit at the same time, hardware will have higher priority. IRCON0 Interrupt Request Register 0 Reset Value: 00...
Page 137 XC886/888CLM Interrupt System Field Bits Type Description Error Interrupt Flag for SSC This bit is set by hardware and can only be cleared by software. Interrupt event has not occurred. Interrupt event has occurred. Transmit Interrupt Flag for SSC This bit is set by hardware and can only be cleared by software.
Page 138 XC886/888CLM Interrupt System IRCON2 Interrupt Request Register 2 Reset Value: 00 CANSRC3 CANSRC0 Field Bits Type Description CANSRC0 Interrupt Flag 0 for MultiCAN This bit is set by hardware and can only be cleared by software. Interrupt event has not occurred. Interrupt event has occurred.
Page 139 XC886/888CLM Interrupt System Field Bits Type Description CANSRC4 Interrupt Flag 4 for MultiCAN This bit is set by hardware and can only be cleared by software. Interrupt event has not occurred. Interrupt event has occurred. CCU6SR1 Interrupt Flag 1 for CCU6 This bit is set by hardware and can only be cleared by software.
Page 140 XC886/888CLM Interrupt System Field Bits Type Description CCU6SR3 Interrupt Flag 3 for CCU6 This bit is set by hardware and can only be cleared by software. Interrupt event has not occurred. Interrupt event has occurred. CANSRC7 Interrupt Flag 7 for MultiCAN This bit is set by hardware and can only be cleared by software.
Page 141 XC886/888CLM Interrupt System Field Bits Type Description Timer 1 Overflow Flag Set by hardware on Timer 1 overflow. Cleared by hardware when processor vectors to interrupt routine. Can also be cleared by software. SCON Serial Channel Control Register Reset Value: 00 Field Bits Type Description...
Page 142 XC886/888CLM Interrupt System Field Bits Type Description FNMIPLL PLL NMI Flag No PLL NMI has occurred. PLL loss-of-lock to the external crystal has occurred. FNMIFLASH Flash NMI Flag No Flash NMI has occurred. Flash NMI has occurred. FNMIOCDS OCDS NMI Flag No OCDS NMI has occurred.
Page 143: Interrupt Priority Registers
XC886/888CLM Interrupt System 5.6.4 Interrupt Priority Registers Each interrupt source can be individually programmed to one of the four available priority levels. Two pairs of interrupt priority registers are available to program the priority level of each interrupt vector. The first pair of Interrupt Priority Registers are SFRs IP and IPH. The second pair of Interrupt Priority Registers are SFRs IP1 and IPH1.
Page 144 XC886/888CLM Interrupt System Interrupt Priority High Register Reset Value: 00 PT2H PT1H PX1H PT0H PX0H Field Bits Type Description PX0H Priority Level High Bit for Interrupt Node XINTR0 PT0H Priority Level High Bit for Interrupt Node XINTR1 PX1H Priority Level High Bit for Interrupt Node XINTR2 PT1H Priority Level High Bit for Interrupt Node XINTR3 Priority Level High Bit for Interrupt Node XINTR4...
Page 145 XC886/888CLM Interrupt System Field Bits Type Description PCCIP3 Priority Level Low Bit for Interrupt Node XINTR13 IPH1 Interrupt Priority 1 High Register Reset Value: 00 PCCIP3H PCCIP2H PCCIP1H PCCIP0H PXMH PX2H PSSCH PADCH Field Bits Type Description PADCH Priority Level High Bit for Interrupt Node XINTR6 PSSCH Priority Level High Bit for Interrupt Node XINTR7 PX2H...
Page 146: Interrupt Flag Overview
XC886/888CLM Interrupt System Interrupt Flag Overview The interrupt events have interrupt flags that are located in different SFRs. Table 5-4 provides the corresponding SFR to which each interrupt flag belongs. Detailed information on the interrupt flags is provided in the respective peripheral chapters. Table 5-4 Locations of the Interrupt Request Flags Interrupt Source...
Page 147 XC886/888CLM Interrupt System Table 5-4 Locations of the Interrupt Request Flags (cont’d) Interrupt Source Interrupt Flag SSC Error IRCON1 SSC Transmit IRCON1 SSC Receive IRCON1 MultiCAN Interrupt 0 CANSRC0 IRCON2 MultiCAN Interrupt 1 CANSRC1 IRCON1 MultiCAN Interrupt 2 CANSRC2 IRCON1 MultiCAN Interrupt 3 CANSRC3 IRCON2...
Page 148: Parallel Ports
XC886/888CLM Parallel Ports Parallel Ports The XC886 has 34 port pins organized into five parallel ports, Port 0 (P0) to Port 4 (P4), while the XC888 has 48 port pins organized into six parallel ports, Port 0 (P0) to Port 5 (P5).
Page 149: General Port Operation
XC886/888CLM Parallel Ports General Port Operation Figure 6-1 shows the block diagram of an XC886/888 bidirectional port pin. Each port pin is equipped with a number of control and data bits, thus enabling very flexible usage of the pin. By defining the contents of the control register, each individual pin can be configured as an input or an output.
Page 150 XC886/888CLM Parallel Ports Px_PUDSEL Internal Bus Pull-up/Pull-down Select Register Px_PUDEN Pull-up/Pull-down Enable Register Px_OD Open Drain Control Register Px_DIR Direction Register Px_ALTSEL0 Alternate Select Register 0 VDDP Px_ALTSEL1 Pull enable Alternate Select Register 1 Device AltDataOut 3 enable Output AltDataOut 2 Driver AltDataOut1 enable...
Page 151 XC886/888CLM Parallel Ports activated while register P2_PUDEN enables or disables the pull device. The analog input (AnalogIn) bypasses the digital circuitry and Schmitt-Trigger device for direct feed through to the ADC input channel. Internal Bus Px_PUDSEL Pull-up/Pull-down Select Register Px_PUDEN Pull-up/Pull-down Enable Register Px_DIR...
Page 152: General Register Description
XC886/888CLM Parallel Ports 6.1.1 General Register Description The individual control and data bits of each parallel port are implemented in a number of 8-bit registers. Bits with the same meaning and function are assembled together in the same register. The registers configure and use the port as general purpose I/O or alternate function input/output.
Page 153: Data Register
XC886/888CLM Parallel Ports 6.1.1.1 Data Register If a port pin is used as general purpose output, output data is written into the data register Px_DATA. If a port pin is used as general purpose input, the latched value of the port pin can be read through register Px_DATA.
Page 154: Direction Register
XC886/888CLM Parallel Ports 6.1.1.2 Direction Register The direction of bidirectional port pins is controlled by the respective direction register Px_DIR. For input-only port pins, register Px_DIR is used to enable or disable the input drivers. Px_DIR Port x Direction Register Field Bits Type Description...
Page 155: Open Drain Control Register
XC886/888CLM Parallel Ports 6.1.1.3 Open Drain Control Register Each pin in output mode can be switched to open drain mode. If driven with 1, no driver will be activated and the pin output state depends on the internal pull-up/pull-down device setting. If driven with 0, the driver’s pull-down transistor will be activated. The open drain mode is controlled by the register Px_OD.
Page 156 XC886/888CLM Parallel Ports Px_PUDSEL Port x Pull-Up/Pull-Down Select Register Field Bits Type Description Pull-Up/Pull-Down Select Port x Bit n (n = 0 – 7) Pull-down device is selected. Pull-up device is selected. Px_PUDEN Port x Pull-Up/Pull-Down Enable Register Field Bits Type Description Pull-Up/Pull-Down Enable at Port x Bit n (n = 0 –...
Page 157: Alternate Input And Output Functions
XC886/888CLM Parallel Ports 6.1.1.5 Alternate Input and Output Functions The number of alternate functions that uses a pin for input is not limited. Each port control logic of an I/O pin provides several input paths of digital input value via register or direct digital input value.
Page 158: Register Map
XC886/888CLM Parallel Ports Register Map The Port SFRs are located in the standard memory area (RMAP = 0) and are organized into 4 pages. The PORT_PAGE register is located at address B2 . It contains the page value and page control information. The addresses of the Port SFRs are listed in Table 6-2.
Page 159 XC886/888CLM Parallel Ports Field Bits Type Description PAGE [2:0] Page Bits When written, the value indicates the new page. When read, the value indicates the currently active page. STNR [5:4] Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP.
Page 160: Port 0
XC886/888CLM Parallel Ports Port 0 Port P0 is a 8-bit general purpose bidirectional port. The registers of P0 are summarized Table 6-3. Table 6-3 Port 0 Registers Register Short Name Register Full Name P0_DATA Port 0 Data Register P0_DIR Port 0 Direction Register P0_OD Port 0 Open Drain Control Register P0_PUDSEL...
Page 161 XC886/888CLM Parallel Ports Table 6-4 Port 0 Input/Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P0.1 Input P0_DATA.P1 – ALT1 TDI_0 JTAG ALT2 T13HR_1 CCU6 ALT3 RXD_1 UART ALT4 RXDC1_0 MultiCAN Output P0_DATA.P1 – ALT1 EXF2_1 Timer 2 ALT2 COUT61_1 CCU6...
Page 162 XC886/888CLM Parallel Ports Table 6-4 Port 0 Input/Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P0.4 Input P0_DATA.P4 – ALT1 MTSR_1 ALT2 – – ALT3 CC62_1 CCU6 Output P0_DATA.P4 – ALT1 MTSR_1 ALT2 CC62_1 CCU6 ALT3 TXD1_0 UART1 P0.5 Input...
Page 163 XC886/888CLM Parallel Ports Table 6-4 Port 0 Input/Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P0.7 Input P0_DATA.P7 – ALT1 – – ALT2 – – ALT3 – – Output P0_DATA.P7 – ALT1 CLKOUT_1 ALT2 – – ALT3 –...
Page 164: Register Description
XC886/888CLM Parallel Ports 6.3.1.1 Register Description Note: For the XC886, bit P6 is not available for use as its corresponding pad is not bonded. P0_DATA Port 0 Data Register Reset Value: 00 Field Bits Type Description Port 0 Pin n Data Value (n = 0 –...
Page 165 XC886/888CLM Parallel Ports P0_OD Port 0 Open Drain Control Register Reset Value: 00 Field Bits Type Description Port 0 Pin n Open Drain Mode (n = 0 – 7) Normal mode; output is actively driven for 0 and 1 states (default) Open drain mode;...
Page 166 XC886/888CLM Parallel Ports P0_PUDEN Port 0 Pull-Up/Pull-Down Enable Register Reset Value: C4 Field Bits Type Description Pull-Up/Pull-Down Enable at Port 0 Bit n (n = 0 – 7) Pull-up or Pull-down device is disabled. Pull-up or Pull-down device is enabled (default). P0_ALTSELn (n = 0 –...
Page 167: Port 1
XC886/888CLM Parallel Ports Port 1 Port P1 is a 8-bit general purpose bidirectional port. The registers of P1 are summarized Table 6-5. Table 6-5 Port 1 Registers Register Short Name Register Full Name P1_DATA Port 1 Data Register P1_DIR Port 1 Direction Register P1_OD Port 1 Open Drain Control Register P1_PUDSEL...
Page 168 XC886/888CLM Parallel Ports Table 6-6 Port 1 Input/Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P1.1 Input P1_DATA.P1 – ALT1 – – ALT2 EXINT3 External interrupt 3 ALT3 T0_1 Timer 0 Output P1_DATA.P1 – ALT1 TDO_1 JTAG ALT2 TXD_0 UART...
Page 169 XC886/888CLM Parallel Ports Table 6-6 Port 1 Input/Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P1.4 Input P1_DATA.P4 – ALT1 MRST_0 ALT2 EXINT0_1 External interrupt 0 ALT3 RXDC1_3 MultiCAN Output P1_DATA.P4 – ALT1 MRST_0 ALT2 – – ALT3 –...
Page 170 XC886/888CLM Parallel Ports Table 6-6 Port 1 Input/Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P1.7 Input P1_DATA.P7 – ALT1 CCPOS2_1 CCU6 ALT2 T13HR_0 CCU6 ALT3 T2_1 Timer 2 Output P1_DATA.P7 – ALT1 – – ALT2 – –...
Page 171 XC886/888CLM Parallel Ports 6.4.2 Register Description P1_DATA Port 1 Data Register Reset Value: 00 Field Bits Type Description Port 1 Pin n Data Value (n = 0 – 7) Port 1 pin n data value = 0 (default) Port 1 pin n data value = 1 P1_DIR Port 1 Direction Register Reset Value: 00...
Page 172 XC886/888CLM Parallel Ports P1_OD Port 1 Open Drain Control Register Reset Value: 00 Field Bits Type Description Port 1 Pin n Open Drain Mode (n = 0 – 7) Normal mode; output is actively driven for 0 and 1 states (default) Open drain mode;...
Page 173 XC886/888CLM Parallel Ports P1_PUDEN Port 1 Pull-Up/Pull-Down Enable Register Reset Value: FF Field Bits Type Description Pull-Up/Pull-Down Enable at Port 1 Bit n (n = 0 – 7) Pull-up or Pull-down device is disabled. Pull-up or Pull-down device is enabled (default). P1_ALTSELn (n = 0 –...
Page 174: Port 2
XC886/888CLM Parallel Ports Port 2 Port P2 is an 8-bit general purpose input-only port. The registers of P2 are summarized Table 6-7. Table 6-7 Port 2 Registers Register Short Name Register Full Name P2_DATA Port 2 Data Register P2_DIR Port 2 Direction Register P2_PUDSEL Port 2 Pull-Up/Pull-Down Select Register P2_PUDEN...
Page 175 XC886/888CLM Parallel Ports Table 6-8 Port 2 Input Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P2.2 Input P2_DATA.P2 – ALT 1 CCPOS2_0 CCU6 ALT 2 – – ALT 3 CTRAP_1 CCU6 ALT 4 – – ALT 5 CC60_3 CCU6 ANALOG...
Page 176 XC886/888CLM Parallel Ports Table 6-8 Port 2 Input Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P2.6 Input P2_DATA.P6 – ALT 1 – – ALT 2 – – ALT 3 – – ALT 4 – – ALT 5 –...
Page 177: Register Description
XC886/888CLM Parallel Ports 6.5.2 Register Description P2_DATA Port 2 Data Register Reset Value: 00 Field Bits Type Description Port 2 Pin n Data Value (n = 0 – 7) Port 2 pin n data value = 0 (default) Port 2 pin n data value = 1 P2_DIR Port 2 Direction Register Reset Value: 00...
Page 178 XC886/888CLM Parallel Ports P2_PUDSEL Port 2 Pull-Up/Pull-Down Select Register Reset Value: FF Field Bits Type Description Pull-Up/Pull-Down Select Port 2 Bit n (n = 0 – 7) Pull-down device is selected. Pull-up device is selected. P2_PUDEN Port 2 Pull-Up/Pull-Down Enable Register Reset Value: 00 Field Bits...
Page 179: Port 3
XC886/888CLM Parallel Ports Port 3 Port P3 is an 8-bit general purpose bidirectional port. The registers of P3 are summarized in Table 6-9. Table 6-9 Port 3 Registers Register Short Name Register Full Name P3_DATA Port 3 Data Register P3_DIR Port 3 Direction Register P3_OD Port 3 Open Drain Control Register...
Page 180 XC886/888CLM Parallel Ports Table 6-10 Port 3 Input/Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P3.1 Input P3_DATA.P1 – ALT1 – – ALT2 CCPOS0_2 CCU6 ALT3 CC61_2 CCU6 Output P3_DATA.P1 – ALT1 COUT60_0 CCU6 ALT2 CC61_2 CCU6 ALT3 TXD1_1 UART1...
Page 181 XC886/888CLM Parallel Ports Table 6-10 Port 3 Input/Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P3.4 Input P3_DATA.P4 – ALT1 CC62_0 CCU6 ALT2 T2EX1_0 Timer 21 ALT3 RXDC0_1 MultiCAN Output P3_DATA.P4 – ALT1 CC62_0 CCU6 ALT2 – –...
Page 182 XC886/888CLM Parallel Ports Table 6-10 Port 3 Input/Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P3.7 Input P3_DATA.P7 – ALT1 – – ALT2 EXINT4 External interrupt 4 ALT3 – – Output P3_DATA.P7 – ALT1 COUT63_0 CCU6 ALT2 –...
Page 183: Register Description
XC886/888CLM Parallel Ports 6.6.2 Register Description P3_DATA Port 3 Data Register Reset Value: 00 Field Bits Type Description Port 3 Pin n Data Value (n = 0 – 7) Port 3 pin n data value = 0 (default) Port 3 pin n data value = 1 P3_DIR Port 3 Direction Register Reset Value: 00...
Page 184 XC886/888CLM Parallel Ports P3_OD Port 3 Open Drain Control Register Reset Value: 00 Field Bits Type Description Port 3 Pin n Open Drain Mode (n = 0 – 7) Normal mode; output is actively driven for 0 and 1 states (default) Open drain mode;...
Page 185 XC886/888CLM Parallel Ports P3_PUDEN Port 3 Pull-Up/Pull-Down Enable Register Reset Value: 40 Field Bits Type Description Pull-Up/Pull-Down Enable at Port 3 Bit n (n = 0 – 7) Pull-up or Pull-down device is disabled. Pull-up or Pull-down device is enabled. P3_ALTSELn (n = 0 –...
Page 186: Port 4
XC886/888CLM Parallel Ports Port 4 Port P4 is an 8-bit general purpose bidirectional port. The registers of P4 are summarized in Table 6-11. Table 6-11 Port 4 Registers Register Short Name Register Full Name P4_DATA Port 4 Data Register P4_DIR Port 4 Direction Register P4_OD Port 4 Open Drain Control Register...
Page 187 XC886/888CLM Parallel Ports Table 6-12 Port 4 Input/Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P4.1 Input P4_DATA.P1 – ALT1 – – ALT2 – – ALT3 – – Output P4_DATA.P1 – ALT1 COUT60_1 CCU6 ALT2 – – ALT3 TXDC0_3 MultiCAN...
Page 188 XC886/888CLM Parallel Ports Table 6-12 Port 4 Input/Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P4.4 Input P4_DATA.P4 – ALT1 CCPOS0_3 CCU6 ALT2 T0_0 Timer 0 ALT3 – – Output P4_DATA.P4 – ALT1 CC61_4 CCU6 ALT2 – –...
Page 189 XC886/888CLM Parallel Ports Table 6-12 Port 4 Input/Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P4.7 Input P4_DATA.P7 – ALT1 CTRAP_3 CCU6 ALT2 – – ALT3 – – Output P4_DATA.P7 – ALT1 COUT62_2 CCU6 ALT2 – – ALT3 –...
Page 190: Register Description
XC886/888CLM Parallel Ports 6.7.2 Register Description Note: For the XC886, bits P2, P4, P5, P6 and P7 are not available for use as their corresponding pads are not bonded. P4_DATA Port 4 Data Register Reset Value: 00 Field Bits Type Description Port 4 Pin n Data Value (n = 0 –...
Page 191 XC886/888CLM Parallel Ports P4_OD Port 4 Open Drain Control Register Reset Value: 00 Field Bits Type Description Port 4 Pin n Open Drain Mode (n = 0 – 7) Normal mode; output is actively driven for 0 and 1 states (default) Open drain mode;...
Page 192 XC886/888CLM Parallel Ports P4_PUDEN Port 4 Pull-Up/Pull-Down Enable Register Reset Value: See note below Field Bits Type Description Pull-Up/Pull-Down Enable at Port 4 Bit n (n = 0 – 7) Pull-up or Pull-down device is disabled. Pull-up or Pull-down device is enabled. Note: The reset value of P4_PUDEN is package dependent.
Page 193 XC886/888CLM Parallel Ports Port 5 Port P5 is an 8-bit general purpose bidirectional port. The registers of P5 are summarized in Table 6-13. Note: Port 5 is only available in XC888. Table 6-13 Port 5 Registers Register Short Name Register Full Name P5_DATA Port 5 Data Register P5_DIR...
Page 194 XC886/888CLM Parallel Ports Table 6-14 Port 5 Input/Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P5.1 Input P5_DATA.P1 – ALT1 – – ALT2 EXINT2_1 External Interrupt 2 ALT3 – – Output P5_DATA.P1 – ALT1 – – ALT2 –...
Page 195 XC886/888CLM Parallel Ports Table 6-14 Port 5 Input/Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P5.4 Input P5_DATA.P4 – ALT1 – – ALT2 – – ALT3 – – Output P5_DATA.P4 – ALT1 – – ALT2 RXDO_2 UART ALT3 –...
Page 196 XC886/888CLM Parallel Ports Table 6-14 Port 5 Input/Output Functions (cont’d) Port Pin Input/Output Select Connected Signal(s) From/to Module P5.7 Input P5_DATA.P7 – ALT1 TDI_2 JTAG ALT2 RXD1_2 UART1 ALT3 – – Output P5_DATA.P7 – ALT1 – – ALT2 – – ALT3 –...
Page 197 XC886/888CLM Parallel Ports 6.8.2 Register Description P5_DATA Port 5 Data Register Reset Value: 00 Field Bits Type Description Port 5 Pin n Data Value (n = 0 – 7) Port 5 pin n data value = 0 (default) Port 5 pin n data value = 1 P5_DIR Port 5 Direction Register Reset Value: 00...
Page 198 XC886/888CLM Parallel Ports P5_OD Port 5 Open Drain Control Register Reset Value: 00 Field Bits Type Description Port 5 Pin n Open Drain Mode (n = 0 – 7) Normal mode; output is actively driven for 0 and 1 states (default) Open drain mode;...
Page 199 XC886/888CLM Parallel Ports P5_PUDEN Port 5 Pull-Up/Pull-Down Enable Register Reset Value: FF Field Bits Type Description Pull-Up/Pull-Down Enable at Port 5 Bit n (n = 0 – 7) Pull-up or Pull-down device is disabled. Pull-up or Pull-down device is enabled. P5_ALTSELn (n = 0 –...
Page 200: Power Supply, Reset And Clock Management
XC886/888CLM Power Supply, Reset and Clock Management Power Supply, Reset and Clock Management The XC886/888 provides a range of utility features for secure system performance under critical conditions (e.g., brownout). The power supply to the core, memories and the peripherals is regulated by the Embedded Voltage Regulator (EVR) that comes with detection circuitries to ensure that the supplied voltages are within the specified operating range.
Page 201 XC886/888CLM Power Supply, Reset and Clock Management EVR Features: • Input voltage ( ): 3.3 V/5.0 V • Output voltage ( ): 2.5 V +/-7.5% • Low power voltage regulator provided in power-down mode • prewarning detection • brownout detection The EVR consists of a main voltage regulator and a low power voltage regulator.
Page 202: Reset Control
XC886/888CLM Power Supply, Reset and Clock Management Reset Control The XC886/888 has five types of resets: power-on reset, hardware reset, watchdog timer reset, power-down wake-up reset, and brownout reset. When the XC886/888 is first powered up, the status of certain pins (see Table 7-2) must be defined to ensure proper start operation of the device.
Page 203 XC886/888CLM Power Supply, Reset and Clock Management 3.3 / 5V 220nF 100nF typ. RESET 100nF XC886/888 Figure 7-2 Reset Circuitry Voltage 2.5V 2.3V 0.9*V Time Voltage RESET with capacitor < 0.4V Time typ. < 50 µs Figure 7-3 during Power-on Reset DDP, RESET When the system starts up, the PLL is disconnected from the oscillator and will run at its...
Page 204: Hardware Reset
XC886/888CLM Power Supply, Reset and Clock Management The status of pins MBC, TMS and P0.0 is latched by the reset. The latched values are used to select the boot options (see Section 7.2.3). A correctly executed reset leaves the system in a defined state. The program execution starts from location 0000 Figure 7-4 shows the power-on reset sequence.
Page 205: Power-Down Wake-Up Reset
XC886/888CLM Power Supply, Reset and Clock Management 7.2.1.4 Power-Down Wake-Up Reset Power is still applied to the XC886/888 during power-down mode, as the low power voltage regulator is still operating. If power-down mode is entered appropriately, all important system states will have been preserved in the Flash by software. If the XC886/888 is in power-down mode, three options are available to awaken it: •...
Page 206: Module Reset Behavior
XC886/888CLM Power Supply, Reset and Clock Management 7.2.2 Module Reset Behavior Table 7-1 lists the functions of the XC886/888 and the various reset types that affect these functions. The symbol “ ” signifies that the particular function is reset to its default state.
Page 207: Booting Scheme
XC886/888CLM Power Supply, Reset and Clock Management 7.2.3 Booting Scheme When the XC886/888 is reset, it must identify the type of configuration with which to start the different modes once the reset sequence is complete. Thus, boot configuration information that is required for activation of special modes and conditions needs to be applied by the external world through input pins.
Page 208: Register Description
XC886/888CLM Power Supply, Reset and Clock Management 7.2.4 Register Description Table 7-3 Reset Values of Register PMCON0 Reset Source Reset Value Power-on Reset/Hardware Reset/Brownout Reset 0000 0000 Watchdog Timer Reset 0100 0000 Power-down Wake-up Reset 0010 0000 PMCON0 Power Mode Control Register 0 Reset Value: See Table 7-3 WDTRST...
Page 209 XC886/888CLM Power Supply, Reset and Clock Management Field Bits Type Description WDTRST Watchdog Timer Reset Indication Bit No watchdog timer reset occurred. Watchdog timer reset has occurred. This bit can only be set by hardware and reset by software. Reserved Returns 0 if read;...
Page 210: Clock System
XC886/888CLM Power Supply, Reset and Clock Management Clock System The XC886/888 clock system performs the following functions: • Acquires and buffers incoming clock signals to create a master clock frequency • Distributes in-phase synchronized clock signals throughout the system • Divides a system master clock frequency into lower frequencies for power saving mode 7.3.1...
Page 211: Functional Description
XC886/888CLM Power Supply, Reset and Clock Management 7.3.1.1 Functional Description When the XC886/888 is powered up, the PLL is disconnected from the oscillator and will run at its VCO base frequency. After the EVR is stable, provided the oscillator is running, the PLL will be connected and the continuous lock detection will ensure that the PLL starts functioning.
Page 212: Clock Source Control
XC886/888CLM Power Supply, Reset and Clock Management Changing PLL Parameters To change the PLL parameters, first check if the oscillator is running (OSC_CON.OSCR = 1). In this case: 1. Select VCO bypass mode (VCOBYP = 1). 2. Program desired NDIV value. 3.
Page 213 XC886/888CLM Power Supply, Reset and Clock Management PLL Base Mode When the oscillator is disconnected from the PLL, the system clock is derived from the VCO base (free running) frequency clock (shown in Table 7-6) divided by the K factor. (7.1) VCObase Prescaler Mode (VCO Bypass Operation)
Page 214: Clock Management
XC886/888CLM Power Supply, Reset and Clock Management For different source oscillator, the selection of output frequency = 96 MHz is shown Table 7-5. Table 7-5 System frequency ( = 96 MHz) Oscillator fosc fsys On-chip 9.6 MHz 96 MHz External 8 MHz 96 MHz 6 MHz...
Page 215 XC886/888CLM Power Supply, Reset and Clock Management Furthermore, a clock output (CLKOUT) is available on pin P(0.0 or 0.7) as an alternate output. If bit COUTS = 0, the output clock is from oscillator output frequency; if bit COUTS = 1, the clock output frequency is chosen by the bit field COREL. Under this selection, the clock output frequency can further be divided by 2 using toggle latch (bit TLEN is set to 1), so that the resulting output frequency has 50% duty cycle.
Page 216: Register Description
XC886/888CLM Power Supply, Reset and Clock Management 7.3.4 Register Description OSC_CON OSC Control Register Reset Value: 0000 1000 OSCPD OSCSS ORDRES OSCR Field Bits Type Description OSCR Oscillator Run Status Bit This bit shows the state of the oscillator run detection.
Page 217 XC886/888CLM Power Supply, Reset and Clock Management PLL_CON PLL Control Register Reset Value: 1001 0000 NDIV VCOBYP OSCDISC RESLD LOCK Field Bits Type Description LOCK PLL Lock Status Flag PLL is not locked. PLL is locked. RESLD Restart Lock Detection Setting this bit will reset the PLL lock status flag and restart the lock detection.
Page 218 XC886/888CLM Power Supply, Reset and Clock Management Field Bits Type Description NDIV [7:4] PLL N-Divider 0000 N = 10 0001 N = 12 0010 N = 13 0011 N = 14 0100 N = 15 0101 N = 16 0110 N = 17 0111 N = 18 1000 N = 19 1001 N = 20...
Page 219 XC886/888CLM Power Supply, Reset and Clock Management Field Bits Type Description CLKREL [3:0] Clock Divider 0000 f 0001 f 0010 f 0011 f 0100 f 0101 f 0110 f 0111 f 1000 f 1001 f 1010 f /128 1011 f /192 1100 f /256...
Page 220 XC886/888CLM Power Supply, Reset and Clock Management COCON Clock Output Control Register Reset Value: 00 TLEN COUTS COREL Field Bits Type Description COREL [3:0] Clock Output Divider 0000 f 0001 f 0010 f 0011 f 0100 f 0101 f 0110 f 0111 f 1000 f 1001 f...
Page 221 XC886/888CLM Power Supply, Reset and Clock Management Note: Registers OSC_CON, PLL_CON, CMCON, and COCON are not reset during the watchdog timer reset. User’s Manual 7-22 V1.3, 2010-02 Power, Reset and Clock, V 1.0...
Page 222: Power Saving Modes
XC886/888CLM Power Saving Modes Power Saving Modes The power saving modes in the XC886/888 provide flexible power consumption through a combination of techniques, including: • Stopping the CPU clock • Stopping the clocks of individual system components • Reducing clock speed of some peripheral components •...
Page 223: Functional Description
XC886/888CLM Power Saving Modes Functional Description This section describes the various power saving modes, their operations, and how they are entered and exited. 8.1.1 Idle Mode The idle mode is used to reduce power consumption by stopping the core’s clock. In idle mode, the oscillator continues to run, but the core is stopped with its clock disabled.
Page 224: Power-Down Mode
XC886/888CLM Power Saving Modes routine or at any point in the program where the user no longer requires the slow- down mode. • The other way of terminating the combined idle and slow-down mode is through a hardware reset. 8.1.3 Power-down Mode In power-down mode, the oscillator and the PLL are turned off.
Page 225 XC886/888CLM Power Saving Modes Exiting Power-down Mode If power-down mode is exited via a hardware reset, the device is put into the hardware reset state. When the wake-up source and wake-up type have been selected prior to entering power-down mode, the power-down mode can be exited via EXINT0 pin/RXD pin. Bits MODPISEL.URRIS and MODPISEL.URRISH are used to select one of the three RXD inputs and bit MODPISEL.EXINT0IS is used to select one of the two EXINT0 inputs.
Page 226: Peripheral Clock Management
XC886/888CLM Power Saving Modes 8.1.4 Peripheral Clock Management The amount of reduction in power consumption that can be achieved by this feature depends on the number of peripherals running. Peripherals that are not required for a particular functionality can be disabled by gating off the clock inputs. For example, in idle mode, if all timers are stopped, and ADC, CCU6, CORDIC, MDU, MultiCAN and the serial interfaces are not running, maximum power reduction can be achieved.
Page 227 XC886/888CLM Power Saving Modes Field Bits Type Description Power-down Enable Bit Setting this bit will cause the chip to enter power-down mode. It is reset by wake-up circuit. The PD bit is a protected bit. When the Protection Scheme (see Chapter 3.5.4.1) is activated, this bit cannot be written directly.
Page 228 XC886/888CLM Power Saving Modes MODPISEL Peripheral Input Select Register Reset Value: 00 JTAGTCK URRISH JTAGTDIS EXINT2IS EXINT1IS EXINT0IS URRIS Field Bits Type Description URRISH, 6, 0 UART Receive Input Select URRIS UART Receiver Input RXD_0 is selected. UART Receiver Input RXD_1 is selected. UART Receiver Input RXD_2 is selected.
Page 229 XC886/888CLM Power Saving Modes Field Bits Type Description CCU_DIS CCU Disable Request. Active high CCU is in normal operation (default). CCU is disabled. T2_DIS Timer 2 Disable Request. Active high Timer2 is in normal operation (default). Timer2 is disabled. MDU_DIS MDU Disable Request.
Page 230 XC886/888CLM Power Saving Modes ADC_GLOBCTR Global Control Register Reset Value: 00 ANON Field Bits Type Description ANON Analog Part Switched On This bit enables the analog part of the ADC module and defines its operation mode. The analog part is switched off and conversions are not possible.
Page 231 XC886/888CLM Power Saving Modes Field Bits Type Description OSCPD On-chip OSC Power-down Control The on-chip oscillator is not powered down. The on-chip oscillator is powered down. [7:5] Reserved Returns 0 if read; should be written with 0. User’s Manual 8-10 V1.3, 2010-02 Power Saving Modes, V 1.0...
Page 232: Watchdog Timer
XC886/888CLM Watchdog Timer Watchdog Timer The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failures. The WDT is reset at a regular interval that is predefined by the user. The CPU must service the WDT within this interval to prevent the WDT from causing an XC886/888 system reset.
Page 233: Functional Description
XC886/888CLM Watchdog Timer Functional Description The Watchdog Timer is a 16-bit timer, which is incremented by a count rate of /2 or PCLK /128. This 16-bit timer is realized as two concatenated 8-bit timers. The upper 8 bits PCLK of the Watchdog Timer can be preset to a user-programmable value via a watchdog service access in order to vary the watchdog expire time.
Page 234 XC886/888CLM Watchdog Timer access to the WDT and causes the WDT to activate WDTRST, although no NMI request is generated in this instance. The window boundary is from 0000 to the value obtained from the concatenation of WDTWINB and 00 .
Page 235: Module Suspend Control
XC886/888CLM Watchdog Timer Table 9-1 lists the possible ranges for the watchdog time which can be achieved using a certain module clock. Some numbers are rounded to 3 significant digits. Table 9-1 Watchdog Time Ranges Reload value in Prescaler for WDTREL 2 (WDTIN = 0) 128 (WDTIN = 1)
Page 236: Register Map
XC886/888CLM Watchdog Timer Register Map Five SFRs control the operations of the WDT. They can be accessed from the mapped SFR area. Table 9-2 lists the addresses of these SFRs. Table 9-2 SFR Address List Address Register WDTCON WDTREL WDTWINB WDTL WDTH Register Description...
Page 237 XC886/888CLM Watchdog Timer WDTCON Watchdog Timer Register Reset Value: 00 WINBEN WDTPR WDTEN WDTRS WDTIN Field Bits Type Description WDTIN Watchdog Timer Input Frequency Selection Input frequency is PCLK Input frequency is /128 PCLK WDTRS WDT Refresh Start. Active high. Set to start refresh operation on the watchdog timer.
Page 238 XC886/888CLM Watchdog Timer WDTL Watchdog Timer, Low Byte Reset Value: 00 WDT[7..0] Field Bits Type Description WDT[7..0] Watchdog Timer Current Value WDTH Watchdog Timer, High Byte Reset Value: 00 WDT[15..8] Field Bits Type Description WDT[15..8] Watchdog Timer Current Value User’s Manual V1.3, 2010-02 Watchdog Timer, V1.0...
Page 239 XC886/888CLM Watchdog Timer WDTWINB Watchdog Window-Boundary Count Reset Value: 00 WDTWINB Field Bits Type Description WDTWINB Watchdog Window-Boundary Count Value This value is programmble. Within this Window- Boundary range from 0000H to (WDTWINB,00H), the WDT cannot do a Refresh, else it will cause a WDTRST to be asserted.
Page 240: Multiplication/Division Unit
XC886/888CLM Multiplication/Division Unit Multiplication/Division Unit The Multiplication/Division Unit (MDU) provides fast 16-bit multiplication, 16-bit and 32-bit division as well as shift and normalize features. It has been integrated to support the XC886/888 Core in real-time control applications, which require fast mathematical computations.
Page 241: Functional Description
XC886/888CLM Multiplication/Division Unit 10.1 Functional Description The MDU can be regarded as a special coprocessor for multiplication, division, normalization and shift. Its operation can be divided into three phases (see Figure 10-1): Phase one: Load MDx registers In this phase, the operands are loaded into the MDU Operand (MDx) registers by the CPU.
Page 242: Division Operation
XC886/888CLM Multiplication/Division Unit 10.1.1 Division Operation The MDU supports the truncated division operation, which is also the ISO C99 standard and the popular choice among modern processors. The division and modulus functions of the truncated division are related in the following way: If q = D div d and r = D mod d then D = q * d + r...
Page 243: Busy Flag
XC886/888CLM Multiplication/Division Unit 10.1.4 Busy Flag A busy flag is provided to indicate the MDU is still performing a calculation. The flag MDUSTAT.BSY is set at the start of a calculation and cleared after the calculation is completed at the end of phase two. It is also cleared when the error flag is set. If a second operation needs to be executed, the status of the busy flag will be polled first and only when it is not set, can the start bit be written and the second operation begin.
Page 244: Low Power Mode
XC886/888CLM Multiplication/Division Unit reset IRDY int_reset_SW Completion of & Calculation to INT_O0 to INT_O1 & Occurrence of Error reset IERR int_reset_SW Figure 10-2 Interrupt Generation 10.3 Low Power Mode If the MDU functionality is not required at all, it can be completely disabled by gating off its clock input for maximal power reduction.
Page 245: Register Map
XC886/888CLM Multiplication/Division Unit 10.4 Register Map Table 10-2 lists the MDU registers with their addresses: Table 10-2 MDU Registers Address Name MDUCON (mapped) MDU Control Register MDUSTAT (mapped) MDU Status Register MD0/MR0 (mapped) MDU Data/Result Register 0 MD1/MR1 (mapped) MDU Data/Result Register 1 MD2/MR2 (mapped) MDU Data/Result Register 2...
Page 246: Register Description
XC886/888CLM Multiplication/Division Unit 10.5 Register Description The 14 SFRs of the MDU consist of a control register MDUCON, a status register MDUSTAT and 2 sets of data registers, MD0 to MD5 (which contain the operands) and MR0 to MR5 (which contain the results). Depending on the type of operation, the individual MDx and MRx registers assume specific roles as summarized in Table 10-3...
Page 247 XC886/888CLM Multiplication/Division Unit • D’or: Divisor, 2nd operand of division • M’and: Multiplicand, 1st operand of multiplication • M’or: Multiplicator, 2nd operand of multiplication • Pr: Product, result of multiplication • Rem: Remainder • Quo: Quotient, result of division • ...L: means that this byte is the least significant of the 16-bit or 32-bit operand •...
Page 248: Operand And Result Registers
XC886/888CLM Multiplication/Division Unit 10.5.1 Operand and Result Registers The MDx and MRx registers are used to store the operands and results of a calculation. MD4 and MR4 are also used as input and output control registers for shift and normalize operations.
Page 249 XC886/888CLM Multiplication/Division Unit Field Bits Type Description SCTR Shift Counter The count written to SCTR determines the number of shifts to be performed during a shift operation. Shift Direction Selects shift left operation. Selects shift right operation. Reserved Should be written with 0. Returns undefined data if read.
Page 250: Control Register
XC886/888CLM Multiplication/Division Unit 10.5.2 Control Register Register MDUCON contains control bits that select and start the type of operation to be performed. MDUCON MDU Control Register Reset Value: 00 RSEL START OPCODE Field Bits Type Description OPCODE Operation Code 0000 Unsigned 16-bit Multiplication 0001 Unsigned 16-bit/16-bit Division 0010 Unsigned 32-bit/16-bit Division 0011 32-bit Logical Shift L/R...
Page 251 XC886/888CLM Multiplication/Division Unit Field Bits Type Description Interrupt Enable The interrupt is disabled. The interrupt is enabled. Note: Write access to MDUCON is not allowed when the busy flag MDUSTAT.BSY is set during the calculation phase. Note: Writing reserved opcode values to MDUCON results in an error condition when MDUCON.START bit is set to 1.
Page 252: Status Register
XC886/888CLM Multiplication/Division Unit 10.5.3 Status Register Register MDUSTAT contains the status flags of the MDU. MDUSTAT MDU Status Register Reset Value: 00 IERR IRDY Field Bits Type Description IRDY Interrupt on Result Ready The bit IRDY is set by hardware and reset by software.
Page 253: Cordic Coprocessor
XC886/888CLM CORDIC Coprocessor CORDIC Coprocessor The CORDIC algorithm is a useful convergence method for computing trigonometric, linear, hyperbolic and related functions. It allows performance of vector rotation not only in the Euclidian plane, but also in the Linear and Hyperbolic planes. The CORDIC algorithm is an iterative process where truncation errors are inherent.
Page 254: Features
XC886/888CLM CORDIC Coprocessor 11.1 Features • Modes of operation – Supports all CORDIC operating modes for solving circular (trigonometric), linear (multiply-add, divide-add) and hyperbolic functions – Integrated look-up tables (LUTs) for all operating modes • Circular vectoring mode: Extended support for values of initial X and Y data up to full range of [-2 -1)] for solving angle and magnitude •...
Page 255: Functional Description
XC886/888CLM CORDIC Coprocessor 11.2 Functional Description The following sections describe the function of the CORDIC Coprocessor. 11.2.1 Operation of the CORDIC Coprocessor The CORDIC Coprocessor can be used for the circular (trigonometric), linear (multiply- add, divide-add) or hyperbolic function, in either rotation or vectoring mode. The modes are selectable by software via the CD_CON control register.
Page 256: Interrupt
XC886/888CLM CORDIC Coprocessor 11.2.2 Interrupt The End-of-Calculation (EOC) is the only interrupt source of the CORDIC Coprocessor. If interrupt is enabled by CD_STATC.INT_EN = 1, an interrupt request signal is activated at the end of CORDIC calculation and also indicated by the CD_STATC.EOC flag. If not cleared by software, the EOC flag remains set until cleared by hardware when a read access is performed to the low byte of Z result data (DMAP = 0).
Page 257: Cordic Coprocessor Operating Modes
XC886/888CLM CORDIC Coprocessor 11.2.4 CORDIC Coprocessor Operating Modes Table 11-2 gives an overview of the CORDIC Coprocessor operating modes. In this table, represent the initial data, while represent the final final final final result data when all processing is complete and BSY is no longer active. The CORDIC equations are: ·...
Page 258 XC886/888CLM CORDIC Coprocessor Table 11-2 CORDIC Coprocessor Operating Modes and Corresponding Result Data (cont’d) Function Rotation Mode Vectoring Mode Hyperbolic = k[ cosh( sinh( )] / = k sqrt( ) / MPS final final = -1 final = atanh(2 = k[ cosh( sinh( )] /...
Page 259: Domains Of Convergence
XC886/888CLM CORDIC Coprocessor i = 1, 2, ..., 15, such that angles in the range [-π,((2 -1)/2 )π] are represented by integer values ranging [-2 -1)]. Therefore, Z data is limited (not considering domain of convergence) to represent angles [-π,((2 -1)/2 )π] for these CORDIC functions.
Page 260: Overflow Considerations
XC886/888CLM CORDIC Coprocessor Circular Vectoring Mode: The full range of X and Y inputs [-2 -1)] are supported, while Z initial value should satisfy |Z| ≤ π / 2 to prevent possible Z result data overflow. Note: Considerations should also be given to function limitations such as the meaning of the result data, e.g.
Page 261: Accuracy Of Cordic Coprocessor
XC886/888CLM CORDIC Coprocessor fixed input and result data form of S4.11 (signed 4Q16) which is a fraction with 11 decimal places. Refer to Chapter 11.2.3 for details on data normalization. 11.2.6 Accuracy of CORDIC Coprocessor Each CORDIC calculation involves a fixed number of 16 CORDIC iterations starting from iteration 0.
Page 262 XC886/888CLM CORDIC Coprocessor Table 11-3 Normalized Deviation of a Calculation Mode X Normalized Deviation Y or Z Normalized Deviation ) ≥ 600] Circular Input conditions: Useful Domain and [(1.64676/2)·sqrt(X Vectoring 0 : 50.8317% 0 : 55.8702% 1 : 49.1683% 1 : 44.1298% ND for X ≤...
Page 263: Performance Of Cordic Coprocessor
XC886/888CLM CORDIC Coprocessor Table 11-3 Normalized Deviation of a Calculation (cont’d) Mode X Normalized Deviation Y or Z Normalized Deviation Input conditions: Useful Domain (|Z| ≤ 1.11rad, Y = 0) Hyperbolic Rotation 0 : 14.9401% 0 : 40.4787% 1 : 31.6474% 1 : 40.6711% 2 : 23.7692% 2 : 11.9209%...
Page 264: The Cordic Coprocessor Kernel
XC886/888CLM CORDIC Coprocessor 11.3 The CORDIC Coprocessor Kernel The CORDIC Coprocessor consists of data registers for holding the X, Y and Z values, in twos complement format. Three shift registers are used to shift the values in the X and Y registers by the number of iterations and to generate the emulated LUT data for the linear function.
Page 265: Linear Function Emulated Look-Up Table
XC886/888CLM CORDIC Coprocessor Table 11-5 Precomputed Scaled Values for atanh(2 Iteration No. Scaled atanh(2 ) in hex Iteration No. Scaled atanh(2 ) in hex i = 0 i = 8 i = 1 16618 i = 9 i = 2 A681 i = 10 i = 3...
Page 266: Low Power Mode
XC886/888CLM CORDIC Coprocessor 11.4 Low Power Mode If the CORDIC Coprocessor functionality is not required at all, it can be completely disabled by gating off its clock input for maximal power reduction. This is done by setting bit CDC_DIS in register PMCON1 as described below. Refer to Chapter 8.1.4 for details on peripheral clock management.
Page 267: Register Map
XC886/888CLM CORDIC Coprocessor 11.5 Register Map The CORDIC Coprocessor registers are located in the mapped Special Function Register (SFR) area. Table 11-6 lists the addresses of these registers. Note: All CORDIC Coprocessor register names described in this section shall be referenced fully with the module name prefix “CD_”.
Page 268: Register Description
XC886/888CLM CORDIC Coprocessor 11.6 Register Description 11.6.1 Control Register The CD_CON register allows for the general control of the CORDIC Coprocessor. Write action to this register while CD_STATC.BSY is set has no effect. CD_CON CORDIC Control Register Reset Value: 62 X_USIGN ST_MODE ROTVEC MODE Field...
Page 269 XC886/888CLM CORDIC Coprocessor Field Bits Type Description X_USIGN Result Data Format for X in Circular Vectoring Mode When reading the X result data with DMAP = 0, X data has a data format of: Signed, twos complement Unsigned (default) With this bit set, the MSB bit of the X result data is processed as a data bit instead of a sign bit.
Page 270: Status And Data Control Register
XC886/888CLM CORDIC Coprocessor 11.6.2 Status and Data Control Register The CD_STATC register is bit-addressable, and generally reflects the status of the CORDIC Coprocessor. The register also contain bits for data control, as well as for interrupt control. CD_STATC CORDIC Status and Data Control Register Reset Value: 00 KEEPZ KEEPY...
Page 271: Data Registers
XC886/888CLM CORDIC Coprocessor Field Bits Type Description KEEPX Last X Result as Initial Data for New Calculation If set, a new calculation will use as initial data, the value of the result from the previous calculation. In other words, the respective kernel data register will not be overwritten by the contents of the shadow data register at the beginning of new calculation.
Page 272 XC886/888CLM CORDIC Coprocessor Field Bits Type Description DATAL Low Byte Data Write to this byte always writes to the low byte of the corresponding shadow data register. New data may be written during an ongoing CORDIC calculation. For read, DMAP=0: Result data from kernel data byte DMAP=1: Initial data from the shadow data byte CD_CORDxH (x = X, Y or Z) CORDIC x Data High Byte...
Page 273: Serial Interfaces
XC886/888CLM Serial Interfaces Serial Interfaces The XC886/888 contains three serial interfaces, which consists of two Universal Asynchronous Receivers/Transmitters (UART and UART1) and a High-Speed Synchronous Serial Interface (SSC), for serial communication with external devices. Additionally, the UART module can be used to support the Local Interconnect Network (LIN) protocol.
Page 274: Uart
XC886/888CLM Serial Interfaces 12.1 UART The UART provides a full-duplex asynchronous receiver/transmitter, i.e., it can transmit and receive simultaneously. It is also receive-buffered, i.e., it can commence reception of a second byte before a previously received byte has been read from the receive register.
Page 275: Mode 1, 8-Bit Uart, Variable Baud Rate
XC886/888CLM Serial Interfaces Reception is started by the condition REN = 1 and RI = 0. At the start of the reception cycle, 11111110 is written to the receive shift register. In each machine cycle that follows, the contents of the shift register are shifted left one position and the value sampled on the RXD line in the same machine cycle is shifted in from the right.
Page 276 XC886/888CLM Serial Interfaces Transmit Receive Figure 12-1 Serial Interface, Mode 1, Timing Diagram User’s Manual 12-4 V1.3, 2010-02 Serial Interfaces, V 1.0...
Page 277: Mode 2, 9-Bit Uart, Fixed Baud Rate
XC886/888CLM Serial Interfaces 12.1.1.3 Mode 2, 9-Bit UART, Fixed Baud Rate In mode 2, the UART behaves as a 9-bit serial port. A start bit (0), 8 data bits plus a programmable 9th bit and a stop bit (1) are transmitted on TXD or received on RXD. The 9th bit for transmission is taken from TB8 (SCON.3) while for reception, the 9th bit received is placed in RB8 (SCON.2).
Page 278 XC886/888CLM Serial Interfaces Transmit Receive Figure 12-2 Serial Interface, Modes 2 and 3, Timing Diagram User’s Manual 12-6 V1.3, 2010-02 Serial Interfaces, V 1.0...
Page 279: Multiprocessor Communication
XC886/888CLM Serial Interfaces 12.1.2 Multiprocessor Communication Modes 2 and 3 have a special provision for multiprocessor communication using a system of address bytes with bit 9 = 1 and data bytes with bit 9 = 0. In these modes, 9 data bits are received. The 9th data bit goes into RB8. The communication always ends with one stop bit.
Page 280: Uart Register Description
XC886/888CLM Serial Interfaces 12.1.3 UART Register Description Both UART modules contain the two Special Function Registers (SFRs), SCON and SBUF. SCON is the control register and SBUF is the data register. On reset, both SCON and SBUF return 00 . The serial port control and status register is the SFR SCON. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8) and the serial port interrupt bits (TI and RI).
Page 281 XC886/888CLM Serial Interfaces Field Bits Type Description Transmit Interrupt Flag This is set by hardware at the end of the 8th bit in mode 0, or at the beginning of the stop bit in modes 1, 2, and 3. Must be cleared by software. Serial Port Receiver Bit 9 In modes 2 and 3, this is the 9th data bit received.
Page 282: Baud Rate Generation
XC886/888CLM Serial Interfaces 12.1.4 Baud Rate Generation There are several ways to generate the baud rate clock for the serial ports, depending on the mode in which they are operating. The baud rates in modes 0 and 2 are fixed, so they use the •...
Page 283: Dedicated Baud-Rate Generator
XC886/888CLM Serial Interfaces Field Bits Type Description SMOD Double Baud Rate Enable Do not double the baud rate of serial interface in modes 1, 2 and 3. Double the baud rate of serial interface in mode 2, and in modes 1 and 3 only if Timer 1 is used as variable baud rate source.
Page 284 XC886/888CLM Serial Interfaces occurs, the auto-reload action will be delayed until the first instruction cycle after setting BCON.R. Fractional Divider 8-Bit Reload Value FDSTEP FDEN&FDM Adder 8-Bit Baud Rate Timer FDRES (overflow) FDEN PCLK Prescaler NDOV ‘0’ Figure 12-3 Baud-rate Generator Circuitry The baud rate ( ) value is dependent on the following parameters: •...
Page 285 XC886/888CLM Serial Interfaces The following formulas calculate the final baud rate without (see Equation (12.2)) and with the fractional divider (see Equation (12.3)), respectively: (12.2) PCLK BRPRE baud rate × > where VALUE BRPRE (BR_VALUE (12.3) STEP PCLK baud rate BRPRE (BR_VALUE The maximum baud rate that can be generated is limited to...
Page 286 XC886/888CLM Serial Interfaces Table 12-3 Deviation Error for UART with Fractional Divider enabled Prescaling Factor Reload Value STEP Deviation PCLK BRPRE (BR_VALUE + 1) Error 26.67 MHz 10 (A 177 (B1 +0.03 % 24 MHz 10 (A 197 (C5 +0.20 % 16 MHz 8 (8 236 (EC...
Page 287 XC886/888CLM Serial Interfaces Figure 12-4 shows the operation in fractional divider mode with a reload value of STEP = 8D (factor of 141/256 = 0.55). STEP = 8D = 0.55 x f RESULT Figure 12-4 Fractional Divider Mode Timing Note: In fractional divider mode, f will have a maximum jitter of one f clock period.
Page 288 XC886/888CLM Serial Interfaces STEP Reload Reload Reload RESULT Figure 12-5 Normal Mode Timing Baud Rate Generator Registers Both UART and UART1 module baud rate generators contain the five SFRs, BG, BCON, FDCON, FDSTEP and FDRES. The functionality of these registers are described in the following pages.
Page 289 XC886/888CLM Serial Interfaces Field Bits Type Description BRDIS Break/Synch Detection Disable Break/Synch detection is enabled. Break/Synch detection is disabled. BGSEL [7:6] Baud Rate Select for Detection For different values of BGSEL, the baud rate range for detection is defined by the following formula: /(2184*2^BGSEL)<...
Page 290 XC886/888CLM Serial Interfaces When =24 MHz, the baud rate range between 1.4 kHz to 333.3 kHz can be PCLK detected. In order to increase the detection accuracy of the baud rate, the following examples serve as a guide to select BGSEL value: •...
Page 291 XC886/888CLM Serial Interfaces Register FDCON contains the control and status bits for the fractional divider, and also the status flags used in LIN protocol support (see Section 12.2.1). FDCON Fractional Divider Control Register Reset Value: 00 SYNEN ERRSYN EOFSYN NDOV FDEN Field Bits...
Page 292: Timer 1
XC886/888CLM Serial Interfaces Field Bits Type Description SYNEN End of SYN Byte and SYN Byte Error Interrupts Enable End of SYN Byte and SYN Byte Error Interrupts are not enabled. End of SYN Byte and SYN Byte Error Interrupts are enabled. Baud-rate Generator Select Baud-rate generator is selected.
Page 293 XC886/888CLM Serial Interfaces Register FDRES contains the 8-bit RESULT value for the fractional divider. FDRES Fractional Divider Result Register Reset Value: 00 RESULT Field Bits Type Description RESULT [7:0] RESULT Value In normal divider mode, RESULT acts as reload counter (addition +1). In fractional divider mode, this bit field contains the result of the addition RESULT+STEP.
Page 294 XC886/888CLM Serial Interfaces 12.1.4.3 Timer 1 In modes 1 and 3 of UART module, Timer 1 can be used for generating the variable baud rates. In theory, this timer could be used in any of its modes. But in practice, it should be set into auto-reload mode (Timer 1 mode 2), with its high byte set to the appropriate value for the required baud rate.
Page 295: Port Control
XC886/888CLM Serial Interfaces 12.1.5 Port Control The UART modules shift in data through RXD which can be selected from three different sources, RXD_0, RXD_1 and RXD_2. This selection is performed by the SFR bits MODPISEL.URRIS MODPISEL.URRISH UART module, MODPISEL1.UR1RIS in UART1 module. MODPISEL Peripheral Input Select Register Reset Value: 00...
Page 296: Low Power Mode
XC886/888CLM Serial Interfaces Field Bits Type Description [6:5] Reserved Returns 0 if read; should be written with 0. 12.1.6 Low Power Mode If the UART1 module functionality is not required at all, it can be completely disabled by gating off its clock input for maximal power reduction. This is done by setting bit UART1_DIS in register PMCON2 as described below.
Page 297: Register Map
XC886/888CLM Serial Interfaces 12.1.7 Register Map All UART1 module register names described in the previous sections are referenced in other chapters of this document with the module name prefix “UART1_”, e.g., UART1_SCON. However, all UART module registers are not referenced by any prefix. Besides the SCON and SBUF registers, which can be accessed from both the standard (non-mapped) and mapped SFR area, the rest of the UART module’s SFRs are located in SCU page 0 of the standard area.
Page 298: Lin
XC886/888CLM Serial Interfaces 12.2 The UART module can be used to support the Local Interconnect Network (LIN) protocol for both master and slave operations. The LIN baud rate detection feature, which consists of the hardware logic for Break and Synch Byte detection, provides the capability to detect the baud rate within LIN protocol using Timer 2.
Page 299 XC886/888CLM Serial Interfaces Byte field Start Stop (bit 0) (bit 7) Figure 12-7 The Structure of Byte Field The break is used to signal the beginning of a new frame. It is the only field that does not comply with Figure 12-7.
Page 300: Lin Header Transmission
XC886/888CLM Serial Interfaces The slave task will receive and transmit data when an appropriate ID is sent by the master: 1. Slave waits for Synch Break 2. Slave synchronizes on Synch Byte 3. Slave snoops for ID 4. According to ID, slave determines whether to receive or transmit data, or do nothing 5.
Page 301: Baud Rate Detection Of Lin
XC886/888CLM Serial Interfaces 12.2.2.2 Baud Rate Detection of LIN The LIN baud rate detection feature provides the capability to detect the baud rate within the LIN protocol using Timer 2. Initialization consists of: • Serial port of the microcontroller set to Mode 1 (8-bit UART, variable baud rate) for communication.
Page 302 XC886/888CLM Serial Interfaces If the Break Field Flag FDCON.BRK is set, software may continue to capture 4/6/8 bits of SYN byte. Finally, the End of SYN Byte Flag (FDCON.EOFSYN) is set, Timer 2 is stopped. T2 Reload/Capture register (RC2H/L) is the time taken for 2/4/6/8 bits according to the implementation.
Page 303: High-Speed Synchronous Serial Interface
XC886/888CLM Serial Interfaces 12.3 High-Speed Synchronous Serial Interface The SSC supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSC internally (master mode) using its own 16-bit baud-rate generator, or can be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable.
Page 304: General Operation
XC886/888CLM Serial Interfaces 12.3.1 General Operation 12.3.1.1 Operating Mode Selection The operating mode of the serial channel SSC is controlled by its control register CON. This register has a double function: • During programming (SSC disabled by CON.EN = 0), it provides access to a set of control bits •...
Page 305: Full-Duplex Operation
XC886/888CLM Serial Interfaces The Data Width Selection supports the transfer of frames of any data length, from 2-bit “characters” up to 8-bit “characters”. Starting with the LSB (CON.HB = 0) allows communication with SSC devices in synchronous mode or with serial interfaces such as the one in 8051.
Page 306 XC886/888CLM Serial Interfaces TXD is the transmit line; the receive line is connected to its data input line RXD; the shift clock line is either MS_CLK or SS_CLK. Only the device selected for master operation generates and outputs the shift clock on line MS_CLK. Since all slaves receive this clock, their pin SCLK must be switched to input mode.
Page 307 XC886/888CLM Serial Interfaces • The slaves use open drain output on MRST. This forms a wired-AND connection. The receive line needs an external pull-up in this case. Corruption of the data on the receive line sent by the selected slave is avoided when all slaves not selected for transmission to the master send ones only.
Page 308: Half-Duplex Operation
XC886/888CLM Serial Interfaces be prepared via the related ALTSEL register, or the output latch must be loaded with the clock idle level. 12.3.1.3 Half-Duplex Operation In a half-duplex mode, only one data line is necessary for both receiving and transmitting of data.
Page 309: Continuous Transfers
XC886/888CLM Serial Interfaces 12.3.1.4 Continuous Transfers When the transmit interrupt request flag is set, it indicates that the transmit buffer TB is empty and ready to be loaded with the next transmit data. If TB has been reloaded by the time the current transmission is finished, the data is immediately transferred to the shift register and the next transmission will start without any additional delay.
Page 310: Port Control
XC886/888CLM Serial Interfaces 12.3.1.5 Port Control The SSC uses three lines to communicate with the external world as shown in Figure 12-15. Pin SCLK serves as the clock line, while pins MRST and MTSR serve as the serial data input/output lines. Interrupt System MRSTA...
Page 311: Baud Rate Generation
XC886/888CLM Serial Interfaces 12.3.1.6 Baud Rate Generation The serial channel SSC has its own dedicated 16-bit baud-rate generator with 16-bit reload capability, allowing baud rate generation independent of the timers. Figure 12-16 shows the baud-rate generator. 16-Bit Reload Register MS_CLK/SS_CLK PCLK 16-Bit Counter in Master Mode...
Page 312 XC886/888CLM Serial Interfaces Table 12-6 Typical Baud Rates of the SSC ( = 24 MHz) hw_clk Reload Value Baud Rate (= Deviation MS_CLK/SS_CLK 0000 12 MBaud (only in Master mode) 0.0% 0001 6 MBaud 0.0% 0008 1.3 MBaud 0.0% 000B 1 MBaud 0.0% 000F...
Page 313: Error Detection Mechanisms
XC886/888CLM Serial Interfaces 12.3.1.7 Error Detection Mechanisms The SSC is able to detect four different error conditions. Receive Error and Phase Error are detected in all modes; Transmit Error and Baud Rate Error apply only to slave mode. When an error is detected, the respective error flag is/can be set and an error interrupt request will be generated by activating the Error Interrupt Request line (EIR) (see Figure 12-17).
Page 314 XC886/888CLM Serial Interfaces A Phase Error (master or slave mode) is detected when the incoming data at pin MRST (master mode) or MTSR (slave mode), sampled with the same frequency as the module clock, changes between one cycle before and two cycles after the latching edge of the shift clock signal SCLK.
Page 315: Interrupts
XC886/888CLM Serial Interfaces 12.3.2 Interrupts An overview of the various interrupts in SSC is provided in Table 12-7. Table 12-7 SSC Interrupt Sources Interrupt Signal Description Transmission Indicates that the transmit buffer can be reloaded with new starts data. Transmission The configured number of bits have been transmitted and ends shifted to the receive buffer.
Page 316: Low Power Mode
XC886/888CLM Serial Interfaces 12.3.3 Low Power Mode If the SSC functionality is not required at all, it can be completely disabled by gating off its clock input for maximal power reduction. This is done by setting bit SSC_DIS in register PMCON1 as described below. Refer to Chapter 8.1.4 for details on peripheral clock management.
Page 317: Register Description
XC886/888CLM Serial Interfaces 12.3.5 Register Description All SSC register names described in this section are referenced in other chapters of this document with the module name prefix “SSC_”, e.g., SSC_PISEL. 12.3.5.1 Port Input Select Register The PISEL register controls the receiver input selection of the SSC module. PISEL Port Input Select Register Reset Value: 00...
Page 318: Configuration Register
XC886/888CLM Serial Interfaces 12.3.5.2 Configuration Register The operating mode of the serial channel SSC is controlled by the control register CON. This register contains control bits for mode and error check selection, and status flags for error identification. Depending on bit EN, either control functions or status flags and master/slave control are enabled.
Page 319 XC886/888CLM Serial Interfaces CONH Control Register High Reset Value: 00 AREN Field Bits Type Description Transmit Error Interrupt Enable Transmit error interrupt is disabled Transmit error interrupt is enabled Receive Error Enable Receive error interrupt is disabled Receive error interrupt is enabled Phase Error Enable Phase error interrupt is disabled Phase error interrupt is enabled...
Page 320 XC886/888CLM Serial Interfaces CON.EN = 1: Operating Mode CONL Control Register Low Reset Value: 00 Field Bits Type Description [3:0] Bit Count Field 0001 - 1111 Shift counter is updated with every shifted bit [7:4] Reserved Returns 0 if read; should be written with 0. CONH Control Register High Reset Value: 00...
Page 321 XC886/888CLM Serial Interfaces Field Bits Type Description Baud rate Error Flag No error More than factor 2 or 0.5 between slave’s actual and expected baud rate Busy Flag Set while a transfer is in progress Master Select Bit Slave mode. Operate on shift clock received via SCLK.
Page 322: Baud Rate Timer Reload Register
XC886/888CLM Serial Interfaces 12.3.5.3 Baud Rate Timer Reload Register The SSC baud rate timer reload register BR contains the 16-bit reload value for the baud rate timer. Baud Rate Timer Reload Register Low Reset Value: 00 BR_VALUE Field Bits Type Description BR_VALUE [7:0] Baud Rate Timer/Reload Register Value [7:0]...
Page 323: Transmit And Receive Buffer Register
XC886/888CLM Serial Interfaces 12.3.5.4 Transmit and Receive Buffer Register The SSC transmitter buffer register TB contains the transmit data value. Transmitter Buffer Register Low Reset Value: 00 TB_VALUE Field Bits Type Description TB_VALUE [7:0] Transmit Data Register Value TB_VALUE is the data value to be transmitted. Unselected bits of TB are ignored during transmission.
Page 324 XC886/888CLM Serial Interfaces User’s Manual 12-52 V1.3, 2010-02 Serial Interfaces, V 1.0...
Page 325: Timers
XC886/888CLM Timers Timers The XC886/888 provides four 16-bit timers, Timer 0, Timer 1, Timer 2 and Timer 21. They are useful in many timing applications such as measuring the time interval between events, counting events and generating signals at regular intervals. In particular, Timer 1 can be used as the baud-rate generator for the on-chip serial port.
Page 326: Timer 0 And Timer 1
XC886/888CLM Timers 13.1 Timer 0 and Timer 1 Timer 0 and Timer 1 can function as both timers or counters. When functioning as a timer, Timer 0 and Timer 1 are incremented every machine cycle, i.e. every 2 input clocks (or 2 PCLKs). When functioning as a counter, Timer 0 and Timer 1 are incremented in response to a 1-to-0 transition (falling edge) at their respective external input pins, T0 or T1.
Page 327 XC886/888CLM Timers 13.1.2 Timer Modes Timers 0 and 1 are fully compatible and can be configured in four different operating modes, as shown in Table 13-1. The bit field TxM in register TMOD selects the operating mode to be used for each timer. In modes 0, 1 and 2, the two timers operate independently, but in mode 3, their functions are specialized.
Page 328 XC886/888CLM Timers 13.1.2.1 Mode 0 Putting either Timer 0 or Timer 1 into mode 0 configures it as an 8-bit timer/counter with a divide-by-32 prescaler. Figure 13-1 shows the mode 0 operation. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the timer overflow flag TFx.
Page 329: Mode 1
XC886/888CLM Timers 13.1.2.2 Mode 1 Mode 1 operation is similar to that of mode 0, except that the timer register runs with all 16 bits. Mode 1 operation for Timer 0 is shown in Figure 13-2. PCLK T0S = 0 (8 Bits) (8 Bits) Interrupt...
Page 330 XC886/888CLM Timers 13.1.2.3 Mode 2 In Mode 2 operation, the timer is configured as an 8-bit counter (TLx) with automatic reload, as shown in Figure 13-3 for Timer 0. An overflow from TLx not only sets TFx, but also reloads TLx with the contents of THx that has been preset by software.
Page 331: Mode 3
XC886/888CLM Timers 13.1.2.4 Mode 3 In mode 3, Timer 0 and Timer 1 behave differently. Timer 0 in mode 3 establishes TL0 and TH0 as two separate counters. Timer 1 in mode 3 simply holds its count. The effect is the same as setting TR1 = 0 The logic for mode 3 operation for Timer 0 is shown in Figure 13-4.
Page 332: Port Control
XC886/888CLM Timers 13.1.3 Port Control When functioning as an event counter, Timer 0 and 1 count 1-to-0 transitions at their external input pins, T0 and T1, which can be selected from two different sources, T0_0 and T0_1 for Timer 0, and T1_0 and T1_1 for Timer 1. This selection is performed by the SFR bits MODPISEL2.T0IS and MODPISEL2.T1IS.
Page 333: Register Map
XC886/888CLM Timers 13.1.4 Register Map Seven SFRs control the operations of Timer 0 and Timer 1. They can be accessed from both the standard (non-mapped) and mapped SFR area. Table 13-2 lists the addresses of these SFRs. Table 13-2 Register Address Register TCON...
Page 334: Register Description
XC886/888CLM Timers 13.1.5 Register Description The low bytes(TL0, TL1) and high bytes(TH0, TH1)of both Timer 0 and Timer 1 can be combined to a one-timer configuration depending on the mode used. Register TCON controls the operations of Timer 0 and Timer 1. The operating modes of both timers are selected using register TMOD.
Page 335 XC886/888CLM Timers Field Bits Type Description THx.VAL(x = 0, 1) 7:0 Timer 0/1 High Register OM0 THx holds the 8-bit timer value. OM1 THx holds the higher 8-bit part of the 16-bit timer value. OM2 THx holds the 8-bit reload value. OM3 TH0 holds the 8-bit timer value;...
Page 336 XC886/888CLM Timers TMOD Timer Mode Register Reset Value: 00 GATE1 GATE0 Field Bits Type Description [1:0] Mode select bits 13-bit timer (M8048 compatible mode) 16-bit timer 8-bit auto-reload timer Timer 0 is split into two halves. TL0 is an 8- bit timer controlled by the standard Timer 0 control bits, and TH0 is the other 8-bit timer controlled by the standard Timer 1 control...
Page 337 XC886/888CLM Timers Field Bits Type Description Timer 1 Selector Input is from internal system clock Input is from T1 pin GATE1 Timer Gate Flag Timer 1 will only run if TCON.TR1 = 1 (software control) Timer 1 will only run if EXINT1 pin = 1 (hardware control) and TCON.TR1 is set IEN0 Interrupt Enable Register...
Page 338: Timer 2 And Timer 21
XC886/888CLM Timers 13.2 Timer 2 and Timer 21 Timer 2 and Timer 21 are 16-bit general purpose timers that are functionally identical. Both have two modes of operation, a 16-bit auto-reload mode and a 16-bit one channel capture mode and can function as a timer or counter in each of its modes. As a timer, the timers count with an input clock of PCLK/12 (if prescaler is disabled).
Page 339: Up/Down Count Enabled
XC886/888CLM Timers negative/positive transition at pin T2EX caused the reload, bit EXF2 in register T2CON is set. In either case, an interrupt is generated to the core and the timer proceeds to its next count sequence. The EXF2 flag, similar to the TF2, must be cleared by software. If bit T2RHEN is set, Timer 2 is started by first falling edge/rising edge at pin T2EX, which is defined by bit T2REGS.
Page 340 XC886/888CLM Timers A logic 1 at pin T2EX sets the Timer 2 to up counting mode. The timer, therefore, counts up to a maximum of FFFF . Upon overflow, bit TF2 is set and the timer register is reloaded with a 16-bit reload value of the RC2 register. A fresh count sequence is started and the timer counts up from this reload value as in the previous count sequence.
Page 341 XC886/888CLM Timers FFFF EXF2 (Down count reload) PREN Underflow PCLK T2PRE Timer 2 C/T2 = 0 THL2 Interrupt C/T2 = 1 16-bit Comparator Overflow T2EX Figure 13-6 Auto-Reload Mode (DCEN = 1) User’s Manual 13-17 V1.3, 2010-02 Timers, V 1.0...
Page 342: Capture Mode
XC886/888CLM Timers 13.2.3 Capture Mode In order to enter the 16-bit capture mode, bits CP/RL2 and EXEN2 in register T2CON must be set. In this mode, the down count function must remain disabled. The timer functions as a 16-bit timer and always counts up to FFFF , after which, an overflow condition occurs.
Page 343: Count Clock
XC886/888CLM Timers PREN PCLK T2PRE C/T2=0 THL2 C/T2=1 Overflow TF 2 Timer 2 Interrupt EXF2 EXEN2 T2EX Figure 13-7 Capture Mode 13.2.4 Count Clock The count clock for the auto-reload mode is chosen by the bit C/T2 in register T2CON. If C/T2 = 0, a count clock of PCLK/12 (if prescaler is disabled) is used for the count operation.
Page 344: External Interrupt Function
XC886/888CLM Timers 13.2.5 External Interrupt Function While the timer/counter function is disabled (TR2 = 0), it is still possible to generate a Timer 2 interrupt to the core via an external event at T2EX, as long as Timer 2 remains enabled (PMCON1.T2_DIS = 0).
Page 345: Low Power Mode
XC886/888CLM Timers 13.2.7 Low Power Mode If the Timer 2 and Timer 21 functionalities are not required at all, they can be completely disabled by gating off their clock inputs for maximal power reduction. This is done by setting bits T2_DIS in register PMCON1 and T21_DIS in register PMCON2 as described below.
Page 346: Module Suspend Control
XC886/888CLM Timers 13.2.8 Module Suspend Control Timer 2 and Timer 21 can be configured to stop their counting when the OCDS enters monitor mode (see Chapter 17.3) by setting their respective module suspend bits, T2SUSP and T21SUSP, in SFR MODSUSP. MODSUSP Module Suspend Control Register Reset Value: 01...
Page 347: Register Map
XC886/888CLM Timers 13.2.9 Register Map Timer 2 and Timer 21 contain an identical set of SFRs. All Timer 2 register names described in the following sections are referenced in other chapters of this document with the module name prefix “T2_”, e.g., T2_T2CON, while those of Timer 21 are referenced with “T21_”, e.g., T21_T2CON.
Page 348: Register Description
XC886/888CLM Timers 13.2.10 Register Description Register T2MOD is used to configure Timer 2 for the various modes of operation. T2MOD Timer 2 Mode Register Reset Value: 00 T2REGS T2RHEN EDGESEL PREN T2PRE DCEN Field Bits Type Description DCEN Up/Down Counter Enable Up/Down Counter function is disabled.
Page 349 XC886/888CLM Timers Field Bits Type Description T2REGS Edge Select for Timer 2 External Start The falling edge at Pin T2EX is selected. The rising edge at Pin T2EX is selected. Register T2CON controls the operating modes of Timer 2. In addition, it contains the status flags for interrupt generation.
Page 350 XC886/888CLM Timers Field Bits Type Description EXF2 Timer 2 External Flag In capture/reload mode, this bit is set by hardware when a negative/positive transition occurs at pin T2EX, if bit EXEN2 = 1. This bit must be cleared by software. Note: When bit DCEN = 1 in auto-reload mode, no interrupt request to the core is generated.
Page 351 XC886/888CLM Timers Register RC2 is used for a 16-bit reload of the timer count upon overflow or a capture of current timer count depending on the mode selected. RC2L Timer 2 Reload/Capture Register Low Reset Value: 00 Field Bits Type Description [7:0] Reload/Capture Value [7:0] If CP/RL2 = 0, these contents are loaded into the...
Page 352 XC886/888CLM Timers Register T2 holds the current 16-bit value of the Timer 2 count. Timer 2 Register Low Reset Value: 00 THL2 Field Bits Type Description THL2 [7:0] Timer 2 Value [7:0] These bits indicate the current timer value. Timer 2 Register High Reset Value: 00 THL2 Field...
Page 353: Capture/Compare Unit 6
XC886/888CLM Capture/Compare Unit 6 Capture/Compare Unit 6 The Capture/Compare Unit 6 (CCU6) provides two independent timers (T12, T13), which can be used for Pulse Width Modulation (PWM) generation, especially for AC-motor control. The CCU6 also supports special control modes for block commutation and multi-phase machines.
Page 354 XC886/888CLM Capture/Compare Unit 6 module kernel compare channel 0 address dead- multi- decoder trap channel 1 time channel control control control channel 2 clock control start channel 3 compare interrupt control input / output control port control CCU6_block_diagram Figure 14-1 CCU6 Block Diagram User’s Manual 14-2 V1.3, 2010-02...
Page 355: Functional Description
XC886/888CLM Capture/Compare Unit 6 14.1 Functional Description 14.1.1 Timer T12 The timer T12 is built with three channels in capture/compare mode. The input clock for timer T12 can be from to a maximum of /128 and is configured by bit field CCU6 CCU6 T12CLK.
Page 356: Timer Configuration
XC886/888CLM Capture/Compare Unit 6 14.1.1.1 Timer Configuration Register T12 represents the counting value of timer T12. It can be written only while timer T12 is stopped. Write actions while T12 is running are not taken into account. Register T12 can always be read by software. In edge-aligned mode, T12 only counts up, whereas in center-aligned mode, T12 can count up and down.
Page 357: Switching Rules
XC886/888CLM Capture/Compare Unit 6 14.1.1.3 Switching Rules Compare actions take place in parallel for the three compare channels. Depending on the count direction, the compare matches have different meanings. In order to get the PWM information independent of the output levels, two different states have been introduced for the compare actions: the active state and the passive state.
Page 358: Compare Mode Of T12
XC886/888CLM Capture/Compare Unit 6 The switching rules are considered only while the timer is running. As a result, write actions to the timer registers while the timer is stopped do not lead to compare actions. 14.1.1.4 Compare Mode of T12 In compare mode, the registers CC6xR (x = 0 - 2) are the actual compare registers for T12.
Page 359 XC886/888CLM Capture/Compare Unit 6 period value compare value CC6xST Pin CC6x (CC6xPS=0, passive active passive PSL=0) Pin COUT6x (COUT6xPS=1, active passive active PSL=0) CCU6_T12_comp_states Figure 14-4 Compare States of Timer T12 Driving Driving Stage Stage CC60 CC60 high active low active COUT60 COUT60 high active...
Page 360: Duty Cycle Of 0% And 100
XC886/888CLM Capture/Compare Unit 6 For the hysteresis-like compare mode (MSEL6x = 1001 ) (see Section 14.1.1.9), the setting of the compare state bit is possible only while the corresponding input CCPOSx = 1 (inactive). If the hall sensor mode (MSEL6x = 1000 ) is selected (see Section 14.1.6), the...
Page 361: Capture Mode
XC886/888CLM Capture/Compare Unit 6 Center-aligned Edge-aligned CC6xST CC6xST DTCx_o CC6xST AND DTCx_o Pin CC6x (CC6xPS=0, PSL=0) Pin COUT6x (COUT6xPS=1, CC6xST AND DTCx_o PSL=0) Figure 14-6 PWM-signals with Dead-time Generation Register T12DTC controls the dead-time generation for the timer T12 compare channels.
Page 362: Single-Shot Mode
XC886/888CLM Capture/Compare Unit 6 CC6xSR registers. In order to work in capture mode, the capture pins must be configured as inputs. There are several ways to store the captured values in the registers. For example, in double register capture mode, the timer value is stored in the channel shadow register CC6xSR.
Page 363 XC886/888CLM Capture/Compare Unit 6 This mode can be used to introduce a timing-related behavior to a hysteresis controller. A standard hysteresis controller detects if a value exceeds a limit and switches its output according to the compare result. Depending on the operating conditions, the switching frequency and the duty cycle may change constantly.
Page 364: Timer T13
XC886/888CLM Capture/Compare Unit 6 14.1.2 Timer T13 The timer T13 is similar to timer T12, except that it has only one channel in compare mode. The counter can only count up (similar to the edge-aligned mode of T12). The input clock for timer T13 can be from to a maximum of /128 and is configured CCU6...
Page 365: Compare Mode
XC886/888CLM Capture/Compare Unit 6 • Bit T13R is set/reset by software by setting bit T13RS or T13RR. • In single-shot mode, if bit T13SSC = 1, the bit T13R is reset by hardware when T13 reaches its period value. • Bit fields T13TEC and T13TED select the trigger event that will set bit T13R for synchronization of different T12 compare events.
Page 366 XC886/888CLM Capture/Compare Unit 6 • a T12 compare event on channel 0 • a T12 compare event on channel 1 • a T12 compare event on channel 2 • any T12 compare event on channel 0, 1, or 2 • a period-match of T12 •...
Page 367: Modulation Control
XC886/888CLM Capture/Compare Unit 6 14.1.3 Modulation Control The modulation control part combines the different modulation sources (CC6x_T12_o COUT6x_T12_o are output signals that configured with CC6xPS/COUT6xPS; MOD_T13_o is the output signal after T13 Inverted Modulation (T13IM)). Each modulation source can be individually enabled per output line. Furthermore, the trap functionality is taken into account to disable the modulation of the corresponding output line during the trap state (if enabled).
Page 368 XC886/888CLM Capture/Compare Unit 6 As shown in Figure 14-12, the modulation control part for the T13-related output COUT63 combines the T13 output signal (COUT63_T13_o is the output signal that is configured by COUT63PS) and the enable bit ECT13O with the trap functionality. The output level of the passive state is selected by bit PSL63.
Page 369: Trap Handling
XC886/888CLM Capture/Compare Unit 6 Figure 14-13 shows a modulation control example for CC60 and COUT60. CC60 (MCMP0, no modulation) COUT60 (MCMP1, no modulation) CC60 (T12, no modulation) COUT60 (T12, no modulation) CC60 (MCMP0 modulated with T12) COUT60 (MCMP1 modulated with T12) CC60 (MCMP0 modulated with T12 and T13) COUT60...
Page 370 XC886/888CLM Capture/Compare Unit 6 • synchronized to T13 PWM after TRPF is reset (T13 period-match) • no synchronization to T12 or T13 TRPF CTRAP active TRPS sync. to T13 TRPS sync. to T12 TRPS no sync. CCU6_trap_sync Figure 14-14 Trap State Synchronization (with TRPM2 = 0) User’s Manual 14-18 V1.3, 2010-02...
Page 371: Multi-Channel Mode
XC886/888CLM Capture/Compare Unit 6 14.1.5 Multi-Channel Mode The multi-channel mode offers the possibility of modulating all six T12-related outputs. The bits in bit field MCMP are used to select the outputs that may become active. If the multi-channel mode is enabled (bit MCMEN = 1), only those outputs that have a 1 at the corresponding bit positions in bit field MCMP may become active.
Page 372 XC886/888CLM Capture/Compare Unit 6 synchronization event, which leads to the transfer from MCMPS to MCMP. Due to this structure, an update takes place with a new PWM period. The update can also be requested by software by writing to bit field MCMPS with the shadow transfer request bit STRMCM set.
Page 373: Hall Sensor Mode
XC886/888CLM Capture/Compare Unit 6 14.1.6 Hall Sensor Mode In Brushless-DC motors, the next multi-channel state values depend on the pattern of the Hall inputs. There is a strong correlation between the Hall pattern (CURH) and the modulation pattern (MCMP). Because of different machine types, the modulation pattern for driving the motor can vary.
Page 374: Brushless-Dc Control
XC886/888CLM Capture/Compare Unit 6 This correct Hall event can be used as a transfer request event for register MCMOUTS. The transfer from MCMOUTS to MCMOUT transfers the new CURH-pattern as well as the next EXPH-pattern. In case the sampled Hall inputs were neither the current nor the expected Hall pattern, the bit WHE (wrong Hall event) is set, which can also cause an interrupt and set the IDLE mode to clear MCMP (modulation outputs are inactive).
Page 375 XC886/888CLM Capture/Compare Unit 6 Table 14-1 lists an example of block commutation in BLDC motor control. If the input signal combination CCPOS0-CCPOS2 changes its state, the outputs CC6x and COUT6x are set to their new states. Figure 14-17 shows the block commutation in rotate left mode and Figure 14-18 shows the block commutation in rotate right mode.
Page 376 XC886/888CLM Capture/Compare Unit 6 CCPOS0 CCPOS1 CCPOS2 CC60 CC61 CC62 COUT60 COUT61 COUT62 Figure 14-17 Block Commutation in Rotate Left Mode CCPOS0 CCPOS1 CCPOS2 CC60 CC61 CC62 COUT60 COUT61 COUT62 Figure 14-18 Block Commutation in Rotate Right Mode User’s Manual 14-24 V1.3, 2010-02 CCU6, V 1.0...
Page 377: Interrupt Generation
XC886/888CLM Capture/Compare Unit 6 14.1.7 Interrupt Generation The interrupt generation can be triggered by the interrupt event or the setting of the corresponding interrupt bit in register IS by software. The interrupt is generated independently of the interrupt flag in register IS. Register IS can only be read; write actions have no impact on the contents of this register.
Page 378: Low Power Mode
XC886/888CLM Capture/Compare Unit 6 14.1.8 Low Power Mode If the CCU6 functionality is not required at all, it can be completely disabled by gating off its clock input for maximal power reduction. This is done by setting bit CCU_DIS in register PMCON1 as described below.
Page 379: Module Suspend Control
XC886/888CLM Capture/Compare Unit 6 14.1.9 Module Suspend Control The timers of CCU6, Timer 12 and Timer 13, can be configured to stop their counting when the OCDS enters monitor mode (see Chapter 17.3) by setting their respective module suspend bits, T12SUSP and T13SUSP, in SFR MODSUSP. MODSUSP Module Suspend Control Register Reset Value: 01...
Page 380: Port Connection
XC886/888CLM Capture/Compare Unit 6 14.1.10 Port Connection Table 14-2 shows how bits and bit fields must be programmed for the required I/O functionality of the CCU6 I/O lines. This table also shows the values of the peripheral input select registers. Table 14-2 CCU6 I/O Control Selection Port Lines...
Page 381 XC886/888CLM Capture/Compare Unit 6 Table 14-2 CCU6 I/O Control Selection (cont’d) Port Lines PISEL Register Bit Input/Output Control Register Bits P3.1/COUT60_0 – P3_DIR.P1 = 1 Output P3_ALTSEL0.P1 = 1 P3_ALTSEL1.P1 = 0 P4.1/COUT60_1 – P4_DIR.P1 = 1 Output P4_ALTSEL0.P1 = 1 P4_ALTSEL1.P1 = 0 P3.2/CC61_0 ISCC61 = 00...
Page 382 XC886/888CLM Capture/Compare Unit 6 Table 14-2 CCU6 I/O Control Selection (cont’d) Port Lines PISEL Register Bit Input/Output Control Register Bits P4.5/COUT61_2 – P4_DIR.P5 = 1 Output P4_ALTSEL0.P5 = 1 P4_ALTSEL1.P5 = 0 P3.4/CC62_0 ISCC62= 00 P3_DIR.P4 = 0 Input – P3_DIR.P4 = 1 Output P3_ALTSEL0.P4 = 1...
Page 383 XC886/888CLM Capture/Compare Unit 6 Table 14-2 CCU6 I/O Control Selection (cont’d) Port Lines PISEL Register Bit Input/Output Control Register Bits P4.3/COUT63_2 – P4_DIR.P3 = 1 Output P4_ALTSEL0.P3 = 0 P4_ALTSEL1.P3 = 1 P1.6/T12HR_0 IST12HR = 00 P1_DIR.P6 = 0 Input P0.0/T12HR_1 IST12HR = 01 P0_DIR.P0 = 0...
Page 384: Register Map
XC886/888CLM Capture/Compare Unit 6 14.2 Register Map The CCU6 SFRs are located in the standard memory area (RMAP = 0) and are organized into 4 pages. The CCU6_PAGE register is located at address A3 . It contains the page value and the page control information. All CCU6 register names described in the following sections are referenced in other chapters of this document with the module name prefix “CCU6_”, e.g., CCU6_CC63SRL.
Page 385 XC886/888CLM Capture/Compare Unit 6 CCU6_PAGE Page Register for CCU6 Reset Value: 00 STNR PAGE Field Bits Type Description PAGE [2:0] Page Bits When written, the value indicates the new page address. When read, the value indicates the currently active page = addr [y:x+1]. STNR [5:4] Storage Number...
Page 386 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description [7:6] Operation Manual page mode. The value of STNR is ignored and PAGE is directly written. New page programming with automatic page saving. The value written to the bit positions of PAGE is stored. In parallel, the previous contents of PAGE are saved in the storage bit field STx indicated by STNR.
Page 387: Register Description
XC886/888CLM Capture/Compare Unit 6 14.3 Register Description Table 14-4 shows all registers associated with the CCU6 module. For all CCU6 registers, the write-only bit positions (indicated by “w”) always deliver the value of 0 when they are read out. If a hardware and a software request to modify a bit occur simultaneously, the software wins.
Page 388 XC886/888CLM Capture/Compare Unit 6 Table 14-4 Registers Overview (cont’d) Register Register Long Name Description Short Name CC63RH Capture/Compare Register for Channel CC63 Page 14-53 High CC63SRL Capture/Compare Shadow Register for Channel Page 14-54 CC63 Low CC63SRH Capture/Compare Shadow Register for Channel Page 14-54 CC63 High CCU6 Control Registers...
Page 389: System Registers
XC886/888CLM Capture/Compare Unit 6 Table 14-4 Registers Overview (cont’d) Register Register Long Name Description Short Name T12MSELH T12 Mode Select Register High Page 14-44 Interrupt Control Registers Capture/Compare Interrupt Status Register Low Page 14-79 Capture/Compare Interrupt Status Register High Page 14-80 ISSL Capture/Compare Interrupt Status Set Register Page 14-83...
Page 390 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description ISCC60 Input Select for CC60 This bit field defines the port pin that is used for the CC60 capture input signal. The input pin for CC60_0. Reserved Reserved The input pin for CC60_3. ISCC61 Input Select for CC61 This bit field defines the port pin that is used for the...
Page 391 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description ISPOS0 Input Select for CCPOS0 This bit field defines the port pin that is used for the CCPOS0 input signal. The input pin for CCPOS0_0. The input pin for CCPOS0_1. The input pin for CCPOS0_2. The input pin for CCPOS0_3.
Page 392: Timer 12 - Related Registers
XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description IST13HR Input Select for T13HR This bit field defines the port pin that is used for the T13HR input signal. The input pin for T13HR_0. The input pin for T13HR_1. The input pin for T13HR_2. Reserved Reserved Returns 0 if read;...
Page 393 XC886/888CLM Capture/Compare Unit 6 Table 14-5 Double-Register Capture Modes (cont’d) Description 0110 The value stored in CC6nSR is copied to CC6nR after a falling edge on the input pin CC6n. The actual timer value of T12 is simultaneously stored in the shadow register CC6nSR.
Page 394 XC886/888CLM Capture/Compare Unit 6 Table 14-7 Multi-Input Capture Modes Description 1100 The timer value of T12 is stored in CC6nR after a rising edge at the input pin CC6n. The timer value of T12 is stored in CC6nSR after a rising edge at the input pin CCPOSx.
Page 395 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description MSEL60, 3:0, Capture/Compare Mode Selection MSEL61 These bit fields select the operating mode of the three timer T12 capture/compare channels. Each channel (n = 0, 1, 2) can be programmed individually either for compare or capture operation according to: 0000 Compare outputs disabled, pins CC6n and COUT6n can be used for I/O.
Page 396 XC886/888CLM Capture/Compare Unit 6 T12MSELH T12 Capture/Compare Mode Select Register High Reset Value: 00 HSYNC MSEL62 Field Bits Type Description MSEL62 Capture/Compare Mode Selection These bit fields select the operating mode of the three timer T12 capture/compare channels. Each channel (n = 0, 1, 2) can be programmed individually either for compare or capture operation according to: 0000 Compare outputs disabled, pins CC6n and...
Page 397 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description HSYNC Hall Synchronization Bit field HSYNC defines the source for the sampling of the Hall input pattern and the comparison to the current and the expected Hall pattern bit fields. In all modes, a trigger by software by writing a 1 to bit SWHC is possible.
Page 398 XC886/888CLM Capture/Compare Unit 6 In edge-aligned mode, T12 only counts up, whereas in center-aligned mode, T12 can count up and down. T12L Timer T12 Counter Register Low Reset Value: 00 T12CVL Field Bits Type Description T12CVL Timer T12 Counter Value Low Byte This register represents the lower 8-bit counter value of timer T12.
Page 399 XC886/888CLM Capture/Compare Unit 6 T12PRL Timer T12 Period Register Low Reset Value: 00 T12PVL Field Bits Type Description T12PVL T12 Period Value Low Byte The value T12PV defines the counter value for T12, which leads to a period-match. On reaching this value, the timer T12 is set to zero (edge- aligned mode) or changes its count direction to down counting (center-aligned mode).
Page 400 XC886/888CLM Capture/Compare Unit 6 CC6xRL (x = 0, 1, 2) Capture/Compare Register for Channel CC6x Low Reset Value: 00 CC6xVL (x = 0, 1, 2) Field Bits Type Description CC6xVL Channel x Capture/Compare Value Low Byte (x = 0, 1, 2) In compare mode, the bit fields CC6xV contain the values that are compared to the T12 counter value.
Page 401 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description CC6xSL Shadow Register for Channel x (x = 0, 1, 2) Capture/Compare Value Low Byte In compare mode, the contents of bit field CC6xS are transferred to the bit field CC6xV during a shadow transfer.
Page 402 XC886/888CLM Capture/Compare Unit 6 T12DTCL Dead-Time Control Register for Timer T12 Low Reset Value: 00 Field Bits Type Description Dead-Time Bit field DTM determines the programmable delay between switching from the passive state to the active state of the selected outputs. The switching from the active state to the passive state is not delayed.
Page 403: Timer 13 - Related Registers
XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description DTRx Dead-Time Run Indication Bits (x = 0, 1, 2) Bits DTR0..DTR2 indicate the status of the dead-time generation for each compare channel (0, 1, 2) of timer T12. The value of the corresponding dead-time counter channel is 0.
Page 404 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description T13CVL Timer T13 Counter Value Low Byte This register represents the lower 8-bit counter value of timer T13. T13H Timer T13 Counter Register High Reset Value: 00 T13CVH Field Bits Type Description T13CVH Timer T13 Counter Value High Byte This register represents the upper 8-bit counter...
Page 405 XC886/888CLM Capture/Compare Unit 6 T13PRH Timer T13 Period Register High Reset Value: 00 T13PVH Field Bits Type Description T13PVH T13 Period Value High Byte The value T13PV defines the counter value for T13, which leads to a period-match. On reaching this value, the timer T13 is set to zero.
Page 406 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description CC63VH Channel CC63 Compare Value High Byte The bit field CC63V contains the value that is compared to the T13 counter value. CC63SRL Capture/Compare Shadow Register for Channel CC63 Low Reset Value: 00 CC63SL Field Bits...
Page 407: Capture/Compare Control Registers
XC886/888CLM Capture/Compare Unit 6 14.3.4 Capture/Compare Control Registers The Compare State Register CMPSTAT contains status bits monitoring the current capture and compare state, and control bits defining the active/passive state of the compare channels. CMPSTATL Compare State Register Low Reset Value: 00 63ST 62ST 61ST...
Page 408 XC886/888CLM Capture/Compare Unit 6 CMPSTATH Compare State Register High Reset Value: 00 OUT63PS OUT62PS 62PS OUT61PS 61PS OUT60PS 60PS Field Bits Type Description CC6xPS 0, 2, Passive State Select for Compare Outputs (x = 0, 1, 2) Bits CC6xPS, COUT6xPS select the state of the corresponding compare channel, which is considered COUT6xPS 1, 3,...
Page 409 XC886/888CLM Capture/Compare Unit 6 CMPMODIFL Compare State Modification Register Low Reset Value: 00 Field Bits Type Description MCC6xS 0, 1, Capture/Compare Status Modification Bits (Set) (x = 0, 1, 2, 3) 2, 6 These bits are used to set the corresponding CC6xST bits by software.
Page 410 XC886/888CLM Capture/Compare Unit 6 CMPMODIFH Compare State Modification Register High Reset Value: 00 Field Bits Type Description MCC6xR 0, 1, Capture/Compare Status Modification Bits (Reset) (x = 0, 1, 2, 3) 2, 6 These bits are used to reset the corresponding CC6xST bits by software.
Page 411 XC886/888CLM Capture/Compare Unit 6 TCTR0L Timer Control Register 0 Low Reset Value: 00 CDIR STE12 T12R T12CLK Field Bits Type Description T12CLK Timer T12 Input Clock Select Selects the input clock for timer T12 which is derived from the peripheral clock according to the equation <T12CLK>...
Page 412 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description STE12 Timer T12 Shadow Transfer Enable Bit STE12 enables or disables the shadow transfer of the T12 period value, the compare values and passive state select bits and levels from their shadow registers to the actual registers if a T12 shadow transfer event is detected.
Page 413 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description T13CLK Timer T13 Input Clock Select Selects the input clock for timer T13 which is derived from the peripheral clock according to the equation <T13CLK> /128 T13PRE Timer T13 Prescaler Bit In order to support higher clock frequencies, an additional prescaler factor of 1/256 can be enabled for the prescaler for T13.
Page 414 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description Reserved Returns 0 if read; should be written with 0. Note: A write action to the bit fields T12CLK or T12PRE is only taken into account when the timer T12 is not running (T12R = 0). A write action to the bit fields T13CLK or T13PRE is only taken into account when the timer T13 is not running (T13R = 0).
Page 415 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description T13SSC Timer T13 Single Shot Control This bit controls the single shot-mode of T13. No hardware action on T13R The single-shot mode is enabled, the bit T13R is reset by hardware if T13 reaches its period value.
Page 416 XC886/888CLM Capture/Compare Unit 6 counting up - counting down >> a T12 channel 0, 1, 2 compare match triggers T13R only while T12 is counting down - independent from bit CDIR >> each T12 channel 0, 1, 2 compare match triggers T13R The timer count direction is taken from the value of bit CDIR.
Page 417 XC886/888CLM Capture/Compare Unit 6 Register TCTR4 allows the software control of the run bits T12R and T13R by independent set and reset conditions. Furthermore, the timers can be reset (while running) and the bits STE12 and STE13 can be controlled by software. TCTR4L Timer Control Register 4 Low Reset Value: 00...
Page 418 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description Reserved Returns 0 if read; should be written with 0. TCTR4H Timer Control Register 4 High Reset Value: 00 Field Bits Type Description T13RR Timer T13 Run Reset Setting this bit resets the T13R bit. T13R is not influenced.
Page 419: Global Modulation Control Registers
XC886/888CLM Capture/Compare Unit 6 Note: A simultaneous write of a 1 to bits which set and reset the same bit will trigger no action. The corresponding bit will remain unchanged. 14.3.5 Global Modulation Control Registers Register MODCTR contains control bits enabling the modulation of the corresponding output signal by PWM pattern generated by the timers T12 and T13.
Page 420 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description MCMEN Multi-Channel Mode Enable The modulation of the corresponding output signal by a multi-channel pattern according to bit field MCMPis disabled. The modulation of the corresponding output signal by a multi-channel pattern according to bit field MCMP is enabled.
Page 421 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description ECT13O Enable Compare Timer T13 Output The alternate output function COUT63 is disabled. The alternate output function COUT63 is enabled for the PWM signal generated by T13. Reserved Returns 0 if read; should be written with 0. The register TRPCTR controls the trap functionality.
Page 422 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description TRPM0, Trap Mode Control Bits 1, 0 TRPM1 These two bits define the behavior of the selected outputs when leaving the trap state after the trap condition has become inactive again. A synchronization to the timer driving the PWM pattern permits to avoid unintended short pulses when leaving the trap state.
Page 423 XC886/888CLM Capture/Compare Unit 6 TRPCTRH Trap Control Register High Reset Value: 00 TRPEN Field Bits Type Description TRPEN Trap Enable Control Setting these bits enables the trap functionality for the following corresponding output signals: Bit 0 trap functionality of CC60 Bit 1 trap functionality of COUT60 Bit 2 trap functionality of CC61 Bit 3 trap functionality of COUT61...
Page 424 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description TRPPEN Trap Pin Enable The trap functionality based on the input pin CTRAP is disabled. A trap can only be generated by software by setting bit TRPF. The trap functionality based on the input pin CTRAP is enabled.
Page 425: Multi-Channel Modulation Control Registers
XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description PSL63 Passive State Level of Output COUT63 This bit field defines the passive level of the output pin COUT63. The passive level is 0. The passive level is 1. Reserved Returns 0 if read; should be written with 0. Note: Bit field PSL has a shadow register to allow for updates without undesired pulses on the output lines.
Page 426 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description STRMCM Shadow Transfer Request for MCMPS Setting this bit during a write action leads to an immediate update of bit field MCMP by the value written to bit field MCMPS. This functionality permits an update triggered by software.
Page 427 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description STRHP Shadow Transfer Request for the Hall Pattern Setting these bits during a write action leads to an immediate update of bit fields CURH and EXPH by the value written to bit fields CURHS and EXPHS. This functionality permits an update triggered by software.
Page 428 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description MCMP Multi-Channel PWM Pattern Bit field MCMP is written by a shadow transfer from bit field MCMPS. It contains the output pattern for the multi-channel mode. If this mode is enabled by bit MCMEN in register MODCTR, the output state of the following output signal can be modified: Bit 0 multi-channel state for output CC60...
Page 429 XC886/888CLM Capture/Compare Unit 6 MCMOUTH Multi-Channel Mode Output Register High Reset Value: 00 CURH EXPH Field Bits Type Description EXPH Expected Hall Pattern Bit field EXPH is written by a shadow transfer from bit field EXPHS. The contents are compared after every detected edge at the hall input pins with the pattern at the hall input pins in order to detect the occurrence of the next desired (=expected) hall pattern or a wrong...
Page 430 XC886/888CLM Capture/Compare Unit 6 Register MCMCTR contains control bits for the multi-channel functionality. MCMCTR Multi-Channel Mode Control Register Reset Value: 00 SWSYN SWSEL Field Bits Type Description SWSEL Switching Selection Bit field SWSEL selects one of the following trigger request sources (next multi-channel event) for the shadow transfer from MCMPS to MCMP.
Page 431: Interrupt Control Registers
XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description SWSYN Switching Synchronization Bit field SWSYN triggers the shadow transfer between MCMPS and MCMP if it has been requested before (flag R set by an event selected by SWSEL). This feature permits the synchronization of the outputs to the PWM source, that is used for modulation (T12 or T13).
Page 432 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description ICC6xF 1, 3, Capture, Compare-Match Falling Edge Flag (x = 0, 1, 2) In compare mode, a compare-match has been detected while T12 was counting down. In capture mode, a falling edge has been detected at the input CC6x.
Page 433 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description T13PM Timer T13 Period-Match Flag A timer T13 period-match has not yet been detected since this bit has been reset for the last time. A timer T13 period-match has been detected. TRPF Trap Flag The trap flag TRPF will be set by hardware if TRPPEN = 1 and CTRAP = 0 or by software.
Page 434 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description Wrong Hall Event On every valid hall edge, the contents of EXPH are compared with the pattern on pin CCPOSx. If both comparisons (CURH and EXPH with CCPOSx) are not true, bit WHE (wrong hall event) is set. A transition to a wrong hall event (not the expected one) has not yet been detected since this bit has been reset for the last time.
Page 435 XC886/888CLM Capture/Compare Unit 6 ISSL Capture/Compare Interrupt Status Set Register Low Reset Value: 00 Field Bits Type Description SCC60R Set Capture, Compare-Match Rising Edge Flag No action Bit ICC60R in register IS will be set. SCC60F Set Capture, Compare-Match Falling Edge Flag No action Bit ICC60F in register IS will be set.
Page 436 XC886/888CLM Capture/Compare Unit 6 ISSH Capture/Compare Interrupt Status Set Register High Reset Value: 00 IDLE TRPF Field Bits Type Description ST13CM Set Timer T13 Compare-Match Flag No action Bit T13CM in register IS will be set. ST13PM Set Timer T13 Period-Match Flag No action Bit T13PM in register IS will be set.
Page 437 XC886/888CLM Capture/Compare Unit 6 ISRL Capture/Compare Interrupt Status Reset Register Low Reset Value: 00 Field Bits Type Description RCC60R Reset Capture, Compare-Match Rising Edge Flag No action Bit ICC60R in register IS will be reset. RCC60F Reset Capture, Compare-Match Falling Edge Flag No action Bit ICC60F in register IS will be reset.
Page 438 XC886/888CLM Capture/Compare Unit 6 ISRH Capture/Compare Interrupt Status Reset Register High Reset Value: 00 IDLE TRPF Field Bits Type Description RT13CM Reset Timer T13 Compare-Match Flag No action Bit T13CM in register IS will be reset. RT13PM Reset Timer T13 Period-Match Flag No action Bit T13PM in register IS will be reset.
Page 439 XC886/888CLM Capture/Compare Unit 6 IENL Capture/Compare Interrupt Enable Register Low Reset Value: 00 Field Bits Type Description ENCC60R Capture, Compare-Match Rising Edge Interrupt Enable for Channel 0 No interrupt will be generated if the set condition for bit ICC60R in register IS occurs. An interrupt will be generated if the set condition for bit ICC60R in register IS occurs.
Page 440 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description ENCC61F Capture, Compare-Match Falling Edge Interrupt Enable for Channel 1 No interrupt will be generated if the set condition for bit ICC61F in register IS occurs. An interrupt will be generated if the set condition for bit ICC61F in register IS occurs.
Page 441 XC886/888CLM Capture/Compare Unit 6 IENH Capture/Compare Interrupt Enable Register High Reset Value: 00 IDLE TRPF Field Bits Type Description ENT13CM Enable Interrupt for T13 Compare-Match No interrupt will be generated if the set condition for bit T13CM in register IS occurs. An interrupt will be generated if the set condition for bit T13CM in register IS occurs.
Page 442 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description ENWHE Enable Interrupt for Wrong Hall Event No interrupt will be generated if the set condition for bit WHE in register IS occurs. An interrupt will be generated if the set condition for bit WHE in register IS occurs.
Page 443 XC886/888CLM Capture/Compare Unit 6 Field Bits Type Description INPCC60 Interrupt Node Pointer for Channel 0 Interrupts This bit field defines the interrupt output line, which is activated due to a set condition for bit ICC60R (if enabled by bit ENCC60R) or for bit ICC60F (if enabled by bit ENCC60F).
Page 444 XC886/888CLM Capture/Compare Unit 6 INPH Capture/Compare Interrupt Node Pointer Register High Reset Value: 39 Field Bits Type Description INPERR Interrupt Node Pointer for Error Interrupts This bit field defines the interrupt output line, which is activated due to a set condition for bit TRPF (if enabled by bit ENTRPF) or for bit WHE (if enabled by bit ENWHE).
Page 445: Controller Area Network (Multican) Controller
XC886/888CLM Controller Area Network (MultiCAN) Controller Controller Area Network (MultiCAN) Controller The MultiCAN module contains 2 Full-CAN nodes operating independently or exchanging data and remote frames via a gateway function. Transmission and reception of CAN frames is handled in accordance to CAN specification V2.0 B active. Each CAN node can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers.
Page 446 XC886/888CLM Controller Area Network (MultiCAN) Controller Features • Compliant with ISO 11898 • CAN functionality according to CAN specification V2.0 B active • Dedicated control registers for each CAN node • Data transfer rates up to 1 Mbit/s • Flexible and powerful message transfer control and error handling capabilities •...
Page 447 XC886/888CLM Controller Area Network (MultiCAN) Controller – Up to 8 interrupt output lines are available. Interrupt requests can be individually routed to one of the 8 interrupt output lines – Message post-processing notifications can be combined flexibly into a dedicated register field of 64 notification bits User’s Manual 15-3...
Page 448: Multican Kernel Functional Description
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.1 MultiCAN Kernel Functional Description This section describes the functionality of the MultiCAN module. 15.1.1 Module Structure Figure 15-2 shows the general structure of the MultiCAN module. CAN Bus 0 CAN Bus 1 Bitstream Node Processor Control...
Page 449 XC886/888CLM Controller Area Network (MultiCAN) Controller • Error Handling Unit The Error Handling Unit manages the receive and transmit error counter. According to the contents of both counters, the CAN node is set into an error-active, error passive or bus-off state. •...
Page 450 XC886/888CLM Controller Area Network (MultiCAN) Controller module. If more than one interrupt source is connected to the same interrupt node pointer (in the interrupt node pointer register), the requests are combined to one common line. Reset Interrupt Writing 0 Flag Interrupt Event &...
Page 451: Clock Control
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.1.2 Clock Control Table 15-1 indicates the minimum operating frequencies in MHz for that are required for a baud rate of 1 Mbit/s for the active CAN nodes. If less baud rate is desired, the values can be scaled linearly (e.g.
Page 452: Can Node Control
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.1.3 CAN Node Control Each CAN node may be configured and run independently from the other CAN nodes. Each CAN node is equipped with an individual set of SFR registers to control and to monitor the CAN node.
Page 453: Bitstream Processor
XC886/888CLM Controller Area Network (MultiCAN) Controller quanta is requested by the ISO standard. According to ISO standard, a CAN bit time, calculated as the sum of T and T , must not fall below 8 time quanta. Sync Seg1 Seg2 Calculation of the bit time: = (BRP + 1) / if DIV8 = 0...
Page 454: Error Handling Unit
XC886/888CLM Controller Area Network (MultiCAN) Controller Processor starts the CAN bus arbitration procedure and continues with the frame transmission when the bus was found in idle state. While the data transmission is running, the Bit Stream Processor monitors continuously the I/O line. If (outside the CAN bus arbitration phase or the acknowledge slot) a mismatch is detected between the voltage level on the I/O line and the logic state of the bit currently sent out by the transmit shift register, a ‘Last Error’...
Page 455: Can Frame Counter
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.1.3.4 CAN Frame Counter Each CAN node is equipped with a frame counter which enables the counting of transmitted/received CAN frames or helps obtain information on the time instant when a frame has started to transmit or received by the CAN node. CAN frame counting/bit time counting is performed by a 16-bit counter which is controlled by register NFCRx.
Page 456 XC886/888CLM Controller Area Network (MultiCAN) Controller NSRx NCRx Correct Message Object Transfer TXOK TRIE NIPRx > Transmit TRINP Receive RXOK NSRx NSRx NCRx LECIE NIPRx CAN Error LECINP NCRx NSRx ALIE > EWRN NIPRx BOFF ALINP List Length Error NSRx List Object Error ALERT NSRx...
Page 457: Message Object List Structure
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.1.4 Message Object List Structure This section describes the structure of the message object lists in the MultiCAN module. 15.1.4.1 Basics The message objects of the MultiCAN module are organized in double-chained lists, where each message object has a pointer to the previous message object in the list as well as a pointer to the next message object in the list.
Page 458: List Of Unallocated Elements
XC886/888CLM Controller Area Network (MultiCAN) Controller has no successor (in the example object 3 is the last message object in the list, indicated by PNEXT = 3). Bit field MOCTRn.LIST indicates the list index number to which the message object is currently allocated.
Page 459: List Command Panel
XC886/888CLM Controller Area Network (MultiCAN) Controller CAN Bus 0 CAN Bus 1 Unallocated List Node 0 Node 1 Elements 1. Object 1. Object 1. Object in List 0 in List 1 in List 2 2. Object 2. Object 2. Object in List 0 in List 1 in List 2...
Page 460 XC886/888CLM Controller Area Network (MultiCAN) Controller Table 15-2 gives an overview on the available panel commands while Table 15-7 describes the panel commands in more detail. Table 15-2 Panel Commands Overview Command Name Description No Operation No new command is started. Initialize Lists Run the initialization sequence to reset the CTRL and LIST field of all message objects.
Page 461 XC886/888CLM Controller Area Network (MultiCAN) Controller 1. The message number of the message object taken from the list of unallocated elements is written to PANAR1. 2. If ERR (bit 7 of PANAR2) is set to 1, the list of unallocated elements was empty and the command is aborted.
Page 462: Can Node Analysis Features
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.1.5 CAN Node Analysis Features This section describes the CAN node analysis capabilities of the MultiCAN module. 15.1.5.1 Analyze Mode The CAN analyze mode allows the CAN traffic to be monitored without affecting the logical state of the CAN bus.
Page 463: Bit Timing Analysis
XC886/888CLM Controller Area Network (MultiCAN) Controller internal CAN bus NPCR0.LBM CAN Bus 0 CAN node 0 NPCR1.LBM CAN Bus 1 CAN node 1 MultiCAN_loop_back_x2 Figure 15-8 Loop-Back Mode 15.1.5.3 Bit Timing Analysis Detailed analysis of the bit timing can be performed for each CAN node using the analysis modes of the CAN frame counter.
Page 464 XC886/888CLM Controller Area Network (MultiCAN) Controller Synchronization Analysis The bit time synchronization is monitored if NFCRx.CFSEL = 010 . The time between the first dominant edge and the sample point is measured and stored in the NFCRx.CFC bit field. The bit timing synchronization offset may be derived from this time as the first edge after the sample point triggers synchronization and there is only one synchronization between consecutive sample points.
Page 465: Message Acceptance Filtering
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.1.6 Message Acceptance Filtering This section describes the Message Acceptance Filtering capabilities of the MultiCAN module. 15.1.6.1 Receive Acceptance Filtering When a CAN frame is received by a CAN node, a unique message object is determined in which the received frame is stored after successful frame reception.
Page 466: Transmit Acceptance Filtering
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.1.6.2 Transmit Acceptance Filtering A message is requested for transmission by setting a transmit request in the message object that holds the message. If more than one message object have a valid transmit request for the same CAN node, one of these message objects is chosen for transmission, because only a single message object can be transmitted at one time on a CAN bus.
Page 467: Message Postprocessing
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.1.7 Message Postprocessing After a message object has successfully received or transmitted a frame, the CPU can be notified to perform a message postprocessing on the message object. The postprocessing of the MultiCAN module consists of two elements: 1.
Page 468 XC886/888CLM Controller Area Network (MultiCAN) Controller MOSTATn MOFCRn TXPND RXPND OVIE TXIE RXIE = 0010 MOIPRn = 0001 Message n > transmitted TXINP & Message n FIFO full & MOIPRn > RXINP Message n received MMC = 0001 : Message object n is a Receive FIFO Base Object MultiCAN_msg_interrupts MMC = 0010 : Message object n is a Transmit FIFO Base Object...
Page 469: Pending Messages
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.1.7.2 Pending Messages With a message interrupt request generation, a message pending bit is set in one of the Message Pending Registers. There are two Message Pending Registers MSPNDk (k = 1-0) with 32 pending bits available to each, resulting in 64 pending bits. Figure 15-10 shows the allocation of the message pending bits.
Page 470 XC886/888CLM Controller Area Network (MultiCAN) Controller The location of a pending bit is defined by two demultiplexers selecting the number k of the MSPNDk registers (1-bit demux), and the bit location within the corresponding MSPNDk register (5-bit demux). Allocation Case 1 .
Page 471: Message Object Data Handling
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.1.8 Message Object Data Handling This section describes the handling capabilities for the Message Object Data of the MultiCAN module. 15.1.8.1 Frame Reception After the reception of a message, it is stored in a message object according to the scheme shown in Figure 15-11.
Page 472 XC886/888CLM Controller Area Network (MultiCAN) Controller context of the message object. Therefore, a message object re-configuration should consist of the following steps: 1. Clear MSGVAL bit 2. Re-configure the message object while MSGVAL = 0 3. Clear RTSEL bit and set MSGVAL again RXEN Bit MOSTATn.RXEN enables a message object for frame reception.
Page 473 XC886/888CLM Controller Area Network (MultiCAN) Controller Get Data from Start receiving gateway/fifo CAN fram e source Done Obj. wins acc. filtering RTSEL := 1 Done CAN rec. successful M SGVAL&RTSEL Done M SGVAL=1 Done RXUPD := 1 RXUPD := 1 Copy Fram e to Copy Fram e to M essage Obj.
Page 474: Frame Transmission
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.1.8.2 Frame Transmission The process of a message object transmission is shown in Figure 15-12. With the copy of the message object content to be transmitted (identifier, IDE bit, RTR = DIR bit, DLC, and for data frames also the data field) into the internal transmit buffer of the assigned CAN node, also several status flags are served and monitored to control consistent data handling.
Page 475 XC886/888CLM Controller Area Network (MultiCAN) Controller Table 15-3 Message Transmission Bit Definitions (cont’d) Description TXEN1 Transmit Enable 1 This bit is used in transmit FIFOs to select the message object that is transmit active within the FIFO structure. For message objects that are not transmit FIFO elements, TXEN1 can either be set permanently to 1 or can be used as a second independent transmission enable bit.
Page 476 XC886/888CLM Controller Area Network (MultiCAN) Controller Obj. wins transm it acc. filtering RTSEL := 1 Copy M essage to internal transm it buffer M SGVAL & TXRQ & TXEN0 & TXEN1 = 1 Done continously during m essage copying Done RTSEL = 1 Request Transm ission of internal buffer on CAN bus...
Page 477: Message Object Functionality
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.1.9 Message Object Functionality This section describes the functionality of the Message Objects in the MultiCAN module. 15.1.9.1 Standard Message Object A message object is selected as Standard Message Object when bit field MOFCRn.MMC = 0000 .
Page 478: Message Object Fifo Structure
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.1.9.4 Message Object FIFO Structure In case of high CPU load it may be difficult to process a series of CAN frames in time. This may happen if multiple messages are received or must be transmitted in short time. Therefore, a FIFO buffer structure is available to avoid loss of incoming messages and to minimize the setup time for outgoing messages.
Page 479 XC886/888CLM Controller Area Network (MultiCAN) Controller allows the end of a predefined message transfer series to be detected or to issue a warning interrupt when the FIFO becomes full. PPREV = f[n-1] PNEXT Slave Object fn PPREV PPREV = f[i-1] PNEXT PNEXT = f[i+1] TOP = fn...
Page 480: Receive Fifo
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.1.9.5 Receive FIFO The Receive FIFO structure is used to buffer incoming (received) remote or data frames. A Receive FIFO is selected by setting MOFCRn.MMC = 0001 in the FIFO base object. This MMC code automatically designates a message object as FIFO base object. The message modes of the FIFO slave objects are not relevant for the operation of the Receive FIFO.
Page 481: Transmit Fifo
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.1.9.6 Transmit FIFO The Transmit FIFO structure is used to buffer a series of data or remote frames that must be transmitted. A Transmit FIFO is selected by setting MOFCRn.MMC = 0010 in the FIFO base object. Unlike the Receive FIFO, slave objects assigned to the Transmit FIFO are required to set explicitly their bit fields MOFCRn.MMC = 0011 .
Page 482: Gateway Mode
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.1.9.7 Gateway Mode The gateway mode allows an automatic information transfer to be established between two independent CAN buses without CPU interaction. The gateway mode operates on message object level. In gateway mode, information is transferred between two message objects, resulting in an information transfer between the two CAN nodes to which the message objects are allocated.
Page 483 XC886/888CLM Controller Area Network (MultiCAN) Controller The gateway operates in the same way for the reception of data frames (source object is receive object, i.e., DIR = 0) as well as for the reception of remote frames (source object is transmit object). Source CAN Bus Destination CAN Bus Pointer to Destination...
Page 484: Foreign Remote Requests
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.1.9.8 Foreign Remote Requests When a remote frame has been received on a CAN node and is stored in a message object, a transmit request is set to trigger the answer (transmission of a data frame) to the request or to automatically issue a secondary request.
Page 485: Access Mediator
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.1.10 Access Mediator The MultiCAN needs to cover a maximum of 16 Kbytes SFR kernel address range, which is much greater than the XC886/888 can provide. To meet this demand, an address extension decoding mechanism is built in the unit called “Access Mediator” to decode the SFRs in the MultiCAN kernel.
Page 486 XC886/888CLM Controller Area Network (MultiCAN) Controller • Write the data to the CAN_DATA0/CAN_DATA1/CAN_DATA2/CAN_DATA3 registers. • Write the register CAN_ADCON, including setting the valid bit of the data registers and setting register bit RWEN to 1. • The valid data will be written to the MultiCAN kernel only once. Register bit BSY will become 1.
Page 487: Port Control
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.1.11 Port Control The interconnections between the MultiCAN module and the port I/O lines are controlled in the port logics. In addition to the I/O control selection, the selection of a CAN node’s receive input line is configured by a bit field RXSEL in its node port control register NPCRx (x = 1-0).
Page 488: Low Power Mode
XC886/888CLM Controller Area Network (MultiCAN) Controller Table 15-4 CAN I/O Control Selection (cont’d) (cont’d) Port Lines PISEL Register Bit Input/Output Control Register Bits P3.3/TXDC1_1 – P3_DIR.P3 = 1 Output P3_ALTSEL0.P3 = 1 P3_ALTSEL1.P3 = 1 P1.4/RXDC1_3 NPCR1.RXSEL = 011 P1_DIR.P4 = 0 Input P1.3/TXDC1_3 –...
Page 489: Registers Description
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.2 Registers Description This section describes the registers of the MultiCAN module. All MultiCAN register names described in this section are also referenced in other parts of the User’s Manual by the module name prefix “CAN_”. MultiCAN Kernel Register Overview The MultiCAN Kernel include three blocks of registers: •...
Page 490 XC886/888CLM Controller Area Network (MultiCAN) Controller Table 15-5 Registers Overview - MultiCAN Kernel Registers (cont’d) Register Register Long Name Offset Address Description Short Name MOIPRn Message Object n 1008 + n x 20 Page 15-84 Interrupt Pointer Register MOAMRn Message Object n 100C + n x 20 Page 15-91...
Page 491 XC886/888CLM Controller Area Network (MultiCAN) Controller Figure 15-15 shows the MultiCAN kernel register address map. MO = Message Object; n = 31-0 = 1000 + n * 20 BASE +1400 + 1C MO n Control/Status Reg. BASE Message Object 31 +13E0 + 18 MO n Arbitration Reg.
Page 492: Global Module Registers
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.2.1 Global Module Registers All list operations such as allocation, de-allocation and relocation of message objects within the list structure are performed via the Command Panel. It is not possible to modify the list structure directly by software by writing to the message objects and the LIST registers.
Page 493 XC886/888CLM Controller Area Network (MultiCAN) Controller Field Bits Type Description PANAR1 [23:16] rwh Panel Argument 1 Table 15-7. PANAR2 [31:24] rwh Panel Argument 2 Table 15-7. [15:10] r Reserved Read as 0; should be written with 0. Panel Commands A panel operation consists of a command code (PANCMD) and up to two panel arguments (PANAR1, PANAR2).
Page 494 XC886/888CLM Controller Area Network (MultiCAN) Controller Table 15-7 Panel Commands (cont’d) PANCMD PANAR2 PANAR1 Command Description Argument: Argument: Static Allocate List Index Message Allocate message object to a list. The Object message object is removed from the list Number that it currently belongs to and appended to the end of the list given by PANAR2.
Page 495 XC886/888CLM Controller Area Network (MultiCAN) Controller Table 15-7 Panel Commands (cont’d) PANCMD PANAR2 PANAR1 Command Description Argument: Result: Dynamic Insert Before Destination Object Object Insert a new message object before a Number Number of given destination object. The new object Result: inserted is taken from the list of unallocated...
Page 496 XC886/888CLM Controller Area Network (MultiCAN) Controller The Module Control Register MCR contains basic settings that define the operation of the MultiCAN module. Module Control Register Reset Value: 0000 0000 MPSEL Field Bits Type Description MPSEL [15:12] Message Pending Selector Bit field MPSEL allows the bit position of the message pending bit to be selected after a message reception/transmission by a mixture of the MOIPRn register bit fields RXINP, TXINP, and MPN.
Page 497 XC886/888CLM Controller Area Network (MultiCAN) Controller The Interrupt Trigger Register ITR allows interrupt requests to be triggered on each interrupt output line by software. MITR Module Interrupt Trigger Register Reset Value: 0000 0000 Field Bits Type Description [7:0] Interrupt Trigger Writing a 1 to IT[n] (n = 0-7) generates an interrupt request on interrupt output line CANSRC[n].
Page 498 XC886/888CLM Controller Area Network (MultiCAN) Controller List Pointer and List Register Each of the two CAN nodes has a list which defines the allocated message objects. Additionally, a list of all unallocated objects is available. Further, general purpose lists are available which are not associated to a CAN node. The List Registers are assigned in the following way: •...
Page 499 XC886/888CLM Controller Area Network (MultiCAN) Controller Field Bits Type Description [31:25] r Reserved ead as 0; should be written with 0. User’s Manual 15-55 V1.3, 2010-02 MultiCAN, V1.0...
Page 500 XC886/888CLM Controller Area Network (MultiCAN) Controller Message Notifications When a message object n generates an interrupt request upon the transmission or reception of a message, then the request is routed to the interrupt output line selected by the bit field MOIPRn.TXIPND or MOIPRn.RXIPND of the message object n. As there are more message objects than interrupt output lines, an interrupt routine typically processes requests from more than one message object.
Page 501 XC886/888CLM Controller Area Network (MultiCAN) Controller Each Message Pending Register has a Message Index Register MSIDk associated with it. The Message Index Register shows the active (set) pending bit with lowest bit position within groups of pending bits. MSIDk (k = 0-1) Message Index Register k Reset Value: 0000 0020 INDEX...
Page 502 XC886/888CLM Controller Area Network (MultiCAN) Controller The Message Index Mask Register MSIMASK selects individual bits for the calculation of the Message Pending Index. The Message Index Mask Register is used commonly for all Message Pending registers and their associated Message Index registers. MSIMASK Message Index Mask Register Reset Value: 0000 0000...
Page 503: Can Node Registers
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.2.2 CAN Node Registers The CAN node registers are built in for each CAN node of the MultiCAN module. They contain information that is directly related to the operation of the CAN nodes and are shared among the nodes.
Page 504 XC886/888CLM Controller Area Network (MultiCAN) Controller Field Bits Type Description INIT Node Initialization Resetting bit INIT enables the participation of the node in the CAN traffic. If the CAN node is in the bus-off state then the ongoing bus-off recovery (which does not depend on the INIT bit) is continued.
Page 505 XC886/888CLM Controller Area Network (MultiCAN) Controller Field Bits Type Description LECIE LEC Indicated Error Interrupt Enable LECIE enables the last error code interrupt of CAN node x. This interrupt is generated with each update of bit field NSRx.LEC with LEC > 0 (CAN protocol error). Last error code interrupt is disabled.
Page 506 XC886/888CLM Controller Area Network (MultiCAN) Controller Field Bits Type Description [31:8], Reserved Read as 0; should be written with 0. User’s Manual 15-62 V1.3, 2010-02 MultiCAN, V1.0...
Page 507 XC886/888CLM Controller Area Network (MultiCAN) Controller The Node Status Register NSRx reports errors as well as successfully transferred CAN frames. NSRx (x = 0-1) Node x Status Register Reset Value: 0000 0000 LOE LLE Field Bits Type Description [2:0] Last Error Code This bit field indicates the type of the last (most recent) CAN error.
Page 508 XC886/888CLM Controller Area Network (MultiCAN) Controller Field Bits Type Description ALERT Alert Warning The ALERT bit is set upon the occurrence of one of the following events (the same events which also trigger an alert interrupt if NCRx.ALIE is set): •...
Page 509 XC886/888CLM Controller Area Network (MultiCAN) Controller Field Bits Type Description [31:10] r Reserved Read as 0; should be written with 0. Encoding of the LEC Bit Field Table 15-8 Encoding of the LEC Bit Field LEC Value Signification No Error: No error was detected for the last (most recent) message on the CAN bus.
Page 510 XC886/888CLM Controller Area Network (MultiCAN) Controller The four interrupt pointers in the NIPR register select one out of the eight interrupt outputs individually for each type of CAN node interrupt. See also Page 15-11 for more CAN node interrupt details. NIPRx (x = 0-1) Node x Interrupt Pointer Register Reset Value: 0000 0000...
Page 511 XC886/888CLM Controller Area Network (MultiCAN) Controller Field Bits Type Description TRINP [11:8] Transfer OK Interrupt Node Pointer TRINP selects the interrupt output line CANSRCm (m = 0-7) for a transfer OK interrupt of CAN Node x. 0000 Interrupt output line CANSRC0 is selected. 0001 Interrupt output line CANSRC1 is selected.
Page 512 XC886/888CLM Controller Area Network (MultiCAN) Controller The Node Port Control Register NPCRx configures the CAN bus transmit/receive ports. NPCRx can be written only if bit NCRx.CCE is set. NPCRx (x = 0-1) Node x Port Control Register Reset Value: 0000 0000 RXSEL Field Bits...
Page 513 XC886/888CLM Controller Area Network (MultiCAN) Controller The Node Bit Timing Register NBTRx contains all parameters to set up the bit timing for the CAN transfer. NBTRx can be written only if bit NCRx.CCE is set. NBTRx (x = 0-1) Node x Bit Timing Register Reset Value: 0000 0000 DIV8 TSEG2...
Page 514 XC886/888CLM Controller Area Network (MultiCAN) Controller Field Bits Type Description DIV8 Divide Prescaler Clock by 8 A time quantum lasts (BRP+1) clock cycles. A time quantum lasts 8 × (BRP+1) clock cycles. [31:16] r Reserved Read as 0; should be written with 0. User’s Manual 15-70 V1.3, 2010-02...
Page 515 XC886/888CLM Controller Area Network (MultiCAN) Controller The Node Error Counter Register NECNTx contains the CAN receive and transmit error counter as well as some additional bits to ease error analysis. NECNTx can be written only if bit NCRx.CCE is set. NECNTx (x = 0-1) Node x Error Counter Register Reset Value: 0060 0000...
Page 516 XC886/888CLM Controller Area Network (MultiCAN) Controller Field Bits Type Description [31:26] r Reserved Read as 0; should be written with 0. The Node Frame Counter Register NFCRx contains the actual value of the frame counter as well as control and status bits of the frame counter. NFCRx (x = 0-1) Node x Frame Counter Register Reset Value: 0000 0000...
Page 517 XC886/888CLM Controller Area Network (MultiCAN) Controller Field Bits Type Description CFSEL [18:16] rw CAN Frame Count Selection This bit field selects the function of the frame counter for the chosen frame count mode. Frame Count Mode Bit 0 If Bit 0 of CFSEL is set, then CFC is incremented each time a foreign frame (i.e.
Page 518 XC886/888CLM Controller Area Network (MultiCAN) Controller Field Bits Type Description CFCOV 23 CAN Frame Counter Overflow Flag Flag CFCOV is set upon a frame counter overflow (transition from FFFF to 0000 ). In bit timing analysis mode, CFCOV is set upon an update of CFC. An interrupt request is generated if CFCIE = 1.
Page 519 XC886/888CLM Controller Area Network (MultiCAN) Controller Table 15-10 CAN Bus State Information CFC[13:12] CAN Bus State NoBit The CAN bus is idle, performs bit (de-) stuffing or is in one of the following frame segments: SOF, SRR, CRC, delimiters, first 6 EOF bits, IFS. NewBit This code represents the first bit of a new frame segment.
Page 520: Message Object Registers
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.2.3 Message Object Registers The Message Object Control Register MOCTRn and the Message Object Status Register MOSTATn are located at the same address offset within a message object address block (offset address 1C ). The MOCTRn is a write-only register that makes it possible to set/reset CAN transfer related control bits through software.
Page 521 XC886/888CLM Controller Area Network (MultiCAN) Controller Field Bits Type Description RESMSGLST Reset/Set Message Lost SETMSGLST These bits control the set/reset condition for MSGLST (see Table 15-11). RESMSGVAL Reset/Set Message Valid SETMSGVAL These bits control the set/reset condition for MSGVAL (see Table 15-11).
Page 522 XC886/888CLM Controller Area Network (MultiCAN) Controller Table 15-11 Reset/Set Conditions for Bits in Register MOCTRn (cont’d) RESy Bit SETy Bit Action on Write Write 1 Write 0 Reset element No write Write 0 Write 1 Set element No write 1) The parameter “y” stands for the second part of the bit name (“RXPND”, “TXPND”, … up to “DIR”). User’s Manual 15-78 V1.3, 2010-02...
Page 523 XC886/888CLM Controller Area Network (MultiCAN) Controller The MOSTATn is a read-only register that indicates message object list status information such as the number of the current message object predecessor and successor message object, as well as the list number to which the message object is assigned.
Page 524 XC886/888CLM Controller Area Network (MultiCAN) Controller Field Bits Type Description RXUPD Receive Updating No receive update ongoing. Message identifier, DLC, and data of the message object are currently updated. NEWDAT New Data No update of the message object n since last flag reset.
Page 525 XC886/888CLM Controller Area Network (MultiCAN) Controller Field Bits Type Description RTSEL Receive/Transmit Selected Message object n is not selected for receive or transmit operation. Message object n is selected for receive or transmit operation. Frame Reception: RTSEL is set by hardware when message object n has been identified for storage of a CAN frame that is currently received.
Page 526 XC886/888CLM Controller Area Network (MultiCAN) Controller Field Bits Type Description TXRQ Transmit Request No transmission of message object n is requested. Transmission of message object n on the CAN bus is requested. The transmit request becomes valid only if TXRQ, TXEN0, TXEN1 and MSGVAL are set.
Page 527 XC886/888CLM Controller Area Network (MultiCAN) Controller Field Bits Type Description Message Direction Receive Object selected: With TXRQ = 1, a remote frame with the identifier of message object n is scheduled for transmission. On reception of a data frame with matching identifier, the message is stored in message object n.
Page 528 XC886/888CLM Controller Area Network (MultiCAN) Controller The Message Object Interrupt Pointer Register MOIPRn holds the message interrupt pointers, the message pending number, and the frame counter value of message object n. MOIPRn (n = 0-31) Message Object n Interrupt Pointer Register Reset Value: 0000 0000 CFCVAL TXINP...
Page 529 XC886/888CLM Controller Area Network (MultiCAN) Controller Field Bits Type Description [15:8] Message Pending Number This bit field selects the bit position of the bit in the Message Pending Register that is set upon a message object n receive/transmit interrupt. CFCVAL [31:16] rwh CAN Frame Counter Value When a message is stored in message object n or...
Page 530 XC886/888CLM Controller Area Network (MultiCAN) Controller The Message Object Function Control Register MOFCRn contains bits that select and configure the function of the message object. It also holds the CAN data length code. MOFCRn (n = 0-31) Message Object n Function Control Register Reset Value: 0000 0000 STT SDT RMM OVIE TXIE RXIE...
Page 531 XC886/888CLM Controller Area Network (MultiCAN) Controller Field Bits Type Description Identifier Copy The identifier of the gateway source object is not copied. The identifier of the gateway source object (after storing the received frame in the source) is copied to the gateway destination object. Applicable only to a gateway source object;...
Page 532 XC886/888CLM Controller Area Network (MultiCAN) Controller Field Bits Type Description TXIE Transmit Interrupt Enable TXIE enables the message transmit interrupt of message object n. This interrupt is generated after the transmission of a CAN message. Message transmit interrupt is disabled. Message transmit interrupt is enabled.
Page 533 XC886/888CLM Controller Area Network (MultiCAN) Controller Field Bits Type Description Transmit Object Remote Monitoring Remote monitoring is disabled: Identifier, IDE bit, and DLC of message object n remain unchanged upon the reception of a matching remote frame. Remote monitoring is enabled: Identifier, IDE bit, and DLC of a matching remote frame are copied to transmit object n in order to monitor incoming remote frames.
Page 534 XC886/888CLM Controller Area Network (MultiCAN) Controller The Message Object FIFO/Gateway Pointer register MOFGPRn contains a set of message object link pointers that are used for FIFO and gateway operations. MOFGPRn (n = 0-31) Message Object n FIFO/Gateway Pointer Register Reset Value: 0000 0000 Field Bits Type Description...
Page 535 XC886/888CLM Controller Area Network (MultiCAN) Controller Message Object n Acceptance Mask Register MOAMRn contains the mask bits for the acceptance filtering of the message object n. MOAMRn (n = 0-31) Message Object n Acceptance Mask Register Reset Value: 3FFF FFFF Field Bits Type Description...
Page 536 XC886/888CLM Controller Area Network (MultiCAN) Controller Message Object n Arbitration Register MOARn contains the CAN identifier of the message object. MOARn (n = 0-31) Message Object n Arbitration Register Reset Value: 0000 0000 Field Bits Type Description [28:0] CAN Identifier of Message Object n Identifier of a standard message (ID[28:18]) or an extended message (ID[28:0]).
Page 537 XC886/888CLM Controller Area Network (MultiCAN) Controller Field Bits Type Description [31:30] rw Priority Class PRI assigns one of the four priority classes 0, 1, 2, 3 to message object n. A lower PRI number defines a higher priority. Message objects with lower PRI value always win acceptance filtering for frame reception and transmission over message objects with higher PRI value.
Page 538 XC886/888CLM Controller Area Network (MultiCAN) Controller Transmit Priority of Msg. Objects based on CAN Arbitration Rules Table 15-13 Transmit Priority of Msg. Objects Based on CAN Arbitration Rules Settings of Arbitrarily Chosen Message Comment Objects A and B, (A has higher transmit priority than B) A.MOAR[28:18] <...
Page 539 XC886/888CLM Controller Area Network (MultiCAN) Controller Message Object n Data Register Low MODATALn contains the lowest four data bytes of message object n. Unused data bytes are set to zero upon reception and ignored for transmission. MODATALn (n = 0-31) Message Object n Data Register Low Reset Value: 0000 0000 Field...
Page 540 XC886/888CLM Controller Area Network (MultiCAN) Controller Message Object n Data Register High MODATAH contains the highest four data bytes of message object n. Unused data bytes are set to zero upon reception and ignored for transmission. MODATAHn (n = 0-31) Message Object n Data Register High Reset Value: 0000 0000 Field...
Page 541: Multican Access Mediator Register
XC886/888CLM Controller Area Network (MultiCAN) Controller 15.2.4 MultiCAN Access Mediator Register CAN_ADCON CAN Address/ Data Control Register Reset Value: 0000 0000 AUAD RWEN Field Bits Type Description RWEN Read/Write Enable Read is enabled Write is enabled. Data Transmission Busy Data Transimission is finished. Data Transimission is in progress.
Page 542 XC886/888CLM Controller Area Network (MultiCAN) Controller Field Bits Type Description CAN Data 3 Valid Data in CAN_DATA3 register is not valid for transmission. Data in CAN_DATA3 register is valid for transmission. CAN_ADL Can Address Register Low Reset Value: 0000 0000 Field Bits Type Description...
Page 543 XC886/888CLM Controller Area Network (MultiCAN) Controller CAN_DATA0 CAN Data Register 0 Reset Value: 0000 0000 CD[7:0] Field Bits Type Description [7:0] CAN Data Byte 0 CAN_DATA1 CAN Data Register 1 Reset Value: 0000 0000 CD[15:8] Field Bits Type Description [7:0] CAN Data Byte 1 CAN_DATA2 CAN Data Register 2...
Page 544 XC886/888CLM Controller Area Network (MultiCAN) Controller CAN_DATA3 CAN Data Register 3 Reset Value: 0000 0000 CD[31:24] Field Bits Type Description [7:0] CAN Data Byte 3 User’s Manual 15-100 V1.3, 2010-02 MultiCAN, V1.0...
Page 545: Analog-To-Digital Converter
XC886/888CLM Analog-to-Digital Converter Analog-to-Digital Converter The XC886/888 includes a high-performance 10-bit Analog-to-Digital Converter (ADC) with eight multiplexed analog input channels. The ADC uses a successive approximation technique to convert the analog voltage levels from up to eight different sources. Features •...
Page 546: Structure Overview
XC886/888CLM Analog-to-Digital Converter 16.1 Structure Overview The ADC module consists of two main parts, i.e., analog and digital, with each containing independent building blocks. The analog part includes: • Analog input multiplexer (for selecting the channel to be converted) • Analog converter stage (e.g., capacitor network and comparator as part of the ADC) •...
Page 547: Clocking Scheme
XC886/888CLM Analog-to-Digital Converter 16.2 Clocking Scheme A common module clock f generates the various clock signals used by the analog and digital parts of the ADC module: • is input clock for the analog part. ADCA • is internal clock for the analog part (defines the time base for conversion length ADCI and the sample time).
Page 548: Conversion Timing
XC886/888CLM Analog-to-Digital Converter For module clock = 24 MHz, the analog clock frequency can be selected as ADCI shown in Table 16-1. Table 16-1 Frequency Selection ADCI Module Clock Prescaling Ratio Analog Clock ADCI 24 MHz ÷ 2 12 MHz (N.A) ÷...
Page 549 XC886/888CLM Analog-to-Digital Converter Synchronization Phase period is required for synchronization between the conversion start trigger ADCI (from the digital part) and the beginning of the sample phase (in the analog part). The BUSY and SAMPLE bits will be set with the conversion start trigger. Sample Phase During this period, the analog input voltage is sampled.
Page 550 XC886/888CLM Analog-to-Digital Converter Total Conversion Time CONV The total conversion time (synchronizing + sampling + charge redistribution) CONV given by: × (1 + r × (3 + n + STC)) (16.2) CONV where r = CTC + 2 for CTC = 00 , 01 or 10 r = 32 for CTC = 11...
Page 551: Low Power Mode
XC886/888CLM Analog-to-Digital Converter 16.3 Low Power Mode The ADC module may be disabled, either partially or completely, when no conversion is required in order to reduce power consumption. The analog part of the ADC module may be disabled by resetting the ANON bit. This causes the generation of to be stopped and results in a reduction in power ADCI...
Page 552: Functional Description
XC886/888CLM Analog-to-Digital Converter 16.4 Functional Description The ADC module functionality includes: • Two different conversion request sources (sequential and parallel) with independent registers. The request sources are used to trigger conversions due to external events (synchronization to PWM signals), sequencing schemes, etc. •...
Page 553: Request Source Arbiter
XC886/888CLM Analog-to-Digital Converter 16.4.1 Request Source Arbiter The arbiter can operate in two modes that are selectable by bit ARBM: • Permanent arbitration: In this mode, the arbiter will continuously poll the request sources even when there is no pending conversion request. •...
Page 554: Conversion Start Modes
XC886/888CLM Analog-to-Digital Converter 16.4.2 Conversion Start Modes At the end of each arbitration round, the arbiter would have found the request source with the highest priority and a pending conversion request. It stores the arbitration result, namely the channel number, the sample time and the targeted result register for further actions.
Page 555: Sequential Request Source
XC886/888CLM Analog-to-Digital Converter 16.4.4 Sequential Request Source A sequential request source requests one conversion after the other. The amount of channels requested for conversion depends on the length of the sequential buffer queue (number of queue stages). The sequential source register description can be found in Section 16.7.6.
Page 556 XC886/888CLM Analog-to-Digital Converter data written queue input register by CPU queue stage q-1 intermediate queue stages queue stage 1 queue stage 0 (CHNR, RF, ENSI) start of abort of conversion conversion backup stage (CHNR, RF, ENSI) ADC_seq_reqsrc_flow Figure 16-5 Multi-Stage Queue The automatic refill feature can be activated (RF = 1) to allow automatic re-insertion of the pending request into the queue stage after a successful execution (conversion start).
Page 557: Request Source Control
XC886/888CLM Analog-to-Digital Converter 16.4.4.2 Request Source Control If the conversion requested by the source is not related to an external trigger event (EXTR = 0), the valid bit V = 1 directly requests the conversion by setting signals REQPND and REQCHNRV to 1. In this case, no conversion will be requested if V = 0. A gating mechanism allows the user to enable/disable conversion requests according to bit ENGT.
Page 558: Parallel Request Source
XC886/888CLM Analog-to-Digital Converter 16.4.5 Parallel Request Source A parallel request source generates one or more channel conversion requests in parallel. The requests are always treated one after the other in a pre-defined sequence (higher channel numbers before lower channel numbers). The parallel source register description can be found in Section 16.7.7.
Page 559: Request Source Control
XC886/888CLM Analog-to-Digital Converter 16.4.5.2 Request Source Control All conversion pending bits are ORed together to deliver an intermediate signal PND for generating REQCHNRV and REQPND. The signal PND is gated with bit ENGT, allowing the user to enable/disable conversion requests. See Figure 16-7.
Page 560: External Trigger
XC886/888CLM Analog-to-Digital Converter 16.4.5.3 External Trigger The conversion request for the parallel source (and also the sequential source) can be synchronized to an external trigger event. For the parallel source, this is done by coupling the reload event to a request trigger input, REQTR. 16.4.5.4 Software Control The load event for the parallel source can also be generated under software control in two ways:...
Page 561: Wait-For-Read Mode
XC886/888CLM Analog-to-Digital Converter 16.4.6 Wait-for-Read Mode The wait-for-read mode can be used for all request sources to allow the CPU to treat each conversion result independently without the risk of data loss. Data loss can occur if the CPU does not read a conversion result in a result register before a new result overwrites the previous one.
Page 562 XC886/888CLM Analog-to-Digital Converter analog part conversion from channel result control result buffer boundary values result register 0 add/sub result register 1 result register 3 result path control limit check control channel interrupt data reduction control event interrupt Figure 16-8 Result Path Refer to Section 16.7.8 for description of the result generation registers.
Page 563: Limit Checking
XC886/888CLM Analog-to-Digital Converter 16.4.7.2 Limit Checking The limit checking and the data reduction filter are based on a common add/subtract structure. The incoming result is compared with BOUND0, then with BOUND1. Depending on the result flags (lower-than compare), the limit checking unit can generate a channel interrupt.
Page 564: Data Reduction Filter
XC886/888CLM Analog-to-Digital Converter 16.4.7.3 Data Reduction Filter Each result register can be controlled to enable or disable the data reduction filter. The data reduction block allows the accumulation of conversion results for anti-aliasing filtering or for averaging. conversion ready running conversion delivered result...
Page 565: Result Register View
XC886/888CLM Analog-to-Digital Converter After this addition, the complete result is stored in the selected result register. The result event is generated and the valid bit becomes set. It is possible to have an identical cycle behavior of the path to the result register, with the data reduction filter being enabled or disabled.
Page 566 XC886/888CLM Analog-to-Digital Converter Result Register x High Result Register x Low R9 R8 R7 R6 R5 R4 R3 R1 R0 VF DRC CHNR RESRxH RESRxL RESRAxH RESRAxL R6 R5 R4 R3 R2 R1 R0 VF DRC CHNR R7 R6 R5 R4 R3 R2 R1 VF DRC CHNR 8-bit conversion (with/without accumulation)
Page 567: Interrupts
XC886/888CLM Analog-to-Digital Converter 16.4.8 Interrupts The ADC module provides 2 service request outputs SR[1:0] that can be activated by different interrupt sources. The interrupt structure of the ADC supports two different types of interrupt sources: • Event Interrupts: Activated by events of the request sources (source interrupts) or result registers (result interrupts).
Page 568: Event Interrupts
XC886/888CLM Analog-to-Digital Converter 16.4.8.1 Event Interrupts Event interrupts can be generated by the request sources and the result registers. The event interrupt enable bits are located in the request sources (ENSI) and result register control (IEN). An interrupt node pointer (EVINP) for each event allows the selection of the targeted service output line.
Page 569: Channel Interrupts
XC886/888CLM Analog-to-Digital Converter 16.4.8.2 Channel Interrupts The channel interrupts occur when a conversion is completed and the selected limit checking condition is met. As a result, only one channel interrupt can be activated at a time. An interrupt can be triggered according to the limit checking result by comparing the conversion result with two selectable boundaries for each channel.
Page 570 XC886/888CLM Analog-to-Digital Converter CHINF0 CHINP0 to SR0 CHINF1 CHINP1 CHINF7 CHINP7 to SR1 channel number Figure 16-15 Channel Interrupt Routing User’s Manual 16-26 V1.3, 2010-02 ADC, V 1.0...
Page 571: External Trigger Inputs
XC886/888CLM Analog-to-Digital Converter 16.4.9 External Trigger Inputs The sequential and parallel request sources has one request trigger input REQTRx (x = 0 - 1) each, through which a conversion request can be started. The input to REQTRx is selected from eight external trigger inputs (ETRx0 to ETRx7) via a multiplexer depending on bit field ETRSELx.
Page 572: Adc Module Initialization Sequence
XC886/888CLM Analog-to-Digital Converter 16.5 ADC Module Initialization Sequence The following steps is meant to provide a general guideline on how to initialize the ADC module. Some steps may be varied or omitted depending on the application requirements: • Configure global control functions: –...
Page 573 XC886/888CLM Analog-to-Digital Converter – Generate a pending conversion request using any method described in Section 16.4.4.2 • Start parallel request: – Write to CRCR1 (no load event) or CRPR1 (automatic load event) the channels to be converted. – Generate a load event (if not already available) to trigger a pending conversion request, using any method described in Section 16.4.5.2 •...
Page 574: Register Map
XC886/888CLM Analog-to-Digital Converter 16.6 Register Map All ADC register names described in the following sections are referenced in other chapters of this document with the module name prefix “ADC_”, e.g., ADC_GLOBCTR. The addresses of the ADC SFRs are listed in Table 16-3 Table 16-4 Table 16-3...
Page 575 XC886/888CLM Analog-to-Digital Converter The ADC SFRs are located in the standard memory area (RMAP = 0) and are organized into 7 pages. The ADC_PAGE register is located at address D1 . It contains the page value and page control information. ADC_PAGE Page Register for ADC Reset Value: 00...
Page 576 XC886/888CLM Analog-to-Digital Converter Field Bits Type Description [7:6] Operation Manual page mode. The value of STNR is ignored and PAGE is directly written. New page programming with automatic page saving. The value written to the bit positions of PAGE is stored. In parallel, the former contents of PAGE are saved in the storage bit field STx indicated by STNR.
Page 577: Register Description
XC886/888CLM Analog-to-Digital Converter 16.7 Register Description This section describes all the registers which are associated with the functionalities of the ADC module. 16.7.1 General Function Registers Register GLOBCTR contains bits that control the analog converter and the conversion delay. GLOBCTR Global Control Register Reset Value: 30 ANON...
Page 578 XC886/888CLM Analog-to-Digital Converter Field Bits Type Description ANON Analog Part Switched On This bit enables the analog part of the ADC module and defines its operation mode. The analog part is switched off and conversions are not possible. To achieve minimal power consumption, the internal analog circuitry is in its power-down state and the generation of is stopped.
Page 579 XC886/888CLM Analog-to-Digital Converter Register GLOBSTR contains bits that indicate the current status of a conversion. GLOBSTR Global Status Register Reset Value: 00 CHNR SAMPLE BUSY Field Bits Type Description BUSY Analog Part Busy This bit indicates that a conversion is currently active.
Page 580: Priority And Arbitration Register
XC886/888CLM Analog-to-Digital Converter 16.7.2 Priority and Arbitration Register Register PRAR contains bits that define the request source priority and the conversion start mode. It also contains bits that enable/disable the conversion request treatment in the arbitration slots. PRAR Priority and Arbitration Register Reset Value: 00 ASEN1 ASEN0...
Page 581 XC886/888CLM Analog-to-Digital Converter Field Bits Type Description ASENx [7:6] Arbitration Slot x Enable (x = 0 - 1) Each bit enables an arbitration slot of the arbiter round. ASEN0 enables arbitration slot 0, ASEN1 enables slot 1. If an arbitration slot is disabled, a pending conversion request of a request source connected to this slot is not taken into account for arbitration.
Page 582: External Trigger Control Register
XC886/888CLM Analog-to-Digital Converter 16.7.3 External Trigger Control Register Register ETRCR contains bits that select the external trigger input signal source and enable synchronization of the external trigger input. ETRCR External Trigger Control Register Reset Value: 00 SYNEN1 SYNEN0 ETRSEL1 ETRSEL0 Field Bits Type Description...
Page 583: Channel Control Registers
XC886/888CLM Analog-to-Digital Converter 16.7.4 Channel Control Registers The channel control registers contain bits that select the targeted result register and control the limit check mechanism. Register CHCTRx defines the settings for the input channel x. CHCTRx (x = 0 - 5) Channel Control Register x + x * 1) Reset Value: 00...
Page 584: Input Class Register
XC886/888CLM Analog-to-Digital Converter 16.7.5 Input Class Register Register INPCR0 contains bits that control the sample time for the input channels. INPCR0 Input Class 0 Register Reset Value: 00 Field Bits Type Description [7:0] Sample Time Control This bit field defines the additional length of the sample time, given in terms of clock cycles.
Page 585: Sequential Source Registers
XC886/888CLM Analog-to-Digital Converter 16.7.6 Sequential Source Registers These registers contain the control and status bits of sequential request source 0. Register QMR0 contains bits that are used to set the sequential request source in the desired mode. QMR0 Queue Mode Register Reset Value: 00 TREV FLUSH...
Page 586 XC886/888CLM Analog-to-Digital Converter Field Bits Type Description TREV Trigger Event No action A trigger event is generated by software. If the source waits for a trigger event, a conversion request is started. Clear Event Bit No action Bit EV is cleared. 1, 3 Reserved Returns 0 if read;...
Page 587 XC886/888CLM Analog-to-Digital Converter Register QSR0 contains bits that indicate the status of the sequential source. QSR0 Queue Status Register Reset Value: 20 EMPTY FILL Field Bits Type Description FILL [1:0] Filling Level This bit field indicates how many entries are valid in the sequential-sourced queue.
Page 588 XC886/888CLM Analog-to-Digital Converter Field Bits Type Description Reserved Returns 1 if read; should be written with 0. Note: This bit is initialized to 0 immediately after reset, but is updated by hardware to 1 (and remains as 1) shortly after. [3:0], 6 Reserved Returns 0 if read;...
Page 589 XC886/888CLM Analog-to-Digital Converter Register Q0R0 contains bits that monitor the status of the current sequential request. Q0R0 Queue 0 Register 0 Reset Value: 00 EXTR ENSI REQCHNR Field Bits Type Description REQCHNR [2:0] Request Channel Number This bit field indicates the channel number that will be or is currently requested.
Page 590 XC886/888CLM Analog-to-Digital Converter Field Bits Type Description EXTR External Trigger This bit defines if the conversion request is sensitive to an external trigger event. The event flag (bit EV) indicates if an external event has taken place and a conversion can be requested. Bit EV is not used to start conversion request.
Page 591 XC886/888CLM Analog-to-Digital Converter The registers QBUR0 and QINR0 share the same register address. A read operation at this register address will deliver the ‘rh’ bits of the QBUR0 register, while a write operation to the same address will target the ‘w’ bits of the QINR0 register. Register QBUR0 contains bits that monitor the status of an aborted sequential request.
Page 592 XC886/888CLM Analog-to-Digital Converter Register QINR0 is the entry register for sequential requests. QINR0 Queue Input Register 0 Reset Value: 00 EXTR ENSI REQCHNR Field Bits Type Description REQCHNR [2:0] Request Channel Number This bit field defines the requested channel number. Refill This bit defines the refill functionality.
Page 593: Parallel Source Registers
XC886/888CLM Analog-to-Digital Converter 16.7.7 Parallel Source Registers These registers contain the control and status bits of parallel request source 1. Register CRCR1 contains the bits that are copied to the pending register (CRPR1) when the load event occurs. This register can be accessed at two different addresses (one read view, two write views).
Page 594 XC886/888CLM Analog-to-Digital Converter Register CRPR1 contains bits that request a conversion of the corresponding analog channel. The bits in this register have only a read view. A write operation to this address leads to a data write to CRCR1 with an automatic load event one clock cycle later. CRPR1 Conversion Request Pending Register 1(CB Reset Value: 00...
Page 595 XC886/888CLM Analog-to-Digital Converter Register CRMR1 contains bits that are used to set the request source in the desired mode. CRMR1 Conversion Request Mode Register 1 (CC Reset Value: 00 LDEV CLRPND SCAN ENSI ENTR ENGT Field Bits Type Description ENGT Enable Gate This bit enables the gating functionality for the request source.
Page 596 XC886/888CLM Analog-to-Digital Converter Field Bits Type Description CLRPND Clear Pending Bits No action The bits in register CRPR1 are reset. LDEV Generate Load Event No action The load event is generated. Reserved Returns 1 if read; should be written with 0. Note: This bit is initialized to 0 immediately after reset, but is updated by hardware to 1 (and remains as 1) shortly after.
Page 597: Result Registers
XC886/888CLM Analog-to-Digital Converter 16.7.8 Result Registers The result registers deliver the conversion results and, optionally, the channel number that has lead to the latest update of the result register. The result registers are available as different read views at different addresses. The following bit fields can be read from the result registers, depending on the selected read address.
Page 598 XC886/888CLM Analog-to-Digital Converter Field Bits Type Description Valid Flag for Result Register x This bit indicates that the contents of the result register x are valid. The result register x does not contain valid data. The result register x contains valid data. RESULT[1:0] [7:6] Conversion Result...
Page 599 XC886/888CLM Analog-to-Digital Converter Accumulated Read View RESRAx This view delivers the accumulated 9-bit or 11-bit conversion result and a 3-bit channel number. The corresponding valid flag is cleared when the high byte of the register is accessed by a read command, provided that bit RCRx.VFCTR is set. RESRAxL (x = 0 - 2) Result Register x, View A Low + x * 2)
Page 600 XC886/888CLM Analog-to-Digital Converter RESRAxH (x = 0 - 3) Result Register x, View A High + x * 2) Reset Value: 00 RESRA3H Result Register 3, View A High Reset Value: 00 RESULT[10:3] Field Bits Type Description RESULT[10:3] [7:0] Conversion Result This bit field contains the conversion result or the result of the data reduction filter.
Page 601 XC886/888CLM Analog-to-Digital Converter Writing a 1 to a bit position in register VFCR clears the corresponding valid flag in registers RESRx/RESRAx. If a hardware event triggers the setting of a bit VFx and VFCx = 1, the bit VFx is cleared (software overrules hardware). VFCR Valid Flag Clear Register Reset Value: 00...
Page 602 XC886/888CLM Analog-to-Digital Converter Field Bits Type Description DRCTR Data Reduction Control This bit defines how many conversion results are accumulated for data reduction. It defines the reload value for bit DRC. The data reduction filter is disabled. The reload value for DRC is 0, so the accumulation is done over 1 conversion.
Page 603: Interrupt Registers
XC886/888CLM Analog-to-Digital Converter 16.7.9 Interrupt Registers Register CHINFR monitors the activated channel interrupt flags. CHINFR Channel Interrupt Flag Register Reset Value: 00 CHINF7 CHINF6 CHINF5 CHINF4 CHINF3 CHINF2 CHINF1 CHINF0 Field Bits Type Description CHINFx Interrupt Flag for Channel x (x = 0 - 7) This bit monitors the status of the channel interrupt x.
Page 604 XC886/888CLM Analog-to-Digital Converter Writing a 1 to a bit position in register CHINSR sets the corresponding channel interrupt flag in register CHINFR and generates an interrupt pulse. CHINSR Channel Interrupt Set Register Reset Value: 00 CHINS7 CHINS6 CHINS5 CHINS4 CHINS3 CHINS2 CHINS1 CHINS0...
Page 605 XC886/888CLM Analog-to-Digital Converter Register EVINFR monitors the activated event interrupt flags. EVINFR Event Interrupt Flag Register Reset Value: 00 EVINF7 EVINF6 EVINF5 EVINF4 EVINF1 EVINF0 Field Bits Type Description EVINFx [1:0], Interrupt Flag for Event x (x = 0 - 1, 4 - 7) [7:4] This bit monitors the status of the event interrupt x.
Page 606 XC886/888CLM Analog-to-Digital Converter Writing a 1 to a bit position in register EVINSR sets the corresponding event interrupt flag in register EVINFR and generates an interrupt pulse (if the interrupt is enabled). EVINSR Event Interrupt Set Flag Register Reset Value: 00 EVINS7 EVINS6 EVINS5...
Page 607 XC886/888CLM Analog-to-Digital Converter The bit fields in register LCBR define the four MSB of the compare values (boundaries) used by the limit checking unit. The values defined in bit fields BOUND0 and BOUND1 are concatenated with either four (8-bit conversion) or six (10-bit conversion) 0s at the end to form the final value used for comparison with the converted result.
Page 608: On-Chip Debug Support
XC886/888CLM On-Chip Debug Support On-Chip Debug Support The On-Chip Debug Support (OCDS) provides the basic functionality required for software development and debugging of XC800-based systems. The OCDS design is based on these principles: • Use the built-in debug functionality of the XC800 Core •...
Page 609: Functional Description
XC886/888CLM On-Chip Debug Support 17.2 Functional Description The OCDS functional blocks are shown in Figure 17-1. The Monitor Mode Control (MMC) block at the center of OCDS system brings together control signals and supports the overall functionality. The MMC communicates with the XC800 Core, primarily via the Debug Interface, and also receives reset and clock signals.
Page 610: Debugging
XC886/888CLM On-Chip Debug Support Note: All the debug functionality described here can normally be used only after XC886/888 has been started in OCDS mode. For more information on boot configuration options, see Chapter 7.2.3. Attention: As long as the OCDS is actively used, the application software should not change the TRAP_EN bit within Extended Operation (EO) register! 17.3 Debugging...
Page 611: Hardware Breakpoints
XC886/888CLM On-Chip Debug Support 17.3.1.1 Hardware Breakpoints Hardware breakpoints are generated by observing certain address buses within the XC886/888 system. The bus relevant to the hardware breakpoint type is continuously compared against certain registers where addresses for the breakpoints have been programmed.
Page 612: Software Breakpoints
XC886/888CLM On-Chip Debug Support The OCDS differentiates between a breakpoint on read and a breakpoint on write operation to the IRAM. Configurations of Hardware Breakpoints The OCDS allows setting of up to 4 hardware breakpoints. In XC886/888, the Program Memory address is 16-bit wide, while the Internal Data Memory address (both for Read and Write) is 8-bit wide.
Page 613: External Breaks
XC886/888CLM On-Chip Debug Support Note: In order to continue user program execution after the debug event, an external Debugger must restore the original opcode at the address of the current software breakpoint. 17.3.1.3 External Breaks These debug events are of Break Now type and can be raised in two ways: •...
Page 614: Activate The Mbc Pin
XC886/888CLM On-Chip Debug Support Once started, the Monitor runs with own stack- and data- memory (see Monitor RAM in Figure 17-1), which guarantees that all of the core and memory resources will be found untouched when returning control back to the user program. Therefore the OCDS- debugging in XC886/888 is fully non-destructive.
Page 615 XC886/888CLM On-Chip Debug Support Also suspending the other timer-modules makes sense for debugging: once the application is not running, stopping counters helps for a more complete “freeze” of the device-status during a break. It must be noted, in XC886/888 all of the debug suspend control bits (global enable in OCDS and individual selections in SCU) have values 0 after reset, i.e.
Page 616: Register Description
XC886/888CLM On-Chip Debug Support 17.5 Register Description From a programmer’s point of view, OCDS is represented in XC886/888 by a total of 10 register-addresses (see Table 17-1), all located within the mapped SFR area. Table 17-1 OCDS Directly Addressable Registers Register Address Register Full Name...
Page 617 XC886/888CLM On-Chip Debug Support The OCDS registers are exclusively dedicated to the on-chip Monitor program and the user should not write into them. Anyway a big part of these registers or separate bits/fields are protected and can not be written by user software but only by the firmware in two modes of XC886/888: •...
Page 618: Input Select Registers
XC886/888CLM On-Chip Debug Support 17.5.2 Input Select Registers Bits MODPISEL.JTAGTCKS and MODPISEL1.JTAGTCKS1 are used to select one of the three TCK inputs while bits MODPISEL.JTAGTDIS and MODPISEL1.JTAGTDIS1 are used to select one of the three TDI inputs. MODPISEL Peripheral Input Select Register Reset Value: 00 JTAGTCK URRISH JTAGTDIS...
Page 619: Jtag Id
XC886/888CLM On-Chip Debug Support Field Bits Type Description JTAGTDIS1 JTAG TDI Input Select 1 JTAG TDI Input TDI_2 is not selected JTAG TDI Input TDI_2 is selected. Note: If this bit is set, JTAG TDI input TDI_2 is selected regardless of the bit JTAGTDIS in register MODPISEL.
Page 620: Bootstrap Loader
XC886/888CLM Bootstrap Loader Bootstrap Loader The XC886/888 includes a Bootstrap Loader (BSL) Mode that can be entered with the pin configuration shown in Table 18-1 during hardware reset. The main purpose of BSL Mode is to allow easy and quick programming/erasing of the Flash and XRAM via serial interface.
Page 621: Uart And Lin Bsl Modes
XC886/888CLM Bootstrap Loader 18.1 UART and LIN BSL Modes The UART and LIN BSL Modes have three functional parts represented by the three phases described below: • Phase I: Establish a serial connection and automatically synchronize to the transfer speed (baud rate) of the serial communication partner (host). •...
Page 622: Communication Protocol
XC886/888CLM Bootstrap Loader 18.1.1 Communication Protocol Once baud rate is established, the host sends a block of information to the microcontroller to select the desired mode. All blocks follow the specified block structure as shown in Section 18.1.1.1 for UART and Section 18.1.1.2 for LIN.
Page 623: Lin Transfer Block Structure
XC886/888CLM Bootstrap Loader 18.1.1.2 LIN Transfer Block Structure A LIN transfer block, 9 bytes long (fixed), consists of four parts: Block Type Data Area Checksum (1 byte) (1 byte) (6 bytes) (1 byte) • NAD: Node Address for Diagnostic, which specifies the address of the active slave node to 7E Valid Slave Address...
Page 624 XC886/888CLM Bootstrap Loader An illustration on the Programming Checksum and LIN Checksum calculation is provided Table 18-3 for data of 4A , 55 , 93 and E5 Table 18-3 LIN Frame - Programming Checksum Addition of data Result CARRY Addition with CARRY ) + 55 ) + 93 0132...
Page 625: Response Code To The Host
XC886/888CLM Bootstrap Loader 18.1.1.3 Response Code to the Host The microcontroller would let the host know whether a block has been successfully received by sending out a response code. Table 18-4 tabulates the possible responses from the microcontroller upon reception of a Header, Data or EOT block for each working mode.
Page 626 XC886/888CLM Bootstrap Loader Table 18-5 lists the responses with the possible reasons and/or implcations for error and suggests the possible corrective actions that the host can take upon notification of the error. Table 18-5 Definition of Responses Response Value Description Block Reasons / Implications Corrective Action...
Page 627: Bootstrap Loader Via Uart
XC886/888CLM Bootstrap Loader 18.1.2 Bootstrap Loader via UART Upon entering UART BSL, a serial connection is established and the transfer speed (baud rate) of the serial communication partner (host) is automatically synchronized in the following steps: • STEP 1: Initialize serial interface for reception and timer for baud rate measurement •...
Page 628: Communication Structure
XC886/888CLM Bootstrap Loader 18.1.2.1 Communication Structure There are two types of transfer flow of the Header Block, Data Block, EOT Block, and the Response Code, as shown in Figure 18-1. One is adopted by Mode 0 and Mode 2, while the other is adopted by the rest of the modes. Data and EOT Blocks are transferred only in Mode 0 and 2.
Page 629: The Selection Of Modes
XC886/888CLM Bootstrap Loader 18.1.2.2 The Selection of Modes When UART BSL routine enters Phase II, it first awaits for an 8-byte Header Block, from the host which contains the information for the selection of the modes, as shown below. Data Area Block Type Checksum Mode...
Page 630 XC886/888CLM Bootstrap Loader Not used: 2 bytes, these bytes are not used and will be ignored in Mode 0/2. After the header block is successfully received, the microcontroller enters Mode 0/2, during which the program code is transmitted from the host to the microcontroller by Data Block and EOT Block, which are described below.
Page 631: The Activation Of Modes 1, 3 And F
XC886/888CLM Bootstrap Loader 18.1.2.4 The Activation of Modes 1, 3 and F Modes 1 and 3 are used to execute a user program in the XRAM/Flash of the microcontroller at 0F000 and 0000 respectively, while Mode F is used to enter OCDS UART Mode.
Page 632 XC886/888CLM Bootstrap Loader PFlash_Bank_Pair1 : The sectors 0 to 2 of P-Flash Bank Pair 1 (Banks 2 and 3) are represented by bits 0 to 2 . For example, a value of 05 in the PFlash_Bank_Pair1 byte selects sectors 0 and 2 of P-Flash Banks 2 and 3 for erase. PFlash_Bank_Pair2 : The sectors 0 to 2 of P-Flash Bank Pair 2 (Banks 4 and 5) are represented by bits 0 to 2...
Page 633 XC886/888CLM Bootstrap Loader The Header Block Mode Data (5 bytes) Checksum (Header Not Used Option (Mode 4) Block) (4 bytes) = C0 Mode Data Description: Not used: The four bytes are not used and will be ignored. Note: Un-wanted / un-selected bits should be cleared to 0 Note: It is not possible to erase select specified sectors for P-Flash and D-Flash with this mode 4.
Page 634: The Activation Of Mode A
XC886/888CLM Bootstrap Loader 18.1.2.7 The Activation of Mode A Mode A is used to obtain a 4-byte data. The contents of the 4-byte data is determined by the Option byte in the header block. The header block for this mode has the following structure: The Header Block Mode Data (5 bytes)
Page 635: Bootstrap Loader Via Lin
XC886/888CLM Bootstrap Loader 18.1.3 Bootstrap Loader via LIN Standard LIN protocol can support a maximum baud rate of 20 kHz. However, the XC886/888L device has an enhanced feature which supports a baud rate of up to 115.2 kHz. LIN BSL is implemented to support the baud rate of 20 kHz and below using standard LIN protocol, while Fast LIN BSL is introduced to support the baud rate of 20 kHz to 115.2 kHz via a single-wire UART using UART protocol.
Page 636: Communication Structure
XC886/888CLM Bootstrap Loader • Protected Identifier (ID) field (3C or 7D The Break is used to indicate the beginning of a new frame and it must be at least 13 bits of dominant value. When a negative transition is detected at pin T2EX at the beginning of Break, the Timer 2 External Start Enable bit (T2MOD.T2RHEN) is set.
Page 637 XC886/888CLM Bootstrap Loader Host Microcontroller Phase I: Synchronize Master Request Header and Set up Baud rate Command Phase II: Selection of Working Mode for valid command Slave Response Header Phase I: Synchronize and Set up Baud rate Response Phase III: Report its status to the host Figure 18-3 LIN BSL - Phases I, II and III LIN BSL...
Page 638: The Selection Of Modes
XC886/888CLM Bootstrap Loader 18.1.3.2 The Selection of Modes When the LIN BSL routine enters Phase II, it first awaits for a 9-byte Header Block, from the host which contains the information for the selection of the modes, as shown below. Data Area Block Type Checksum...
Page 639 XC886/888CLM Bootstrap Loader send a block-type error. PC Host will then have to re-send the whole series of blocks (Header, Data and EOT Blocks). Not used: This byte is not used and will be ignored in Mode 0/2/8. Fast_Prog: Indication byte to enter Fast LIN BSL •...
Page 640: The Activation Of Modes 1, 3 And 9
XC886/888CLM Bootstrap Loader Internally, the microcontroller will transfer the valid data (6 bytes) of the Data Block into a buffer, and count the number of data bytes received. Microcontroller will program the data once the maximum buffer size is reached. If an EOT Block is received before maximum bytes are reached, then the remaining data bytes are programmed.
Page 641: The Activation Of Mode 6
XC886/888CLM Bootstrap Loader The Header Block Mode Data (5 bytes) Checksum PFlash PFlash PFlash (Header Option (1 byte) (Mode 4) (1 byte) _Bank _Bank _Bank Used Block) = 00 _Pair0 _Pair1 _Pair2 Mode data description can be referred at Section 18.1.2.5.
Page 642 XC886/888CLM Bootstrap Loader The Header Block Mode Data (5 bytes) Checksum (Header User-Password Not Used (1 byte) (Mode 6) (1 byte) Block) (1 byte) (4 bytes) Mode data description can be referred at Section 18.1.2.6. User’s Manual 18-23 V1.3, 2010-02 Bootstrap Loader, V1.0...
Page 643: The Activation Of Mode A
XC886/888CLM Bootstrap Loader 18.1.3.7 The Activation of Mode A Mode A is used to get 4 bytes data determined by the Option byte in the header block. The header block for this mode has the following structure: The Header Block Mode Data (5 bytes) Checksum (Header...
Page 644: Fast Lin Bsl
XC886/888CLM Bootstrap Loader 18.1.3.9 Fast LIN BSL Fast LIN BSL is an enhanced feature in XC886/888 device, supporting higher baud rate up to 115.2KHz. This is higher than Standard LIN, which supports only a baud rate of up to 20 kHz. This mode is especially useful during back-end programming, where faster programming time is desirable.
Page 645 XC886/888CLM Bootstrap Loader Table 18-6 LIN BSL After-Reset Conditions First Check Block Mode Action Frame Type (Header only) Invalid Don’t Don’t Don’t Don’t Save LIN message to XRAM and care care care care jump to Flash 0000 Invalid Don’t Don’t Don’t Don’t Message is ignored.
Page 646: User Defined Parameter For Lin Bsl
XC886/888CLM Bootstrap Loader 18.1.3.11 User Defined Parameter for LIN BSL The NAD (Node Address for Diagnostic) value, which specifies the address of the active slave node for the LIN modes, is programmed into the uppermost P-Flash bank pair. This parameter is specified by the user. There are two cases to consider when reading the programmed value: one, when the Flash is unprotected;...
Page 647 XC886/888CLM Bootstrap Loader The default NAD value is assumed in the following two cases for protected Flash: 1. LSB of user password is 0. 2. LSB of user password is 1 and user programmed NAD is invalid. Note: For a variant device with LIN BSL support, it must be ensured that a valid NAD is programmed before protecting the device.
Page 648: Multican Bsl Mode
XC886/888CLM Bootstrap Loader 18.2 MultiCAN BSL Mode MultiCAN BSL can be entered only when Flash is not protected, else user mode is entered instead and code from memory address location 0000 will be executed. The MultiCAN BSL protocol is divided into two sections, hardware initialisation and software communication.
Page 649: Can Message Object Definition
XC886/888CLM Bootstrap Loader Control Arbitration Field CRC Field End of Frame Data field (0...64 bits) Field Field (12 bits) (16 bits) (7 bits) (6 bits) (2 bits) Data Length Identifier Field RTR Bit IDE Bit Reserved CRC Sequence Code Delimiter Delimiter (11 bits) (1 bit)
Page 650 XC886/888CLM Bootstrap Loader The message identifier is 555 and the data length code is set to 8. Control Data field Arbitration Field CRC Field End of Frame Field Field Data 7 = DATA Identifier High Byte Data 6 = DATA Identifier Low Byte Data 5 = Number of Messages to receive High Byte Data 4 = Number of Messages to receive Low Byte Data 3 = ACK Identifier High Byte...
Page 651: User Defined Parameter For Multican Bsl
XC886/888CLM Bootstrap Loader 18.2.3 User Defined Parameter for MultiCAN BSL The OSC value, which specifies the oscillator frequency connected to the device, is programmed into the uppermost P-Flash bank pair. This parameter is specified by the user. Table 18-9 shows the address, supported values and default value of the user defined parameter for unprotected Flash.
Page 652: Index
XC886/888CLM Index Index 19.1 Keyword Index This section lists a number of keywords which refer to specific details of the XC886/888 in terms of its architecture, its functional units, or functions. Boot ROM 3-1 Boot ROM operating mode 3-41 Accumulator 2-3 BootStrap Loader Mode 3-42 Alternate functions 6-10 OCDS mode 3-43...
Page 653 XC886/888CLM Index 15-27 Clock management 7-15 Message object FIFO 15-34 Clock source 7-13 Message object functionality 15-33 Clock system 7-11 Message object interrupts 15-23 Register description 7-17 Message object lists 15-13 Conversion error 16-4 Node control 15-8 Conversion phase 16-5 Node interrupts 15-11 CORDIC 11-1 Register map 15-46...
Page 654 XC886/888CLM Index Non-volatile 4-1 Operating modes 4-11 Data Flash 4-2, 4-3 Power-down mode 4-11 Address mapping 3-3, 4-3 Program mode 4-11 Data memory 3-4 Ready-to-read mode 4-11 Data pointer 2-3 Sector 4-4 Data reduction 16-19 Flash devices 3-1 Counter 16-20 Flash memory protection 3-6 Debug 17-3 Flash program memory 3-1...
Page 655 XC886/888CLM Index CPU state 2-6 Minimum program width 4-9 Mnemonic 2-9 Modulation 14-15 Wait state 2-6 Monitor mode control 17-2 In-System Programming 4-14 Monitor RAM 17-2 Internal analog clock 16-3 Data 17-7 Maximum frequency 16-3 Stack 17-7 Internal data memory 3-4 Monitor ROM 17-2 Internal RAM 3-1 MultiCAN BSL 18-29...
Page 656 XC886/888CLM Index Offset addresses 6-11 Pull-down device 6-8 Open drain control register 6-8 Pull-up device 6-8 Normal mode 6-2, 6-8 Pulse width modulation 14-1 Open drain mode 6-2, 6-8 Parallel Read 4-5 Parallel request source 16-14 Read access time 4-1 Password 3-7 Read-out protection 3-6 Peripheral clock management 8-5...
Page 657 XC886/888CLM Index Half-duplex operation 12-36 Duty cycle 14-8 Interrupts 12-41 Edge-aligned mode 14-4 Low power mode 12-44 Hysteresis-like control mode 14-10 Master mode 12-31 Shadow transfer 14-3 Operating mode 12-32 Single-shot mode 14-10 Port control 12-38 Three-phase PWM 14-1 Register description 12-45 Timer T13 14-12 Register map 12-44 Compare mode 14-13...
Page 658 XC886/888CLM Index Window boundary 9-2 Wordline address 4-6 Write buffers 4-9 Write result phase 16-5 XC886/888 Device configuration 1-2 Device profile 1-3 Feature summary 1-4 Functional units 1-2 XRAM 3-1 User’s Manual 19-7 V1.3, 2010-02...
Page 659: Register Index
XC886/888CLM 19.2 Register Index This section lists the references to the Special Function Registers of the XC886/888. CAN_PANCTR 15-48 CC63RH 14-53 ACC 2-3 CC63RL 14-53 ADC_PAGE 16-31 CC63SRH 14-54 ADCON 15-97 CC63SRL 14-54 ADH 15-98 CC6xRH 14-48 ADL 15-98 CC6xRL 14-48 CC6xSRH 14-49 CC6xSRL 14-48 B 2-3...
Page 660 XC886/888CLM EO 2-5 LCBR 16-63 ETRCR 16-38 EVINCR 16-61 EVINFR 16-61 MCMCTR 14-78 EVINPR 16-62 MCMOUTH 14-77 EVINSR 16-62 MCMOUTL 14-75 EXICON0 5-21 MCMOUTSH 14-74 EXICON1 5-22 MCMOUTSL 14-73 MD4 10-9 MDUCON 10-11 FDCON 12-19 MDUSTAT 10-13 FDRES 12-21 MDx (x = 0 - 5) 10-9 FDSTEP 12-20 MISC_CON 3-9 FEAH 4-13...
Page 661 XC886/888CLM P1_OD 6-25 Px_ALTSELn 6-10 P1_PUDEN 6-26 Px_DATA 6-6 P1_PUDSEL 6-25 Px_DIR 6-7 P2_DATA 6-30 Px_OD 6-8 P2_DIR 6-30 Px_PUDEN 6-9 P2_PUDEN 6-31 Px_PUDSEL 6-9 P2_PUDSEL 6-31 P3_ALTSEL0 6-38 P3_ALTSEL1 6-38 Q0R0 16-45 P3_DATA 6-36 QBUR0 16-47 P3_DIR 6-36 QINR0 16-48 QMR0 16-41 P3_OD 6-37 P3_PUDEN 6-38...
Page 662 XC886/888CLM T13PRL 14-52 T2CON 13-25 T2H 13-28 T2L 13-28 T2MOD 13-24 TBL 12-51 TCON 5-24, 5-29, 13-11 TCTR2H 14-64 TCTR2L 14-62 TCTR4H 14-66 TCTR4L 14-65 TCTROH 14-60 TCTROL 14-59 THx (x = 0 - 1) 13-10 TLx (x = 0 - 1) 13-10 TMOD 13-12 TRPCTRH 14-71 TRPCTRL 14-69...
Page 663 . i n f i n e o n . c o m Published by Infineon Technologies AG...

This manual is also suitable for:

Xc888clm

Infineon XC886CLM User Manual

1 Introduction

2 Processor Architecture

3 Memory Organization

4 Flash Memory

5 Interrupt System

6 Parallel Ports

7 Power Supply, Reset and Clock Management

8 Power Saving Modes

9 Watchdog Timer

10 Multiplication/Division Unit

11 CORDIC Coprocessor

12 Serial Interfaces

13 Timers

14 Capture/Compare Unit 6

15 Controller Area Network (Multican) Controller

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