Sign In
Upload
Download
Table of Contents
Contents
Add to my manuals
Delete from my manuals
Share
URL of this page:
HTML Link:
Bookmark this page
Add
Manual will be automatically added to "My Manuals"
Print this page
×
Bookmark added
×
Added to my manuals
Manuals
Brands
AMD Manuals
Microcontrollers
Am186 CU
User manual
AMD Am186 CU User Manual
Hide thumbs
1
2
3
4
Table Of Contents
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
page
of
376
Go
/
376
Contents
Table of Contents
Bookmarks
Table of Contents
Table of Contents
Preface
Introduction
Comm86 Family
Purpose of this Manual
Intended Audience
Overview of this Manual
Related Documents
AMD Documentation
Additional Information
Documentation Conventions
Table 0-1 Documentation Conventions
Microcontroller-Specific Information
Chapter 1 Architectural Overview
Features
Am186Cc Communications Controller
Am186Ch HDLC Microcontroller
Am186Cu USB Microcontroller
Feature Comparison
Table 1-1 Feature Comparison
Figure 1-1 Am186Cc Communications Controller Block Diagram
Figure 1-2 Am186Ch HDLC Microcontroller Block Diagram
Figure 1-3 Am186Cu USB Microcontroller Block Diagram
Am186 Embedded CPU
Serial Communications Support
Universal Serial Bus
HDLC Channels and Tsas
General Circuit Interface
Smartdma Channels
Asynchronous Serial Ports
Synchronous Serial Port
System Peripherals
Interrupt Controller
General-Purpose DMA Channels
Programmable I/O Signals
Programmable Timers
Hardware Watchdog Timer
Memory and Peripheral Interface
Dynamic Random Access Memory Support
System Interfaces and Clock Control
Chip Selects
In-Circuit Emulator Support
Figure 1-4 ISDN Terminal Adapter
Figure 1-5 ISDN-To-Ethernet Low-End Router
Figure 1-6 32-Channel Linecard
Processor Registers
Table 2-1 Internal Processor Registers
CHAPTER 2 CONFIGURATION BASICS 2.1 Overview
Processor Status Flags Register
Figure 2-2 Processor Status Flags Register
Peripheral Registers
Table 2-2 Configuration Register Summary
Table 2-3 Peripheral Register Summary
Figure 2-3 Physical Address Generation
Data Types
Table 2-4 Segment Register Selection Rules
Addressing Modes
Register and Immediate Operands
Memory Operands
Figure 2-5 Supported Data Types
Table 2-5 Memory Addressing Mode Examples
CHAPTER 3 SYSTEM OVERVIEW 3.1 Overview
Table 3-2 Multiplexed Signal Trade-Offs Ordered by PIO
System Configuration
Table 3-3 System Configuration Register Summary
Initialization and Reset
Table 3-4 CPU and Internal Peripheral States Immediately Following Power-On Reset
Table 3-5 Reset Configuration Pins (Pinstraps)
Signal Descriptions
Table 3-6 Signal Descriptions Table Definitions
Table 3-7 Signal Descriptions
Bus Interface
Overview
Block Diagrams
Figure 3-1 Typical Microcontroller Memory System with DRAM
Figure 3-2 Typical Microcontroller Memory System with SRAM
Address and Data Buses
Operation
Programmable Bus Sizing
Bus Mastering
Byte Write Enables
Output Enable
Table 3-8 Programming Am186Cc/Ch/Cu Microcontrollers Bus Width
DRAM Controller
Clock Control
Clock Features
Figure 3-3 Am186Cc/Ch/Cu Microcontroller Clocks
PLL Bypass Mode
Hardware-Related Considerations
Comparison to Other Devices
Initialization
System Overview
Overview
System Design
Table 3-1 Multiplexed Signal Trade-Offs
Chapter 4 Emulator Support
Overview
System Design
Multiplexed Pins
Emulator Connection
Operation
Usage
Emulator-Related Signals
A19-A0
Ad15-Ad0
Aden} / Bhe
Ale
ARDY and SRDY
Bhe
Bsize8
CAS1-CAS0] and [RAS1-RAS0]
Clkout
Lcs
Mcs3-Mcs0
Once
Qs1-Qs0
Ras1-Ras0]
Res
Resout
Hardware-Related Considerations
S2-S0
Srdy
Ucs
UCSX8} and WLB
WHB and WR
Wlb
Comparison to Other Devices
Initialization
Chapter 5 Chip Selects
Overview
Block Diagram
System Design
Figure 5-1 Chip Selects and DRAM Block Diagram
Registers
Table 5-1 Chip Selects Multiplexed Signals
Table 5-2 Chip Select Register Summary
Operation
Usage
Selecting Memory and I/O Space
Lcs
Mcs3-Mcs0
Ucs
Pcs7-Pcs0
Selecting DRAM Using the Chip Selects
Figure 5-3 Chip Selectable I/O Space
Table 5-3 Signal Function When UCS or LCS Is Configured for DRAM
Overlapping Chip Selects
Configuring Address and Data Buses
Non-UCS and Non-LCS
PCS I/O Space
UCS and LCS
Programming Ready Signals and Wait States
Chip Select Timing
Hardware-Related Considerations
Software-Related Considerations
Comparison to Other Devices
Initialization
Chapter 6 Dram Controller
Overview
Block Diagram
System Design
Figure 6-1 Chip Selects and DRAM Block Diagram (same as Figure 5-1)
Table 6-1 DRAM Multiplexed Signals
Registers
Operation
Usage
DRAM Supported
Table 6-2 DRAM Controller Register Summary
DRAM Interface
Table 6-3 DRAM Supported by the Am186Cc/Ch/Cu Microcontrollers
Table 6-4 Address Multiplexing Reference
Option to Overlap DRAM with PCS
DRAM Refresh
DRAM Refresh Cycle
DRAM Refresh Intervals
Hardware-Related Considerations
Software-Related Considerations
Table 6-5 Refresh Interval Times
Comparison to Other Devices
Initialization
Chapter 7 Interrupts
Overview
Block Diagram
System Design
Figure 7-1 Interrupts Block Diagram
Table 7-1 Interrupt Multiplexed Signals
Registers
Registers
Table 7-2 Interrupt Controller Register Summary
Operation
Usage
Types of Interrupt Channels
Using Maskable Interrupts
Using Nonmaskable Interrupts
Definitions of Interrupt Terms
Interrupt Sequence
Figure 7-2 Interrupt Vector Translation
Requesting the Interrupt
Acknowledging the Interrupt
End-Of-Interrupt (EOI)
Returning from the Interrupt
Servicing the Interrupt
Interrupt Priority
Maskable Hardware Interrupt Priority
Nonmaskable Interrupt and Software Interrupt Priority
Table 7-3 Interrupt Types
Maskable Interrupts
Maskable Interrupt Cycle
Considerations for NMI, Software Interrupts, and Traps
Interrupts in Polled Mode
Maskable Interrupt Overview
Figure 7-3 Partial Block Diagram of Interrupt Controller Scheme
Maskable Interrupt Block Diagram
Table 7-4 Interrupt Channel Map
Table 7-5 Interrupt Channel Sources
Pios as Interrupts
Registers Used
Nonmaskable Interrupts
Breakpoint Interrupt (Interrupt Type 03H)
Divide Error Exception (Interrupt Type 00H)
INT0 Detected Overflow Exception (Interrupt Type 04H)
Nonmaskable Interrupt (Interrupt Type 02H)
Software Interrupts
Trace Interrupt (Interrupt Type 01H)
Array Bounds Exception (Interrupt Type 05H)
ESC Opcode Exception (Interrupt Type 07H)
Unused Opcode Exception (Interrupt Type 06H)
Software-Related Considerations
Comparison to Other Devices
Initialization
Chapter 8 Dma Controller
Overview
Block Diagram
Figure 8-1 DMA Block Diagram
System Design
Registers
Table 8-1 DMA Multiplexed Signals
Table 8-2 DMA Controller Register Summary
Operation
Table 8-3 Am186Cc Communications Controller DMA Channel Use
Table 8-4 Am186Ch HDLC Microcontroller DMA Channel Use
DMA Priority
Table 8-5 Am186Cu USB Microcontroller DMA Channel Use
When to Use DMA
DMA Acknowledge
DMA and Interrupts
DMA Request Synchronization
Figure 8-2 Source Versus Destination Synchronization
General-Purpose DMA Channels
Table 8-6 General-Purpose DMA Data Transfers
General-Purpose DMA Cycle
General-Purpose DMA Usage
General-Purpose DMA Source and Destination Addresses
General-Purpose DMA Transfer Suspension
General-Purpose DMA Terminal Count
Figure 8-3 DMA Request Sources
Table 8-7 General-Purpose DMA Request Source and Synchronization
Figure 8-4 Source-Synchronized General-Purpose DMA Transfers
Figure 8-5 Destination-Synchronized General-Purpose DMA Transfers
Table 8-8 Maximum DMA Transfer Rates
Table 8-9 Example Register Settings for Uarts and Circular Buffers
Smartdma Channels
Smartdma Channels Introduction
Smartdma Channel Memory Overview
Smartdma Channel Request Source and Synchronization
Table 8-10 Am186Cc Smartdma Channel Request Source and Synchronization
Table 8-11 Am186Ch Smartdma Channel Request Source and Synchronization
Table 8-12 Am186Cu Smartdma Channel Request Source and Synchronization
Figure 8-6 Smartdma Channel Descriptor Ring Example
Figure 8-7 Smartdma Channel Memory Management
Smartdma Channel Usage
Smartdma Channel Cycle
Figure 8-8 Smartdma Transmit Channel Flow Diagram
Figure 8-9 Smartdma Receive Channel Flow Diagram
Smartdma Channel Descriptor Format
Table 8-13 Smartdma Transmit Channel Descriptor Format
Table 8-14 Smartdma Receive Channel Descriptor Format
Smartdma Channel Descriptor Polling
Smartdma Channel Interrupts
Smartdma Channel Use Without CPU Intervention
DMA and USB
Software-Related Considerations
Initialization
CHAPTER 9 PROGRAMMABLE I/O SIGNALS 9.1 Overview
Figure 9-1 PIO Operation Block Diagram
System Design
Table 9-1 PIO Multiplexed Signals
Defining the PIO Signal as Input or Output
Registers
Table 9-2 PIO Register Summary
Usage
Driving Data on the PIO
Setting and Clearing Data
Table 9-3 PIO Mode and PIO Direction Register Bit Settings
Table 9-4 PIO Set and PIO Clear Registers' Effect on PIO Data Register
Using Pios as Open-Drain Outputs
Comparison to Other Devices
Hardware-Related Considerations
Software-Related Considerations
Figure 10-1 Programmable Timers Block Diagram
Overview
System Design
Table 10-1 Programmable Timer Multiplexed Signals
Table 10-2 Programmable Timers Register Summary
Operation
Table 10-3 Timer 0 and Timer 1 Behavior
Advertisement
Quick Links
Download this manual
™
Am186
CC/CH/CU Microcontrollers
User's Manual
Order #21914B
Table of
Contents
Previous
Page
Next
Page
1
2
3
4
5
Advertisement
Table of Contents
Need help?
Do you have a question about the Am186 CU and is the answer not in the manual?
Ask a question
Questions and answers
Related Manuals for AMD Am186 CU
Microcontrollers AMD Am186 User Manual
Cc/ch/cu microcontroller customer development platform (168 pages)
Microcontrollers AMD Am186 Series Instruction Set
(320 pages)
Microcontrollers AMD Am186 CC User Manual
(376 pages)
Microcontrollers AMD Am186 CH User Manual
(376 pages)
Microcontrollers AMD Am186 ES User Manual
(192 pages)
Microcontrollers AMD Am188 ES User Manual
(192 pages)
Microcontrollers AMD Am188 Series Instruction Set
(320 pages)
Microcontrollers AMD AM186EM User Manual
(186 pages)
Microcontrollers AMD XILINX Kria KR260 User Manual
Robotics starter kit (27 pages)
Microcontrollers AMD Elan SC520 User Manual
(444 pages)
Table of Contents
Print
Rename the bookmark
Delete bookmark?
Delete from my manuals?
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL
Need help?
Do you have a question about the Am186 CU and is the answer not in the manual?
Questions and answers