Table of Contents
Advertisement
Quick Links
Advertisement
Chapters
Table of Contents
Related Manuals for AMD Elan SC520
Summary of Contents for AMD Elan SC520
- Page 1 ™ Élan SC520 Microcontroller User’s Manual Order #22004A...
- Page 2 AMD’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a situation where personal injury, death, or severe property or environmental damage may occur.
- Page 3 Technical Support Answers to technical questions are available online, through e-mail, and by telephone. Go to AMD’s home page at www.amd.com and follow the Service link for the latest AMD technical support phone numbers, software, and Frequently Asked Questions. For technical support questions on all E86 products, send e-mail to epd.support@amd.com (in the US and Canada) or euro.tech@amd.com (in Europe and...
- Page 4 Élan™SC520 Microcontroller User’s Manual...
-
Page 5: Table Of Contents
AMD Documentation ........ - Page 6 Table of Contents 3.7.2 Address Region Attributes......3-12 3.7.2.1 Write-Protect Attribute ......3-12 3.7.2.2 Cacheability Control Attribute .
- Page 7 Table of Contents CHAPTER 5 CLOCK GENERATION AND CONTROL 5.1 Overview ..........5-1 5.2 Block Diagram .
- Page 8 Table of Contents ® CHAPTER 7 7.1 Overview ..........7-1 7.2 Block Diagram .
- Page 9 Table of Contents 9.4 Registers ..........9-7 9.5 Operation .
- Page 10 Table of Contents 10.5.7.5 SDRAM Mode Register Access Cycles ... 10-27 10.5.8 Interrupts ......... 10-27 10.5.9 Software Considerations .
- Page 11 13.5.8.1 Compatibility with Common ISA Devices..13-11 13.5.8.2 Interfacing with a Super I/O Controller... . 13-13 13.5.8.3 Interfacing with an AMD Enhanced Serial Communications Controller (8 MHz) ..13-14 13.5.9 Bus Cycles .
- Page 12 Table of Contents CHAPTER 14 GP BUS DMA CONTROLLER 14-1 14.1 Overview ..........14-1 14.2 Block Diagram .
- Page 13 Table of Contents 15.5.3.2 PC/AT Compatibility ......15-12 15.5.3.3 Floating Point Errors ......15-12 15.5.3.4 Disabling the Slave Controllers .
- Page 14 Table of Contents 17.5.4 Configuration Information ......17-5 17.5.5 Clocking Considerations ....... 17-5 17.5.5.1 Internal Clock .
- Page 15 Table of Contents CHAPTER 21 UART SERIAL PORTS 21-1 21.1 Overview ..........21-1 21.2 Block Diagram .
- Page 16 Table of Contents CHAPTER 23 PROGRAMMABLE INPUT/OUTPUT 23-1 23.1 Overview ..........23-1 23.2 Block Diagram .
- Page 17 Table of Contents CHAPTER 26 AMDebug™ TECHNOLOGY 26-1 26.1 Overview ..........26-1 26.2 Block Diagram .
- Page 18 Table of Contents LIST OF FIGURES Figure 1-1 ÉlanSC520 Microcontroller Block Diagram ....... . . 1-3 Figure 1-2 ÉlanSC520 Microcontroller-Based Smart Residential Gateway Reference Design .
- Page 19 Table of Contents Figure 10-5 SDRAM Clock Generation..........10-7 Figure 10-6 Alternate SDRAM Clock Generation with External Clock Driver .
- Page 20 Table of Contents Figure 19-1 Watchdog Timer Block Diagram ........19-2 Figure 20-1 Real-Time Clock Block Diagram .
- Page 21 Table of Contents LIST OF TABLES Table 0-1 Documentation Notation ..........xxv Table 2-1 Signal Descriptions Table Definitions .
- Page 22 Example Super I/O Controller Interface Timing ......13-13 Table 13-6 Example AMD Enhanced Serial Communications Controller Interface Timing ..13-15 Table 13-7 Differentiating Upper/Lower Byte Access of 16-Bit Devices .
-
Page 23: Preface
PREFACE INTRODUCTION Élan™SC520 MICROCONTROLLER The Élan™SC520 microcontroller is a full-featured microcontroller developed for the general embedded market. The ÉlanSC520 microcontroller combines a 32-bit, low-voltage 86® CPU with a complete set of integrated peripherals suitable for both real-time and PC/AT-compatible embedded applications. PURPOSE OF THIS MANUAL This manual describes the technical features and programming interface of the ÉlanSC520 microcontroller. -
Page 24: Related Documents
RELATED DOCUMENTS The following documents contain additional information that will be useful in designing an embedded application based on the ÉlanSC520 microcontroller. AMD Documentation In addition to this manual, the documentation set for the ÉlanSC520 microcontroller includes the following documents: Élan™SC520 Microcontroller Register Set Manual , order #22005, fully describes all the... -
Page 25: Additional Information
In addition, these documents are available in PDF form on the AMD web site. To access the web site, go to www.amd.com and follow the Embedded Processor link for information about the E86 family. -
Page 26: Index
Introduction Table 0-1 Documentation Notation (Continued) Notation Meaning The bit field is write-only. Reading this register at this bit field does not return a meaningful value and has no side effects. The bit field is read/write. Reading the register at this bit field always returns the last value written. - Page 27 Introduction Table 0-1 Documentation Notation (Continued) Notation Meaning Hexadecimal number Any of several legal values; e.g., using 0xF8h for the UART x in register address Transmit Holding register is either 02F8h or 03F8h, depending on the UART The bit field that consists of bits X through Y. [X–Y] Example: The SB_ADDR[23–16] bit field.
- Page 28 Introduction xxviii Élan™SC520 Microcontroller User’s Manual...
-
Page 29: Chapter 1 Architectural Overview
CHAPTER ARCHITECTURAL OVERVIEW Élan™SC520 MICROCONTROLLER The Élan™SC520 microcontroller is a full-featured microcontroller developed for the general embedded market. The ÉlanSC520 microcontroller combines a 32-bit, low-voltage 86 CPU with a complete set of integrated peripherals suitable for both real-time and PC/AT-compatible embedded applications. An integrated PCI host bridge, SDRAM controller, enhanced PC/AT-compatible peripherals, and advanced debugging features provide the system designer with a wide range of on- chip resources, allowing support for legacy devices as well as new devices available in the... -
Page 30: Block Diagram
Architectural Overview – Parallel debug port for high-speed data exchange during in-circuit emulation General-purpose (GP) bus with programmable timing for 8- and 16-bit devices provides good performance at very low cost. ROM/Flash controller for 8-, 16-, and 32-bit devices Enhanced PC/AT-compatible peripherals provide improved performance. –... -
Page 31: Figure 1-1 Élansc520 Microcontroller Block Diagram
Architectural Overview In addition to these three primary interfaces, the ÉlanSC520 microcontroller also contains internal oscillator circuitry and phase locked loop (PLL) circuitry, requiring only two simple crystals for virtually all system clock generation. Diagrams showing how the ÉlanSC520 microcontroller can be used in various system designs are included in “Applications”... -
Page 32: Architectural Overview
86 CPU in the ÉlanSC520 microcontroller utilizes the industry-standard x86 microprocessor instruction set that enables compatibility across a variety of performance levels from the 16-bit Am186™ processors to the high-end AMD Athlon™ processor. Software written for the x86 architecture family is compatible with the ÉlanSC520 microcontroller. -
Page 33: Industry-Standard Pci Bus Interface
Architectural Overview 1.3.3 Industry-Standard PCI Bus Interface (Chapter 9) The ÉlanSC520 microcontroller provides a 33-MHz, 32-bit PCI bus Revision 2.2-compliant host bridge interface, including integrated write-posting and read-buffering capabilities suitable for high-throughput applications. The PCI host bridge leverages standard peripherals and software. It also provides: High throughput (132 Mbytes/s peak transfer rate) Deep buffering and support for burst transactions from PCI bus masters to SDRAM Flexible arbitration mechanism... -
Page 34: Clock Generation
Architectural Overview I/O address space). The PAR hardware allows designers to flexibly configure both address spaces and place memory and/or external peripherals, as required by the application. The internal memory-mapped configuration registers space can also be remapped to accommodate system requirements. PAR registers also allow control of important attributes, such as cacheability, write protection, and code execution protection for memory resources. -
Page 35: Integrated Peripherals
Architectural Overview 1.3.9 Integrated Peripherals The ÉlanSC520 microcontroller is a highly integrated single-chip CPU with a complete set of integrated peripherals that are a superset of common PC/AT peripherals, plus a set of memory-mapped peripherals that enhance its usability in various applications. A programmable interrupt controller (PIC) (see Chapter 15) that provides the capability to prioritize 22 interrupt levels, up to 15 of these being external sources. -
Page 36: System Testing And Debugging Features
Architectural Overview 1.3.11 System Testing and Debugging Features (Chapter 24) To facilitate debugging, the ÉlanSC520 microcontroller provides observability of many portions of its internal operation, including: A three-pin interface that can be used in either system test mode or write buffer test mode, to aid in determining internal bus initiators of SDRAM cycles, and determining when SDRAM data is valid on the interface. -
Page 37: Digital Set Top Box
Architectural Overview keyboard and mouse commands upstream and transmits video BIOS calls downstream. The thin client renders and displays the graphics for the user. The thin client is typically connected to an Ethernet LAN, although a remote location can connect to a server via a WAN connection such as a modem. A minimum speed of 24 kbaud is required for the communication protocol, unless the application is graphics-intensive, in which case a faster connection is required. -
Page 38: Figure 1-2 Élansc520 Microcontroller-Based Smart Residential Gateway
Architectural Overview Figure 1-2 Élan™SC520 Microcontroller-Based Smart Residential Gateway Reference Design PCI Bus MA12–MA0 GPA25–GPA0 MD31–MD0 GPD15–GPD0 Élan™SC520 Microcontroller Control Control 1-10 Élan™SC520 Microcontroller User’s Manual... -
Page 39: Figure 1-3 Élansc520 Microcontroller-Based Thin Client Reference Design
Architectural Overview Figure 1-3 Élan™SC520 Microcontroller-Based Thin Client Reference Design Control PCI Bus MA12–MA0 GPD15–GPD0 MD31–MD0 GPA25–GPA0 Élan™SC520 Microcontroller Control Control Élan™SC520 Microcontroller User’s Manual 1-11... -
Page 40: Figure 1-4 Élansc520 Microcontroller-Based Digital Set Top Box Reference Design
Architectural Overview Figure 1-4 Élan™SC520 Microcontroller-Based Digital Set Top Box Reference Design PCI Bus MA12–MA0 GPD15–GPD0 MD31–MD0 GPA25–GPA0 Élan™SC520 Microcontroller Control Control 1-12 Élan™SC520 Microcontroller User’s Manual... -
Page 41: Figure 1-5 Élansc520 Microcontroller-Based Telephone Line Concentrator
Architectural Overview Figure 1-5 Élan™SC520 Microcontroller-Based Telephone Line Concentrator Reference Design PCM Highway MD31–MD0 GPD15–GPD0 MA12–MA0 GPA25–GPA0 Élan™SC520 Microcontroller Control Control Élan™SC520 Microcontroller User’s Manual 1-13... - Page 42 Architectural Overview 1-14 Élan™SC520 Microcontroller User’s Manual...
-
Page 43: Chapter 2 Pin Information
CHAPTER PIN INFORMATION OVERVIEW The ÉlanSC520 microcontroller contains 258 signal pins plus power and ground signals. A minimal number of signals are shared with others. The signals are organized alphabetically within the following functional groups: Synchronous DRAM controller (page 2-5) ROM/Flash controller (page 2-6) PCI bus (page 2-6) General-purpose (GP) bus (page 2-7) -
Page 44: Figure 2-1 Logic Diagram By Interface
Pin Information Figure 2-1 Logic Diagram by Interface GPA25–GPA0 BQÃ7ˆ† GPD15–GPD0 Q8DÃ7ˆ† AD31–AD0 GPRESET CBE3–CBE0 GPIORD GPIOWR SERR GPMEMRD GPMEMWR PERR GPALE FRAME TRDY GPBHE IRDY GPRDY STOP GPAEN GPTC DEVSEL CLKPCIOUT GPDRQ3–GPDRQ0 CLKPCIIN GPDACK3–GPDACK0 GPIRQ10–GPIRQ0 INTA–INTD GPDBUFOE REQ4–REQ0 GPIOCS16 GNT4–GNT0 GPMEMCS16 GPCS7–GPCS0... -
Page 45: Figure 2-2 Logic Diagram By Default Pin Function
Pin Information Figure 2-2 Logic Diagram by Default Pin Function BQÃ7ˆ† GPA25 {DEBUG_ENTER} AD31–AD0 Q8DÃ7ˆ† GPA24 {INST_TRCE} CBE3–CBE0 GPA23 {AMDEBUG_DIS} GPA22–GPA15 {RSTLD7–RSTLD0} GPA13–GPA0 SERR GPD15–GPD0 PERR GPRESET FRAME GPIORD TRDY GPIOWR IRDY GPMEMRD STOP GPMEMWR DEVSEL PIO0 [GPALE] CLKPCIOUT PIO1 [GPBHE] CLKPCIIN PIO2 [GPRDY] PIO3 [GPAEN]... -
Page 46: Signal Descriptions
Pin Information SIGNAL DESCRIPTIONS Table 2-1 describes the terms used in the signal description table. In general, the brackets, [ ], indicate alternate, multiplexed functions, and braces, { }, indicate reset configuration pins (pinstraps). The line over a pin name indicates an active Low signal. The word pin refers to the physical wire;... -
Page 47: Table 2-2 Signal Descriptions
Pin Information Table 2-2 Signal Descriptions Multiplexed Signal Signal Type Description Synchronous DRAM Controller BA1–BA0 — Bank Address is the SDRAM bank address bus. CLKMEMIN — SDRAM Clock Input is the SDRAM clock return signal used to minimize skew between the internal SDRAM clock and the CLKMEMOUT signal provided to the SDRAM devices. - Page 48 Pin Information Table 2-2 Signal Descriptions (Continued) Multiplexed Signal Signal Type Description ROM/Flash Controller BOOTCS — ROM/Flash Boot Chip Select is an active Low output that provides the chip select for the startup ROM and/or the ROM/Flash array (BIOS, HAL, O/S, etc.). The BOOTCS signal asserts for accesses made to the 64-Kbyte segment that contains the Am5 86 CPU boot vector: addresses 3FF0000h–3FFFFFFh.
- Page 49 Pin Information Table 2-2 Signal Descriptions (Continued) Multiplexed Signal Signal Type Description CLKPCIOUT — PCI Bus Clock Output is a 33-MHz clock output for the PCI bus devices. This signal is derived from the 33MXTAL2–33MXTAL1 interface. DEVSEL — Device Select is asserted by the target when it has decoded its address as the target of the current transaction.
- Page 50 Pin Information Table 2-2 Signal Descriptions (Continued) Multiplexed Signal Signal Type Description [GPAEN] PIO3 GP Bus Address Enable indicates that the current address on the GPA25–GPA0 address bus is a memory address, and that the current cycle is a DMA cycle. All I/O devices should use this signal in decoding their I/O addresses and should not respond when this signal is asserted.
- Page 51 Pin Information Table 2-2 Signal Descriptions (Continued) Multiplexed Signal Signal Type Description [GPIRQ0] PIO23 GP Bus Interrupt Request can each be mapped to one of the available interrupt channels or NMI. They are asserted when a [GPIRQ1] PIO22 peripheral requires interrupt service. [GPIRQ2] PIO21 Configuration registers allow inversion of these interrupt requests to...
- Page 52 Pin Information Table 2-2 Signal Descriptions (Continued) Multiplexed Signal Signal Type Description SSI_CLK — SSI Clock is driven by the ÉlanSC520 microcontroller SSI port during active SSI transmit or receive transactions. The idle state of the clock and the assertion/sample edge are configurable. SSI_DI —...
- Page 53 Pin Information Table 2-2 Signal Descriptions (Continued) Multiplexed Signal Signal Type Description Chip Selects [GPCS0] PIO27 General-Purpose Chip Select signals are for the GP bus. They can be used for either memory or I/O accesses. These chip selects are [GPCS1] ROMCS1 asserted for Am5 86 CPU accesses to the corresponding regions set...
- Page 54 Pin Information Table 2-2 Signal Descriptions (Continued) Multiplexed Signal Signal Type Description JTAG Boundary Scan Test Interface JTAG_TCK — Test Clock is the input clock for test access port. JTAG_TDI — Test Data Input is the serial input stream for input data. This pin has a weak internal pullup resistor.
- Page 55 High during PWRGOOD assertion, the BOOTCS access is across the SDRAM data bus. Default is Low (by a built-in pulldown resistor). {CFG3} PITOUT2 CFG3 (Internal AMD test mode enable): For normal ÉlanSC520 microcontroller operation, do not pull High during reset. {DEBUG_ENTER} GPA25 Enter AMDebug Mode is an active High configuration signal latched at the assertion of Power Good (PWRGOOD).
- Page 56 Pin Information Table 2-2 Signal Descriptions (Continued) Multiplexed Signal Signal Type Description {RSTLD0} GPA15 Reset Latched Inputs are shared signals that are latched into a register when PWRGOOD is asserted. They are used to input static {RSTLD1} GPA16 information to software (i.e., board revision). These signals have built- {RSTLD2} GPA17 in pulldown resistors.
-
Page 57: Chapter 3 System Initialization
Several source code examples of information described in this chapter are available on the AMD web site. This CodeKit software is tested source code for example applications. To obtain this software, as well as other product information and tools, access the AMD home page at www.amd.com and follow the Embedded Processors link. - Page 58 System Initialization Some use a commercial real-time operating system (RTOS), a custom RTOS, or a simple ‘main loop’ or non-preemptive executive. In general, the executive or RTOS generally interfaces to the hardware using a hardware dependent layer called a board support package (BSP) In general, the system initialization flow for a native embedded system follows this sequence:...
-
Page 59: Bios Initialization Sequence
System Initialization Some embedded systems execute from read-only memory (usually Flash) and only use DRAM for data storage. This style of system architecture is supported by most RTOS products. This is reflected in line 7. Systems that execute out of Flash memory do not need to copy the operating system and/or application to DRAM. -
Page 60: Reset Event
System Initialization In contrast, real-mode code cannot access physical memory above 0010FFEFh (the real- mode addressing limit), and thus cannot access the default location of the MMCR. This problem is easily resolved by programming the Configuration Base Address (CBAR) register (Port FFFCh) to place the MMCR at an address somewhere below the real-mode addressing limit. -
Page 61: Reset Vector And Reset Segment
System Initialization to explicitly perform a soft restart will simply cause a system reset when a soft reset is detected. Note that the watchdog timer can generate an interrupt (maskable or non-maskable) or a system reset, or both. Handling watchdog timer time-outs can be complex. For more information on how the WDT operates, see Chapter 19, “Watchdog Timer”. -
Page 62: Configuring The Sdram Controller
System Initialization Figure 3-1 Initial Near Jump Example F000:FFFF F000:FFF0 Reset Vector F000:C000 Near Jump Reset Handler F000:0000 The reset vector Near Jump is not required to jump to F000:0000. It can jump anywhere into the reset segment. For example, if the reset handler code is only 16 Kbytes in size, it could jump to F000:C000, leaving more room on the boot ROM device for other code. -
Page 63: Identifying The Cpu Core
System Initialization errors will occur when writing data smaller than a 32-bit doubleword. For a more detailed discussion of ECC, see “Error Correction Code (ECC)” on page 10-16. IDENTIFYING THE CPU CORE Information about the integrated Am5 86 CPU core is available by reading the processor DX register after a system reset and by using the CPUID instruction at any time. -
Page 64: Configuring The Pin Multiplexing
System Initialization 2. If needed, program the PIO pin logic to map the GP bus chip select signal and other control signals to a physical pin. 3. Program a PAR register to map the external peripheral into physical address space and to configure a chip select for the device. -
Page 65: Specifying Pages And Regions
System Initialization 3.7.1 Specifying Pages and Regions For memory-mapped address regions, the Region Size/Start Address (SZ_ST_ADR) bit field in the PAR registers specifies the number of 64-Kbyte or 4-Kbyte pages for the region. Regions using a 64-Kbyte page size can have up to 2048 pages, for a maximum size of 128 Mbytes. -
Page 66: Figure 3-2 Programmable Address Region (Par) Register Format
System Initialization Figure 3-2 Programmable Address Region (PAR) Register Format Programmable Address Region Register 31–29 28–26 24–0 Target of the Attribute Page Size Region Size/Start Address PAR Window (ATTR) (PG_SZ) (SZ_ST_ADR) (TARGET) Memory Page Size Target Device 4-Kbyte memory page size on 4-Kbyte Window disabled boundary, ignored for I/O cycles. -
Page 67: Figure 3-3 Programmable Address Region (Par) Register Worksheet
System Initialization Figure 3-3 Programmable Address Region (PAR) Register Worksheet Srtv‚ÃTv“rÃ%#Fi’‡rÃQhtr† T‡h…‡Ã6qq…r††Ã‚Ã%#Fi’‡rÃ7‚ˆqh…’ v “ Uh…tr‡ à T )LHOGV 6‡‡…viˆ‡r Srtv‚ÃTv“rÃ#Fi’‡rÃQhtr† T‡h…‡Ã6qq…r††ÃÂÃ#Fi’‡rÃ7‚ˆqh…’ 9r‰vpr Srtv‚ÃTv“rÃDPÃ7’‡r† DPÃG‚ph‡v‚Ã7h†r %LWV %LQDU\ Srtv‚Æv“rÃ%#Fi’‡rÃQhtr†... -
Page 68: Address Region Attributes
System Initialization 3.7.2 Address Region Attributes The address region attributes (as specified in the ATTR bit field of a PAR register) can be used with ROM or SDRAM regions to control how the regions can be accessed. This section includes some examples of how the attributes can be used with SDRAM and ROM regions. 3.7.2.1 Write-Protect Attribute When this feature is enabled for an address region in SDRAM or ROM, an interrupt is... -
Page 69: Par Register Priority
System Initialization 3.7.3 PAR Register Priority The PAR register mechanism is a very flexible and useful one. It is designed to allow the system programmer to easily program the address decoding and set attributes for addressable regions. One feature of the PAR register system that may not be obvious from the examples included in this chapter is that the PAR registers have a priority mechanism. -
Page 70: Single Device (An A/D Converter) Using One Chip Select
System Initialization 3.7.4.1 Single Device (an A/D Converter) Using One Chip Select In this example, an A/D converter has four 16-bit registers that need to be mapped into I/O space on GPCS5 at I/O address 0500h. As shown in Table 3-2, the value to program into a PAR register in this case is 34070500h. -
Page 71: Pci Bus Devices
System Initialization 3.7.5 PCI Bus Devices Normally, devices on the PCI bus are mapped into memory space that is above the configured amount of DRAM and just under 4 Gbytes (FFFEFFFFh). The ÉlanSC520 microcontroller’s address decode logic forwards all access to these memory locations to the PCI bus. -
Page 72: Network Adapter For Remote Program Loading
System Initialization PAR programming is required to support this configuration. Note that the internal I/O devices will still be correctly accessed when the IO_HOLES_DEST bit is set. However, if any external GP bus device requires I/O addresses, then a PAR register will be required to allow access to this device. -
Page 73: External Rom Devices
System Initialization 3.7.6 External ROM Devices The PAR registers can also be used to define the addressing for ROM devices selected by BOOTCS, ROMCS1, and ROMCS2. ROM devices include true ROMs, EEPROM, Flash devices, and other similar devices. It is important to note that the top 64 Kbytes of the ROM device selected by BOOTCS (the boot device chip select) is always mapped to the physical addresses from FFFF0000–... -
Page 74: Sdram Regions
System Initialization Table 3-10 Example PAR Programming: Second Bank of Flash for XIP Operating System Bit Field Value Meaning Target Device 110b ROMCS2 Attribute Field 000b Write enable, cacheable, code execution allowed Page Size 64-Kbyte granularity Region Size Specifies sixty-four 64-Kbyte pages for a 4-Mbyte region size Start Address Physical address 00800000h 3.7.7... -
Page 75: Configuring The Interrupt Mapping
System Initialization Several actions could be taken, from merely preventing the write from taking place, to killing the offending thread, or even restarting the system. Also, the event could be recorded and/ or reported to a debugging or diagnostic interface or console port. During debugging, a breakpoint could be set at the front of the write-protect interrupt service routine. -
Page 76: Configuring The Programmable I/O Pins
System Initialization 3.8.3 Interrupt Polarity Each of the interrupt controllers can recognize either a Low-to-High edge-triggered or an active High level-sensitive interrupt request. To support external devices that generate active Low interrupt requests (either edge or level), a programmable inversion of each of the external interrupt requests is available. -
Page 77: Disabling Internal Peripherals
System Initialization 3.11 DISABLING INTERNAL PERIPHERALS Most applications will use the ÉlanSC520 microcontroller’s internal UART devices and its internal real-time clock (RTC). However, some applications might need to use external devices mapped to these same I/O locations. To use external devices, the corresponding internal device must be disabled. - Page 78 System Initialization 3-22 Élan™SC520 Microcontroller User’s Manual...
-
Page 79: Chapter 4 System Address Mapping
CHAPTER SYSTEM ADDRESS MAPPING OVERVIEW The ÉlanSC520 microcontroller includes flexible memory and I/O address decoding with features for both real-time operating systems (RTOS) and systems requiring PC/AT functionality for Windows compatibility. Address decoding is distributed between the memory controllers, GP bus controller, and PCI host bridge controller. The ÉlanSC520 microcontroller provides the following memory and I/O address mapping options. -
Page 80: Registers
System Address Mapping Integrated PC/AT compatible peripherals are direct-mapped in normal PC I/O space (i.e., the programmable interrupt controller, programmable interval timer, GP bus DMA controller, RTC, and UARTs). All remaining integrated peripherals are memory-mapped (the watchdog timer, software timer, GP timers, and SSI). As a PCI target, the PCI bus host bridge decodes normal SDRAM address space, allowing external PCI bus master access of the entire SDRAM space. -
Page 81: Operation
System Address Mapping OPERATION There are three types of system bus masters supported on the ÉlanSC520 microcontroller: the Am5 86 CPU, the PCI bus, and the GP bus DMA controller. As shown in Table 4-3, each of the three bus masters can access specific types of address space. -
Page 82: Programming External Memory, Buses, And Chip Selects
System Address Mapping – GP bus I/O space (accessible only by the CPU) – PCI bus I/O space (accessible by the CPU and PCI masters) – PCI bus configuration space (accessible only by the CPU) Table 4-4 summarizes the organization of memory and I/O address regions in the ÉlanSC520 microcontroller. -
Page 83: Programmable Address Region (Par) Registers
System Address Mapping “Programmable Input/Output”, which describes enabling the actual programmable I/O (PIO) pins that can be shared with other functions. 4.3.2 Programmable Address Region (PAR) Registers Programmable Address Region (PAR) registers provide a common programming interface to configure memory space and I/O space regions in an ÉlanSC520 microcontroller system. As referenced in Table 4-4, the PAR registers are primarily used to define the address regions of ROM and GP bus, as well as to set attributes for ROM and SDRAM regions. -
Page 84: Figure 4-1 Programmable Address Region (Par) Register Format
System Address Mapping Figure 4-1 Programmable Address Region (PAR) Register Format Programmable Address Region Register 31–29 28–26 24–0 Target of the Attribute Page Size Region Size/Start Address PAR Window (ATTR) (PG_SZ) (SZ_ST_ADR) (TARGET) Memory Page Size Target Device 4-Kbyte memory page size on 4-Kbyte Window disabled boundary, ignored for I/O cycles. -
Page 85: Memory Space
System Address Mapping 4.3.3 Memory Space Memory space in the ÉlanSC520 microcontroller includes SDRAM, ROM, PCI bus, GP bus, and the MMCR registers. A system memory map is shown in Figure 4-2. The CPU has access to the entire memory space. PCI bus masters and the GP bus DMA controller have access to SDRAM space only. -
Page 86: Sdram Space
System Address Mapping 4.3.3.1 SDRAM Space SDRAM space in an ÉlanSC520 microcontroller system defaults to a linear region starting at the lowest 32-bit memory address (00000000h) and ending at the top of SDRAM, which is defined by the amount of SDRAM populated in the system and programmed in the SDRAM controller’s configuration registers. -
Page 87: Gp Bus Memory Space
System Address Mapping 4.3.3.3 GP Bus Memory Space GP bus memory space is enabled only through PAR registers and is accessible only by the CPU. There are eight chip selects that can be selected by the PAR registers. Note that the PAR registers do not allow any attributes to be defined in GP bus memory space regions, and GP bus memory space is always noncacheable. -
Page 88: I/O Space
System Address Mapping MMCR register space has a higher priority than the Programmable Address Region (PAR) registers. See Section 4.3.4.1 for details on programming the CBAR register. Reading unimplemented registers in this 4-Kbyte region returns indeterminate data values. Writing to unimplemented registers in this region has no effect. 4.3.3.5.1 Integrated Memory-Mapped Peripherals The ÉlanSC520 microcontroller’s non-PC/AT integrated peripherals are located within the... -
Page 89: Pci Configuration Space
System Address Mapping Figure 4-3 System I/O Map FFFFh 64 Kbytes CBAR FFFCh Default PCI Bus Space Can also be retargeted to GP bus 0CFFh PCI Configuration Registers 0CF8h Default PCI Bus Space Can also be retargeted to GP bus 1 Kbyte 03FFh PC/AT Peripherals... -
Page 90: Pci I/O Space
System Address Mapping This PCI configuration space is accessible only by the CPU in the ÉlanSC520 microcontroller, and the I/O cycle is claimed by the PCI bus configuration register block. As a target, the ÉlanSC520 microcontroller does not accept any PCI bus configuration space accesses from other PCI bus masters. -
Page 91: Table 4-5 Pc/At Peripherals I/O Map
System Address Mapping If necessary, PARx registers can be used to override sending accesses to the PCI bus on an individual peripheral basis. In this way, accesses for individual peripherals can be directed back to the external GP bus. For example, some PCI cards (notably VGA cards) use legacy I/O locations. The IO_HOLE_DEST bit allows the holes to be directed to either the PCI or to the GP bus. -
Page 92: Gp Bus I/O Region
System Address Mapping Table 4-5 PC/AT Peripherals I/O Map (Continued) Peripheral Core I/O Address Range Master GP Bus DMA Controller 00C0–00DEh (even addresses only) Floating Point Error Interrupt Clear 00F0h UART 2 02F8–02FFh UART 1 03F8–03FFh The ÉlanSC520 microcontroller also allows the internal UARTs and the real-time clock (RTC) to be disabled, for applications when an external device is preferred. -
Page 93: Configuring Gp Bus Peripheral Space
System Address Mapping 4.3.5.2.1 Noncacheable, Write-Protected, or Nonexecutable SDRAM Regions In the default condition, the entire SDRAM region is cacheable and executable by the CPU, and read/writable by the CPU, PCI bus master, and GP bus DMA controller cycles. There may be some system configurations in which specific portions of SDRAM require restricted access which can be accomplished by enabling specific attributes. -
Page 94: Configuring The Élansc520 Microcontroller For Windows® Compatibility
System Address Mapping the CPU performs I/O accesses to the UART address regions, the cycles will be forwarded out to the external GP bus. Also, the Super I/O is a positive decoding device, i.e., it does not require a chip select because it performs the address decoding from the GP bus addresses. -
Page 95: Configuring Pci Bus Devices
System Address Mapping The Configuration Base Address (CBAR) register (Port FFFCh) can be used to alias the internal memory-mapped registers and peripherals to a convenient location. For example, they could be mapped between 640 Kbytes and 1 Mbyte for real mode operation. The memory-mapped configuration region is always available in the upper CPU space (4 Gbytes), but the aliased location is only accessible when the CBAR is programmed and the ENABLE bit has been set. - Page 96 System Address Mapping PAR registers should not be programmed to conflict with any of the fixed I/O regions, such as the Configuration Base Address (CBAR) register or the PCI bus configuration space.The ÉlanSC520 microcontroller’s address decoding does not permit PAR registers to overlay the integrated PC/AT peripherals.
- Page 97 System Address Mapping potential problem is modifying a PAR register to redirect normal SDRAM region accesses to the PCI bus, while a PCI bus master has already been granted the PCI bus. In this case, when the CPU completes the write to the PAR register, the posted PCI bus master access is forwarded to the SDRAM controller because the bus was already granted to the PCI bus master.
-
Page 98: Initialization
System Address Mapping – All memory-mapped integrated peripherals and configuration registers for PC/AT peripherals must be accessed as specified in the Élan™SC520 Microcontroller Register Set Manual , order #22005. – PCI configuration registers should be accessed as 32 bits unless otherwise specified in the Élan™SC520 Microcontroller Register Set Manual , order #22005. -
Page 99: Chapter 5 Clock Generation And Control
CHAPTER CLOCK GENERATION AND CONTROL OVERVIEW The ÉlanSC520 microcontroller is designed to generate all of the internal and system clocks it requires. The ÉlanSC520 microcontroller includes on-chip oscillators and PLLs, as well as most of the required PLL loop filter components. The ÉlanSC520 microcontroller requires two standard crystals, one for 32.768 kHz and one for 33 MHz. -
Page 100: Block Diagram
Clock Generation and Control BLOCK DIAGRAM Figure 5-1 shows a block diagram of the ÉlanSC520 microcontroller’s internal clocks. Table 5-1 shows PLL lock times and oscillator start-up times. See the Élan™SC520 Microcontroller Data Sheet , order #22003, for timing diagrams and additional clocking specifications. -
Page 101: System Design
Clock Generation and Control SYSTEM DESIGN Figure 5-2 shows a system block diagram of the ÉlanSC520 microcontroller’s external clocks. As shown in Figure 5-2, external clock drivers may be necessary when the system presents a large capacitive load. Table 5-2 lists the shared clock signals of the ÉlanSC520 microcontroller. Figure 5-2 System Clock Distribution Block Diagram VCC_ANLG... -
Page 102: Clock Pin Loading
Clock Generation and Control 5.3.1 Clock Pin Loading Clock pins are designed to either source or sink 24 mA. The maximum amount of capacitive load that can be placed on a clock pin is determined by the required rise/fall times. Use the following equation to determine the maximum capacitive loading. -
Page 103: Figure 5-3 Bypassing The 32.768-Khz Oscillator
Clock Generation and Control Table 5-3 Timing Error as It Translates to Clock Accuracy Timing Error (Parts per Million) Seconds/Month ± 10 ± 25.9 ± 20 ± 51.8 ± 30 ± 77.8 ± 40 ± 103.7 ± 50 ± 129.6 Detailed crystal specifications and further information on crystal selection can be found in the Élan™SC520 Microcontroller Data Sheet , order #22003. -
Page 104: Registers
Clock Generation and Control Figure 5-4 Bypassing the 33-MHz Oscillator External 2.5-V max 33-MHz 33MXTAL2 Oscillator No Connect 33MXTAL1 Élan™SC520 Microcontroller REGISTERS A summary listing of the memory-mapped configuration registers used to control the clocks on the ÉlanSC520 microcontroller is shown in Table 5-4. Table 5-4 Clock Control Registers—Memory-Mapped MMCR... -
Page 105: Operation
Clock Generation and Control OPERATION The clocks on the ÉlanSC520 microcontroller are generated from two local oscillators. The 32.768-kHz oscillator is used to drive PLL1 (1.47456-MHz PLL), which in turn drives PLL2 (36.864-MHz PLL). The 36.864-MHz clock is divided by 2 to produce the 18.432- MHz UART clock. -
Page 106: Gp-Dma Controller
Clock Generation and Control 5.5.1.6 GP-DMA Controller The GP-DMA controller can be programmed to operate at 4 MHz, 8 MHz, or 16 MHz. This option is specified in the GP-DMA Control (GPDMACTL) register (MMCR offset D80h). Note that these frequencies are derived from the 33-MHz clock. The exact frequency is an even fraction of the crystal (33.000-MHz or 33.333-MHz) being used in the system. -
Page 107: Initialization
Clock Generation and Control 5.5.2 Using the CLKTIMER[CLKTEST] Pin The CLKTIMER[CLKTEST] pin can be programmed as an input (CLKTIMER) or as an output (CLKTEST) in the Clock Select (CLKSEL) register (MMCR offset C26h). When programmed as an input (default), this pin can be used to provide the clock for the programmable interval timer (PIT) core. - Page 108 Clock Generation and Control 5-10 Élan™SC520 Microcontroller User’s Manual...
-
Page 109: Chapter 6 Reset Generation
CHAPTER RESET GENERATION OVERVIEW Reset features of the ÉlanSC520 microcontroller include: ÉlanSC520 microcontroller system reset generation via PWRGOOD pin, software writes, watchdog timer, and AMDebug system reset ÉlanSC520 microcontroller system reset with SDRAM interface contents maintained (called programmable reset ) Hard CPU reset generation via system reset Soft CPU reset generation via software writes and detection of the CPU special cycle type “shutdown”... -
Page 110: Figure 6-1 Reset Controller Block Diagram
Reset Generation Figure 6-1 Reset Controller Block Diagram Élan™SC520 Microcontroller Reset Controller GPRESET PWRGOOD Reset Configuration DEBUG_ENTER PRGRESET Register INST_TRCE AMDEBUG_DIS port92_rst Port A Pinstrap a20_ctl CFG3–CFG0 Status a20_gate RSTLD7–RSTLD0 GP Bus Reset port64_rst Registers System Source Information Detect Controller config AMDebug Controller... -
Page 111: Registers
Reset Generation REGISTERS The reset generation on the ÉlanSC520 microcontroller is controlled by the memory- mapped registers listed in Table 6-1 and the direct-mapped registers listed in Table 6-2. Table 6-1 Reset Generation Registers—Memory-Mapped MMCR Offset Register Mnemonic Address Function Host Bridge Control HBCTL PCI reset (RST) -
Page 112: Cpu
Reset Generation Table 6-3 Élan™SC520 Microcontroller Reset Sources GPRESET RST Pin Internal Source (Hard/Soft) (PCI) Registers Notes PWRGOOD pin Hard PRGRESET pin Hard SYS_RST bit, RESCFG register Hard Watchdog timer reset event Hard AMDebug system reset Hard CPU_RST bit, SYSCTLA register (Port 0092h) Soft SCP soft reset, SCPCMD register (Port 0064h) Soft... -
Page 113: Gp Bus
Reset Generation ® CPU reset, see the Am486 DX/DX2 Microprocessor Hardware Reference Manual , 1994 (order #17965). Note: The CFG3–CFG0 and RSTLD7–RSTLD0 pins are latched only as a result of the assertion of the PWRGOOD signal, and not as a result of the SYS_RST bit, AMDebug system reset event, or watchdog timer event. -
Page 114: System Reset With Sdram Retention
Reset Generation System reset is a subset of the power-on reset sequence described in “Initialization” on page 6-9.The only real difference between the two is that, for power-on reset, power is being applied to the part in addition to the reset, and the stabilization of power supplies to deassertion of the reset is specified. -
Page 115: Pci Reset
Reset Generation 6.5.3 Soft CPU Reset A soft CPU reset is differentiated from a hard CPU reset in that soft CPU reset does not affect the CPU’s cache state. See “Initialization” on page 7-5 for more information about the differences between hard and soft CPU reset. A soft CPU reset does not reset the ÉlanSC520 microcontroller’s internal register bits, with the exception of the NMI_ENB bit in the Interrupt Control (PICICR) register (MMCR offset D00h). -
Page 116: Determining Reset Sources
Reset Generation 6.5.7 Determining Reset Sources Status bits are available in the Reset Status (RESSTA) register (MMCR offset D74h) for software to determine the source of reset. These bits are set when the associated event is detected and cleared by writing a 1. They include: ICE_HRST_DET—Hard CPU reset from AMDebug logic ICE_SRST_DET—AMDebug system reset WDT_RST_DET—Watchdog timer time-out system reset... -
Page 117: Latency
Reset Generation 6.5.11 Latency PRGRESET events must be arbitrated in the SDRAM controller to ensure that the SDRAM devices are in a state in which data is not lost when the PRGRESET event is propagated. This arbitration causes the PRGRESET event to be delayed by no more than 32 CPU clock periods prior to assertion of the internal and external reset signals. - Page 118 Reset Generation 6-10 Élan™SC520 Microcontroller User’s Manual...
-
Page 119: Chapter 7 Am5
CHAPTER ® OVERVIEW The ÉlanSC520 microcontroller has an integrated Am5 86 CPU core. The features of the 86 CPU include: Operation at 100 MHz or 133 MHz, with a 33-MHz bus interface 16-Kbyte unified cache configurable for either write-back or write-through cache mode Integrated floating point unit (ANSI/IEEE 754 compliant) On-chip debug support. -
Page 120: Figure 7-1 Am5 X 86 Cpu Block Diagram
® Figure 7-1 86® CPU Block Diagram 86® CPU Bus Élan™SC520 Microcontroller User’s Manual... -
Page 121: Operation
A full description of the operation of the Am5 86 CPU is well beyond the scope of this chapter. The following AMD publications are a good starting point for learning about the 86 CPU as it has evolved over time. The oldest publication is listed first. The later publications enhance the original functional descriptions. -
Page 122: Cache Memory Management
® 7.4.2 Cache Memory Management The ÉlanSC520 microcontroller contains a 16-Kbyte unified code and data cache. Cache operation defaults to write-back cache mode. However, this mode can be disabled by setting the Cache Write Mode (CACHE_WR_MODE) bit in the Am5 86 CPU Control register (MMCR offset 02h). -
Page 123: Interrupts
® coherency issues, PCI bus master cycles, or GP-DMA controller operations during this period. Interrupts generated to the Am5 86 CPU will be honored only after the Am5 CPU is operating again. Once the CPU PLLs have stabilized and the new core frequency has been established, caching is once again enabled in the same mode as it was prior to the clock speed change. - Page 124 ® bits in the Am5 86 CPU’s machine status (CR0) register, and the Am5 86 CPU’s write buffers retain the values they had prior to the soft reset. A soft reset event clears the NMI_ENB bit in the Interrupt Control (PICICR) register, disabling NMIs.
-
Page 125: Chapter 8 System Arbitration
CHAPTER SYSTEM ARBITRATION OVERVIEW The ÉlanSC520 microcontroller includes two arbiters. A CPU bus arbiter arbitrates between the Am5 86 CPU, the PCI host bridge, and the GP-DMA controller on the internal CPU bus. A PCI bus arbiter arbitrates between the Am5 86 CPU and up to five external PCI masters on the external PCI bus. -
Page 126: Registers
System Arbitration Figure 8-1 System Arbitration Block Diagram Élan™SC520 Microcontroller GP Bus System Arbiter CPU Bus Arbiter SDRAM Controller GP-DMA PCI Bus Arbiter PCI Host Bridge PCI Bus REGISTERS The arbitration subsystem is controlled by the memory-mapped registers listed in Table 8-1. Table 8-1 System Arbitration Registers—Memory-Mapped MMCR... -
Page 127: Operation
System Arbitration Table 8-1 System Arbitration Registers—Memory-Mapped (Continued) MMCR Offset Register Mnemonic Address Function PCI Host Bridge Interrupt PCIHOSTMAP D14h System arbiter and PCI host bridge interrupt Mapping mapping to any of 22 available interrupt channels or NMI, PCI NMI enable control OPERATION The ÉlanSC520 microcontroller’s arbitration subsystem consists of two separate bus arbitration units for the CPU bus and the PCI bus. -
Page 128: Concurrent Arbitration Mode
System Arbitration 3. The PCI bus arbiter sees that the host bridge has been granted the CPU bus and grants the PCI bus to the external PCI master requesting the PCI bus. Note that now the external PCI master owns both the PCI bus and the CPU bus. In nonconcurrent arbitration mode, the PCI bus and CPU bus essentially become one bus where only one master is allowed on the bus at any time. -
Page 129: Cpu Bus Arbiter
System Arbitration 8.4.2 CPU Bus Arbiter The CPU bus arbiter controls access to the internal CPU bus. This internal bus allows for: 86 CPU access of SDRAM, GP bus, PCI, or ROM GP-DMA access of SDRAM PCI host bridge access of SDRAM for external PCI master cycles No concurrent operation is allowed on the CPU bus (e.g., Am5 86 CPU accessing the GP bus while the PCI host bridge is accessing SDRAM). -
Page 130: Cpu Cache Snooping
System Arbitration Figure 8-3 CPU Bus Rotating Priority Queue Host Bridge Target GP Bus 8.4.2.2 CPU Cache Snooping The Am5 86 CPU includes a write-back cache that updates only the internal cache on memory writes from the CPU (if configured for write-back mode). When only the internal cache memory is updated for a memory write, the external SDRAM contains invalid data. -
Page 131: Gp Bus Dma Arbitration
System Arbitration 8.4.2.4 GP Bus DMA Arbitration The GP-DMA controller allows internal and external GP bus peripherals to have DMA access to SDRAM. There is no preemption mechanism for GP-DMA. Therefore, once a DMA transaction begins, no other master is granted the CPU bus until the DMA controller deasserts its bus request, which varies according to whether the channel is programmed for a single cycle transfer or a block mode transfer. -
Page 132: Pci Bus Arbitration Protocol
System Arbitration 8.4.3.1 PCI Bus Arbitration Protocol The PCI Local Bus Specification, Revision 2.2, states that the central arbiter must implement a fairness algorithm, which means that each potential bus master must be granted access to the bus independently of other requests. The PCI bus arbiter satisfies this requirement by implementing a rotating priority arbitration scheme that guarantees each bus master a place in the arbitration rotation (see Figure 8-3 on page 8-6 for information on rotating priority arbitration). -
Page 133: Figure 8-4 External Pci Master Arbitration Queues
System Arbitration Figure 8-4 External PCI Master Arbitration Queues High-Priority Queue Low-Priority Queue Notes: HP0, HP1: High-priority masters LP0, LP1, LP2, LP3, ..., LPn: Low-priority masters LPx: Current low-priority master selected Priority: HP0, HP1, LP0, HP0, HP1, LP1, HP0, HP1, LP2, HP0, HP1, LP3, ..., HP0, HP1, LPn Figure 8-5 Host Bridge Master Arbitration Queue Notes:... -
Page 134: Bus Parking
System Arbitration 8.4.3.2 Bus Parking The PCI bus arbiter parks the bus on a PCI bus master when the bus is idle (no master is requesting the bus). This is required on the PCI bus to guarantee that the bus is properly terminated at all times. -
Page 135: Bus Cycles
System Arbitration 8.4.4 Bus Cycles This section includes example timing diagrams showing various types of arbitration that may occur in the ÉlanSC520 microcontroller. Note that these are example cases only, and not all cases are shown. The diagrams are functionally representative in nature, and should not be used to infer detailed timing information. -
Page 136: Cpu Bus Cache Write-Back
System Arbitration cpu_hold to the Am5 86 CPU would remain asserted. In this example, another CPU bus master also requests the bus by asserting mst_req. Clock #3: The Am5 86 CPU samples cpu_hold deasserted and deasserts cpu_hlda to take ownership of the bus. The Am5 86 CPU begins a cycle by asserting cpu_ads. -
Page 137: Figure 8-7 Cpu Bus Cache Write-Back
System Arbitration Figure 8-7 CPU Bus Cache Write-Back cpu_hold cpu_hlda eads hitm cpu_ads cpu_rdy mst_req mst_gnt mst_ads mst_rdy Notes: In Figure 8-7, the CPU bus master signals are labeled mst_xxxx and the Am5 86 CPU signals are labeled cpu_xxxx. The additional internal CPU bus interface signals shown in Figure 8-7 for write-back cycles are •... -
Page 138: Cpu-To-Pci Cycle
System Arbitration Clock #11: The Am5 86 CPU samples cpu_rdy, which ends the write-back cycle. The 86 CPU has also sampled cpu_hold asserted and surrenders the bus by asserting cpu_hlda. Note: This write-back cycle is for illustration purposes only; the actual write-back cycle would consist of multiple data phases. -
Page 139: Pci Bus Arbitration
System Arbitration Clock #4: The cpu_hlda signal is deasserted by the Am5 86 CPU to take ownership of the CPU bus, and cpu_ads is asserted to begin a cycle to PCI. Clock #5: The CPU bus arbiter samples cpu_ads asserted and rearbitrates. In this example, a higher priority master is requesting the bus, so cpu_hold is asserted to the 86 CPU. -
Page 140: Pci Bus Arbitration Parking
System Arbitration Clock #3: The PCI bus arbiter samples REQ asserted and begins arbitration. Master 0 has higher priority at this time than master 1 so the PCI bus arbiter grants the PCI bus to master 0. Clock #4: Master 0 samples the bus idle and its GNT0 signal asserted and begins a transaction by asserting FRAME. - Page 141 System Arbitration The following sequence annotates the PCI bus concurrent mode arbitration parking cycle shown in Figure 8-10. Clock #2: Master 0 requests access to the bus. Clock #3: The PCI bus arbiter samples REQ asserted and begins arbitration. Master 0 is the only master requesting the bus, so the PCI bus arbiter grants the bus to master 0 by asserting GNT0.
-
Page 142: Nonconcurrent Mode Arbitration
System Arbitration 8.4.4.6 Nonconcurrent Mode Arbitration Figure 8-11 shows external PCI master arbitration in nonconcurrent mode. In nonconcurrent arbitration mode, both the CPU bus and the PCI bus are granted to the PCI master, regardless of the destination of the PCI transaction. Figure 8-11 Nonconcurrent Mode Arbitration CLKPCIIN... -
Page 143: Interrupts
System Arbitration maintain ownership of the CPU bus until it deasserts hb_req. The external PCI master samples GNT0 asserted and asserts FRAME to begin the PCI transaction. Clock #8: GNT0 is deasserted because either the external master is parked on the CPU or another master has requested the bus. -
Page 144: Latency
System Arbitration 8.4.7 Latency Because the PCI bus is shared by many masters, each master incurs a latency accessing the bus due to other masters. This latency is determined by each master in the system and the arbitration algorithm. The latency contributed by each master is controlled through its associated master latency timer, which limits the amount of time a master is allowed for each transaction. -
Page 145: High-Priority Queue Latency
System Arbitration 8.4.7.2 High-Priority Queue Latency The maximum latency for a master in the high-priority queue is the sum of: Master latency timer of other master in high-priority queue—This time can be decreased by decreasing the master latency timer of the other master in the high-priority queue, or this time can be eliminated by programming only one master in the high-priority queue. -
Page 146: Concurrent Arbitration Mode Latency
System Arbitration transactions, not only transactions where the ÉlanSC520 microcontroller is the PCI target. Note that this includes PCI bus transactions where both the master and the target are external PCI bus agents. 8.4.7.6 Concurrent Arbitration Mode Latency The CPU bus adds to the PCI bus latency even when operating in concurrent arbitration mode. - Page 147 System Arbitration 4. Enable external PCI requests to the PCI bus arbiter in the System Arbiter Master Enable (SYSARBMENB) register (MMCR offset 72h). By default, all external PCI bus master requests are disabled. 5. Enable/Clear the PCI bus GNT time-out interrupt with the GNT_TO_INT_ENB bit in the System Arbiter Control (SYSARBCTL) register, if desired.
- Page 148 System Arbitration 8-24 Élan™SC520 Microcontroller User’s Manual...
-
Page 149: Chapter 9 Pci Bus Host Bridge
CHAPTER PCI BUS HOST BRIDGE OVERVIEW The ÉlanSC520 microcontroller includes an integrated PCI bus host bridge, which allows the microcontroller to interface with any PCI bus Revision 2.2-compliant master or target device. The PCI host bridge includes the following features: 33 MHz, 32-bit PCI bus Revision 2.2-compliant Peak transfer rate of 132 Mbytes/s Support for delayed transactions improves PCI bus utilization... -
Page 150: System Design
PCI Bus Host Bridge Figure 9-1 PCI Interface Block Diagram Élan™SC520 Microcontroller SDRAM CPU Bus Controller PCI Host Bridge Controller Read Write FIFO FIFO Write FIFO PCI Master Controller PCI Target Controller Interrupt Steering Arbiter PCI Bus SYSTEM DESIGN Figure 9-2 shows how the ÉlanSC520 microcontroller can be connected to an external PCI bus target device. -
Page 151: Figure 9-2 Élansc520 Microcontroller Connection To An External Pci Bus Target
PCI Bus Host Bridge GPIRQ0 pins on the GP bus. See Chapter 15, “Programmable Interrupt Controller”, for further information on connecting interrupt requests to the ÉlanSC520 microcontroller. Figure 9-4 on page 9-5 shows how the PERR and SERR signals are connected to the ÉlanSC520 microcontroller. -
Page 152: Figure 9-3 Élansc520 Microcontroller Connection To An External Pci Bus Master
PCI Bus Host Bridge Figure 9-3 Élan™SC520 Microcontroller Connection to an External PCI Bus Master eODQŒ6& 0LFURFRQWUROOHU AD31–AD0 PCI Master AD31–AD0 Device CBE3–CBE0 CBE3–CBE0 PCI Bus Host Bridge (PCI bus target) FRAME FRAME IRDY IRDY TRDY TRDY STOP STOP DEVSEL DEVSEL PERR PERR... -
Page 153: Pci Clocking
PCI Bus Host Bridge Figure 9-4 Élan™SC520 Microcontroller SERR and PERR Connection PERR PERR PCI Device 0 SERR SERR eODQŒ6& 0LFURFRQWUROOHU PERR PCI Device 1 SERR PERR PCI Device 2 SERR PERR PCI Device 3 SERR PERR PCI Device 4 SERR 9.3.1 PCI Clocking... -
Page 154: Figure 9-5 Pci Bus Clocking Example 1: Lightly Loaded System
PCI Bus Host Bridge Figure 9-5 PCI Bus Clocking Example 1: Lightly Loaded System Élan™SC520 Microcontroller PCI Device 0 CLKPCIOUT CLKPCIIN Notes: In this lightly loaded system, no clock buffering is required. Figure 9-6 PCI Bus Clocking Example 2: Heavily Loaded System Élan™SC520 Microcontroller PCI Device 0 CLKPCIOUT... -
Page 155: Registers
PCI Bus Host Bridge It is up to the system designer to choose the accuracy of the crystal used with the ÉlanSC520 microcontroller. The 33.000-MHz frequency provides a better guard band than the 33.333- MHz crystal. In practice, most PCI devices tolerate both frequencies, but it is important to be aware of the impact of choosing the crystal on this potential violation of the PCI bus specifications. -
Page 156: Operation
PCI Bus Host Bridge Table 9-2 PCI Host Bridge Registers—Direct-Mapped Register Mnemonic I/O Address Function PCI Configuration Address PCICFGADR 0CF8h PCI configuration space enable, bus number, device number, function number, register number PCI Configuration Data PCICFGDATA 0CFCh PCI configuration data Table 9-3 PCI Host Bridge Registers—PCI Indexed Register... -
Page 157: Unsupported Pci Bus Configuration Registers
PCI Bus Host Bridge The LOCK pin is an optional pin not required in most systems, because other mechanisms are typically employed for coherency. Address/data stepping is not supported as a master due to the performance implications. The ÉlanSC520 microcontroller does not support a downstream “Southbridge” device, because most peripherals normally included in a Southbridge are integrated into the ÉlanSC520 microcontroller. -
Page 158: Generating Pci Bus Configuration Cycles
PCI Bus Host Bridge The host bridge PCI bus configuration space contains only PCI bus device configuration header registers, as defined in the PCI bus specification. ÉlanSC520 microcontroller- specific host bridge configuration registers are memory-mapped in ÉlanSC520 microcontroller configuration space. See Chapter 4, “System Address Mapping”, for further details on memory-mapped configuration space. -
Page 159: Élansc520 Microcontroller's Host Bridge As Pci Bus Master
PCI Bus Host Bridge The Master Enable (BUS_MAS) bit in the Status/Command (PCISTACMD) register (PCI index 04h) is always forced active. Thus, the PCI host bridge can always generate memory, I/O, and configuration transactions on the PCI bus to configure external PCI devices. To enable the host bridge as a PCI bus target device, the Memory Access Enable (MEM_ENB) bit in the Status/Command (PCISTACMD) register must be set. -
Page 160: Read Cycles
PCI Bus Host Bridge bridge waits until the write cycle has completed on the PCI bus before returning ready to the Am5 86 CPU. Write posting should not be enabled while operating in nonconcurrent arbitration mode. See Chapter 8, “System Arbitration”, for further details on nonconcurrent mode arbitration. 9.5.3.2 Read Cycles The PCI host bridge does not read ahead PCI bus memory for Am5... -
Page 161: Figure 9-8 Cpu Read Cycle To The Pci Bus
PCI Bus Host Bridge Figure 9-8 CPU Read Cycle to the PCI Bus cycle_info blast CPU Data qh‡hÃv pcihit hqq…r†† qh‡hÃv CBEx …rhqÃp€q i’‡rÃrhiyr† FRAME IRDY TRDY DEVSEL Notes: The diagram includes the following internal signals: • pcihit: Address decode signal that the current Am5 86 CPU cycle is a PCI cycle. -
Page 162: Figure 9-9 Cpu Read Cycle To The Pci Bus With External Target Retry
PCI Bus Host Bridge Clock #10: The PCI host bridge samples TRDY asserted and latches the data from the PCI bus. Clock #13: The Am5 86 CPU bus synchronizes the end of the PCI bus cycle and asserts rdy to the Am5 86 CPU with the requested read data. -
Page 163: Figure 9-10 Cpu Posted Write Cycle To The Pci Bus
PCI Bus Host Bridge delay (the arbiter is parked on the host bridge). If another external PCI bus master was granted the bus or the bus was not idle, FRAME assertion would be delayed until the host bridge’s gnt was asserted and the bus was idle. Clock #14: The PCI bus target asserts TRDY indicating the data is available. - Page 164 PCI Bus Host Bridge Clock #6: The PCI host bridge master controller has synchronized the Am5 86 CPU bus request and asserts req to gain access to the PCI bus. Clock #7: The PCI host bridge gnt signal is sampled asserted, and the PCI bus is idle, so FRAME is asserted to begin the PCI transaction.
-
Page 165: Figure 9-12 Cpu Write Cycles To Internal Pci Bus Configuration Registers
PCI Bus Host Bridge The following sequence annotates the Am5 86 CPU non-posted write cycle to the PCI bus shown in Figure 9-11. Clock #1: The Am5 86 CPU starts a write cycle to the PCI bus. Clock #6: The PCI host bridge master controller has synchronized the Am5 86 CPU bus request and asserts req to gain access to the PCI bus. -
Page 166: Élansc520 Microcontroller's Host Bridge As Pci Bus Target
PCI Bus Host Bridge to the PCI Configuration Data (PCICFGDATA) register that access external PCI bus device configuration registers. Figure 9-13 CPU Read Cycles from Internal PCI Bus Configuration Registers clk_cpu cycle_info Data read data 9.5.4 Élan™SC520 Microcontroller’s Host Bridge as PCI Bus Target As a target, the integrated PCI host bridge only accepts memory cycles from external PCI bus masters to allow accesses to the ÉlanSC520 microcontroller’s SDRAM. -
Page 167: Pci Bus Command Support
PCI Bus Host Bridge 9.5.4.2 PCI Bus Command Support As a PCI bus target, the ÉlanSC520 microcontroller’s PCI host bridge treats the memory- write-and-invalidate command the same as a memory-write cycle. When either of these commands is issued by a PCI bus master, the PCI host bridge and system arbitration blocks force the Am5 86 CPU’s integrated cache to snoop the addresses prior to writing the data to SDRAM. -
Page 168: Address Fifo
PCI Bus Host Bridge The PCI host bridge retries any external PCI bus master write cycle when the write FIFO is full. The PCI host bridge retries all external PCI bus master cycles (write and read) if the address FIFO is full (see the Section 9.5.4.5).The PCI host bridge always disconnects after 64 consecutive doublewords are transferred to prevent any one PCI bus master from monopolizing the bus and to guarantee sufficient CPU bus bandwidth. -
Page 169: Burst Ordering
PCI Bus Host Bridge For memory-read and memory-read-line commands, the PCI host bridge prefetches data up to the next cache line (a cache line is four doublewords). Memory-read-multiple commands fill the target FIFO (64 doublewords). Once the PCI host bridge has been granted access to the CPU bus, it will hold the bus until it has prefetched up to the next cache-line boundary for memory-read and memory-read- line commands, and 64 doublewords for memory-read-multiple commands. -
Page 170: Pci Host Bridge Target Bus Cycles
PCI Bus Host Bridge register (MMCR offset 60h). The T_PURGE_RD_ENB bit must not be changed except during PCI bus initialization after a system or programmable reset. Memory-read and memory-read-line commands generate a purge when the write address is within the same cache line as the prefetched data. Note that the addresses do not necessarily overlap in this case. -
Page 171: Figure 9-14 External Pci Bus Master Posted Write To Sdram
PCI Bus Host Bridge Figure 9-14 External PCI Bus Master Posted Write to SDRAM CLKPCIIN address data1 data2 data3 data4 data5 data6 data7 CBEx write cmd FRAME IRDY TRDY DEVSEL Ã hb_req hb_gnt Notes: The diagram includes the following internal signals: •... -
Page 172: Figure 9-15 External Pci Master Sdram Read (Delayed Transaction)
PCI Bus Host Bridge 9.5.4.9.2 External PCI Master SDRAM Read (Delayed Transaction) Figure 9-15 shows an external PCI bus master read transaction to the ÉlanSC520 microcontroller’s SDRAM. Figure 9-15 External PCI Master SDRAM Read (Delayed Transaction) CLKPCIIN DGGUHV DGGUHVV GDWD GDWD GDWD †... - Page 173 PCI Bus Host Bridge Clock #12: The external PCI bus master retries the delayed transaction. While a delayed transaction is pending, all other read transactions are retried by the host bridge (these are not latched as delayed transactions). Write transactions, however, are allowed to complete and are put into the write FIFO.
-
Page 174: Figure 9-16 Pci Host Bridge Target Disconnect
PCI Bus Host Bridge Figure 9-16 PCI Host Bridge Target Disconnect CLKPCIIN hqq…r†† qh‡h qh‡h! qh‡h" CBEx …v‡rÃp€q ir" FRAME IRDY TRDY DEVSEL STOP à hb_req hb_gnt The following sequence annotates the PCI host bridge target disconnect shown in Figure 9-16. Clock #1: An external PCI bus master initiates a write transaction to ÉlanSC520 microcontroller SDRAM. -
Page 175: Interrupts
PCI Bus Host Bridge 9.5.5 Interrupts The PCI host bridge has one maskable interrupt request signal and one NMI signal routed to the ÉlanSC520 microcontroller’s interrupt controller. These interrupt signals are shared by the arbiter, and PCI master and target controllers of the host bridge. Each interrupt source (both master and target sources) can be individually programmed to generate a maskable interrupt instead of a non-maskable interrupt request. -
Page 176: Latency
PCI Bus Host Bridge 9.5.6 Latency PCI bus latency issues are described separately for the CPU and external PCI bus masters. Master latency refers to the case when the ÉlanSC520 microcontroller’s Am5 86 CPU is the master on the PCI bus. Target latency refers to the case when the ÉlanSC520 microcontroller is a PCI bus target accessed by external PCI bus masters. -
Page 177: Initialization
PCI Bus Host Bridge The concurrent nature of ÉlanSC520 microcontroller’s system architecture is such that a SDRAM read request from an external PCI master may be delayed. The reasons for this delay are: The Am5 86 CPU may be currently accessing ROM, GP bus, or SDRAM. The SDRAM controller may be currently servicing a SDRAM refresh. - Page 178 PCI Bus Host Bridge c. Program the ÉlanSC520 microcontroller-specific PCI host bridge configuration (write posting, retry time-out counter, interrupts, etc.). Note that write-posting must be disabled while operating in nonconcurrent arbitration mode. See Chapter 8, “System Arbitration”, for further details on nonconcurrent mode arbitration. d.
-
Page 179: Chapter 10 Sdram Controller
CHAPTER SDRAM CONTROLLER 10.1 OVERVIEW The ÉlanSC520 microcontroller includes an integrated SDRAM controller. Features include: SDRAM (synchronous DRAM) support 3.3-V DC 66-MHz SDRAM or faster (16 Mbit through 256 Mbit) Achieves 3-1-1-1 read bursts on SDRAM (page hit for all device speed grades with CAS latency (C ) = 2) Support for up to four banks, each bank independently programmed for size and... -
Page 180: Figure 10-1 Sdram Controller Block Diagram
SDRAM Controller Figure 10-1 SDRAM Controller Block Diagram Élan™SC520 Microcontroller MA12–MA0 BA1–BA0 SCS3–SCS0 SCASB–SCASA Read Buffer SRASB–SRASA SDRAM SDQM3–SDQM0 Controller SWEB–SWEA CLKMEMOUT Write Buffer CLKMEMIN MECC6–MECC0 MD31–MD0 33 MHz 32 kHz 32KXTAL2–32KXTAL1 Clock Generator 33MXTAL2–33MXTAL1 33 MHz 10-2 Élan™SC520 Microcontroller User’s Manual... -
Page 181: Figure 10-2 Detailed Block Diagram Of Sdram Controller
SDRAM Controller Figure 10-2 Detailed Block Diagram of SDRAM Controller Élan™SC520 Microcontroller MA12–MA0 BA1–BA0 MA Gen. x5_addr[27–2] SCS3–SCS0 Page/Bnk SCASB–SCASA 32 kHz x5_control SRASB–SRASA Control 33 MHz SWEB–SWEA CLKMEMOUT 66-MHz PLL x5_be[3–0] SDQM3–SDQM0 be3–be0 data[31–0] Write Buffer MD31–MD0 x5_data[31–0] Read Buffer x5_data[31–0] Check MECC6–MECC0... -
Page 182: Figure 10-3 Sdram Bank Configuration
SDRAM Controller Figure 10-3 SDRAM Bank Configuration MD31–MD0 MECC6–MECC0 MA12–MA0, SRASB BA1–BA0 D[38:32] D[31:24] D[23:16] D[15:8] D[7:0] SCS3 DQM[3]* DQM[3] DQM[0] DQM[2] DQM[1] SDQM3– SDQM0 SWEB D[38:32] D[31:24] D[23:16] D[15:8] D[7:0] SCS2 DQM[3]* DQM[0] DQM[3] DQM[2] DQM[1] SCASB SRASA D[38:32] D[31:24] D[23:16] D[15:8]... -
Page 183: Sdram Pins
SDRAM Controller Figure 10-4 Example Configuration of a 168-Pin SDRAM DIMM MA12–MA0, MD31–MD0 BA1–BA0 DQ63–DQ32 DQ31–DQ0 Bank 1 Bank 0 SDQM3 SDQM2 SDQM1 SDQM0 SCASA SCASB SRASA SRASB SWEB SWEA SCS1 SCS0 10.3.1 SDRAM Pins The SDRAM interface pins are dedicated to supporting SDRAM devices only. Four chip select signals, SCS3–SCS0, are provided for independent bank selection. -
Page 184: Sdram Clocking
SDRAM Controller – For example, banks 0 and 1 can share the SRASA and SCASA signal. – Likewise, banks 2 and 3 can share the SRASB and the SCASB signal. Two SWE signals are also provided to alleviate single pin loading. –... -
Page 185: Figure 10-5 Sdram Clock Generation
SDRAM Controller Figure 10-5 shows a lightly loaded system. Typically, this delay can be implemented as fast buffers, capacitors, series resistors, etc. or as a short. Figure 10-5 SDRAM Clock Generation CLKMEMOUT SDRAM Controller Delay CLKMEMIN SDRAM Bank Élan™SC520 Microcontroller Figure 10-6 shows an example of a two-bank SDRAM system that uses an external clock driver. -
Page 186: Sdram Loading
SDRAM Controller 10.3.3 SDRAM Loading Table 10-2 through Table 10-5 show estimated capacitances for the SDRAM devices that the ÉlanSC520 microcontroller can support. (See Table 10-8 on page 10-13 for a listing of the SDRAM devices supported by ÉlanSC520 microcontroller.) The tables are broken up for SDRAM device data width for clarity. -
Page 187: Table 10-4 Estimated Capacitance (16-Bit Sdram Devices)
SDRAM Controller Table 10-4 Estimated Capacitance (16-Bit SDRAM Devices) Number SRASx SCASx SCSx SWEx SDQMx MAx/BAx of 32-Bit Loading Loading Loading Loading Loading Loading Loading Loading Banks (pF) (pF) (pF) (pF) (pF) (pF) (pF) (pF) Notes: Capacitive loads shown in the table above are derived from an estimated SDRAM pin capacitance value of 5 pF for SRASx, SCASx, SWEx, MAx, BAx, SDQMx, and SCSx;... -
Page 188: Registers
SDRAM Controller 10.4 REGISTERS A summary listing of the registers used to control the SDRAM configuration are shown in Table 10-6. Table 10-6 SDRAM Controller Registers—Memory-Mapped MMCR Offset Register Mnemonic Address Function SDRAM Control DRCCTL Operation mode select, refresh enable, refresh rate select, SDRAM write buffer test mode enable SDRAM Timing Control... -
Page 189: Operation
SDRAM Controller 10.5 OPERATION The ÉlanSC520 microcontroller supports up to four 32-bit banks of SDRAM, with a maximum capacity of 256 Mbytes. This integrated SDRAM controller interfaces gluelessly to most commodity synchronous DRAM (SDRAM) devices. Mixed symmetries are supported across all four banks. The ÉlanSC520 microcontroller supports a column boundary method to accept a wide variety of SDRAM devices. -
Page 190: Sdram Addressing
SDRAM Controller During read-modify-write cycles, the SDRAM burst read portion of the transaction is terminated early by the write cycle. This is independent of the enable state of the read- ahead feature of the read buffer, which is provided to increase read performance by prefetching data from SDRAM. -
Page 191: Supported Sdram Devices
SDRAM Controller 10.5.2.1 Supported SDRAM Devices The ÉlanSC520 microcontroller supports the SDRAM organizations listed in Table 10-8. (Note that SDRAM devices requiring less than 11 row address bits are not supported, and are not included in the table.) This table includes all possible device organizations supported by the column boundary method, including those that may not be available at this time. - Page 192 SDRAM Controller Table 10-8 SDRAM Devices Supported with Column Boundary Specification (Continued) Device Column Count Dimension MA/BA Bank Width Density Banks Organization Device Architecture per Bank Row: Col Width (32-Bit) 9-bit 16 Mbit 4M x 4 2M x 4 x 2-banks 12:9 13-bit 16 Mbytes...
-
Page 193: Table 10-9 Column Address Configuration Settings For Sdram
SDRAM Controller Table 10-8 SDRAM Devices Supported with Column Boundary Specification (Continued) Device Column Count Dimension MA/BA Bank Width Density Banks Organization Device Architecture per Bank Row: Col Width (32-Bit) 11-bit 64 Mbit 16M x 4 8M x 4 x 2-banks 12:11 13-bit 64 Mbytes... -
Page 194: Page Size
SDRAM Controller 10.5.2.2 Page Size The page size of an SDRAM device is based on the column address width of the device. The ÉlanSC520 microcontroller address mapping takes advantage of the full page specified by the devices column address width. Table 10-10 lists the page size available based on the column address width specified. -
Page 195: Buffering
SDRAM Controller To avoid this, whenever a single byte is to be written to the SDRAM (or for that matter, any number of bytes that is less than the full doubleword), ECC first reads the whole data word, checks for any single- or multi-bit errors, and, if any are present, generates the corresponding interrupt and corrects the data (for a single-bit error), modifies the necessary bytes, and then generates the check-bits across the modified four bytes. -
Page 196: Sdram Control Configuration
SDRAM Controller demanded access to be read into the read buffer. GP-DMA read accesses are always single word accesses. The read buffer is always enabled, however, the read-ahead feature and write buffer can be independently enabled and are disabled after a system reset or programmable reset. For more information on the SDRAM controller’s buffering, see Chapter 11, “Write Buffer and Read Buffer”. - Page 197 SDRAM Controller For example, if an SDRAM device is organized as 2M x 8 x 4 banks (8Mb x 8) with 4096 rows and 512 columns and requires a 64-ms refresh interval, by using Table 10-11, the refresh rate is 15.6 µs. During an SDRAM refresh period, all enabled banks are issued an Auto Refresh command.
-
Page 198: Sdram Timing Configuration
SDRAM Controller 10.5.5.4 Operation Mode Select The ÉlanSC520 microcontroller provides an SDRAM Operation Mode Select (OPMODE_SEL) bit field in the SDRAM Control (DRCCTL) register (MMCR offset 10h). These bits are used to select a particular mode of operation of the SDRAM controller. The default mode of operation is normal SDRAM mode. -
Page 199: Ras Precharge
SDRAM Controller 10.5.6.2 RAS Precharge (T The RAS Precharge (T ) parameter of an SDRAM device refers to the minimum period of time that must be met following a Precharge command until a subsequent command to the same bank can be issued. After T is met, the SDRAM device is considered to be in the idle state. -
Page 200: Minimum Ras (Tras )
SDRAM Controller 10.5.6.5 Minimum RAS (T The minimum RAS parameter of an SDRAM device refers to the minimum period of time that a row must remain open. This is the period of time between an Active command and a Precharge command to the same internal bank. This parameter is referred to as T Since the ÉlanSC520 microcontroller performs single write cycles, the minimum T occurs during write cycles. -
Page 201: Sdram Write Cycle
SDRAM Controller 10.5.7.2 SDRAM Write Cycle With the write buffer enabled, all writes to the SDRAM come from the write buffer. With the write buffer disabled, the SDRAM write cycle could occur due to any of the following reasons: 86 CPU ÉlanSC520 microcontroller responding to PCI burst cycle as target GP-DMA All the writes are configured for single write mode, with each write occurring independently. -
Page 202: Ecc Sdram Cycles
SDRAM Controller Figure 10-9 SDRAM CPU Burst Write (Write Buffer and ECC Disabled) (Page Miss/Page Hit) clk_cpu x5_abus blast x5_data_out brdy pghit clk_mem MA12–MA0, BA1–BA0 Command MD31–MD0 Notes: This timing diagram does not account for resynchronization of SDRAM signals with CLKMEMIN. 10.5.7.3 ECC SDRAM Cycles When ECC is enabled, additional overhead is necessary to compensate for ECC logic... -
Page 203: Figure 10-10 Sdram Burst Read Cycle With Ecc Enabled
SDRAM Controller Figure 10-10 SDRAM Burst Read Cycle with ECC Enabled clk_cpu x5_abus x5_data_in brdy pghit clk_mem MA12–MA0, BA1–BA0 Command CAS latency = 2 MD31–MD0 MECC6– MECC0 Notes: This timing diagram does not account for resynchronization of SDRAM signals with CLKMEMIN. The ECC overhead is even higher in the case of a read-modify-write cycle, as shown in Figure 10-11. -
Page 204: Sdram Auto Refresh Cycle
SDRAM Controller Figure 10-11 SDRAM Read-Modify-Write Cycle (for Data Write) with ECC Enabled (Page Hit) clk_cpu x5_abus 1011 be3–be0 x5_data_out 00AB0000 brdy pghit clk_mem MA12–MA0, BA1–BA0 Command CAS latency = 2 MD31–MD0 MECC6–MECC0 Notes: 1. This timing diagram does not account for resynchronization of SDRAM signals with CLKMEMIN. 2. -
Page 205: Sdram Mode Register Access Cycles
SDRAM Controller Figure 10-12 SDRAM Auto Refresh Cycle CLKMEMOUT SCS0 SCS1 SCS2 SCS3 MA12–MA0, All Bnk. BA1–BA0 Command Pre. Auto Ref. Auto Ref. Auto Ref. Auto Ref. 10.5.7.5 SDRAM Mode Register Access Cycles The mode register contained in the SDRAM devices is used to define the specific mode of operation of the SDRAM. -
Page 206: Software Considerations
SDRAM Controller 10.5.9 Software Considerations 10.5.9.1 ECC Errors The ECC logic in the SDRAM controller detects single-bit error and multi-bit errors in the SDRAM data being accessed. When a single-bit error is detected, a maskable interrupt is generated. See Chapter 15, “Programmable Interrupt Controller”, for information on steering this interrupt. -
Page 207: Initialization
SDRAM Controller When the write buffer is enabled, writes to SDRAM occur independently of any associated master activity until the write buffer is empty. Since the SDRAM data bus may be shared with the ROM/Flash controller, write-buffer writes may request concurrently with master requests to ROM/Flash. -
Page 208: Sdram Device Initialization
SDRAM Controller to occur throughout the entire duration of the programmable reset. Upon the assertion of the programmable reset, the SDRAM controller arbiter lets the current SDRAM access complete before returning the controller state machines to their idle states. This prevents data corruption in the SDRAM array should the programmable reset be asserted during an access to SDRAM. -
Page 209: Nop Command
SDRAM Controller 10.6.2.2 NOP Command Once power is applied and the clock is stable, most SDRAM devices require a 100-µs delay prior to applying an executable command. Therefore, boot code must guarantee that SDRAM is not accessed immediately after reset. During this period and continuing at least through the end of this period, the NOP command should be applied. -
Page 210: Boot Process
SDRAM Controller 10.6.3 Boot Process In a closed embedded system, the designer may be able to simply choose the correct values to output to the configuration registers. Systems where the SDRAM parameters are not known at boot time present more issues. Many SDRAM considerations, such as signal loading, cannot be accurately determined by software. -
Page 211: Determining The Number Of Columns For An External Bank
SDRAM Controller Precharge command closes all open pages in the SDRAM devices, thus placing them in an idle state. This also forces the SDRAM controller’s page table entries to be invalidated. The column address requirement of the device specifies its symmetry (i.e., its usable number of columns, or page width, that the SDRAM controller can utilize), but does not specify the amount of addressable SDRAM in the 32-bit bank. -
Page 212: Determining The Number Of Internal Banks
SDRAM Controller The final address must have SDRAM column address bits 11, 9, and (processor address bits 12–10) off. There are many addresses which meet this criteria, of which one example is: address1 = 0E001E00h address2 = 0E000E00h address3 = 0E000600h address4 = 0E000200h Here is the sequence to determine the number of columns for a given external bank of SDRAM:... -
Page 213: Determining The True External Bank Ending Address
SDRAM Controller The final address must have processor address bits 27–24 all off. There are many addresses which meet this criteria, of which one example is: address5 = 0F000000h address6 = 07000000h address7 = 03000000h address8 = 01000000h address9 = 00000000h Here is the sequence to determine the correct number of internal banks: 1. - Page 214 SDRAM Controller 10-36 Élan™SC520 Microcontroller User’s Manual...
-
Page 215: Chapter 11 Write Buffer And Read Buffer
CHAPTER WRITE BUFFER AND READ BUFFER 11.1 OVERVIEW The ÉlanSC520 microcontroller includes two buffering techniques to optimize the SDRAM system performance. These include a write buffer and a read buffer with a read-ahead feature. The write buffer provides a mechanism for all masters (Am5 86 CPU, PCI, or GP-DMA) to post write data with zero wait states. -
Page 216: Block Diagram
Write Buffer and Read Buffer 16-bit contiguous transfers, allowing multiple individual transfers to be merged into a single transaction to SDRAM. The read-ahead feature of the read buffer enhances read burst activity by the Am5 86 CPU and external PCI master burst read requests. SDRAM cache line fills by the Am5 86 CPU are probably the most common read requests. -
Page 217: System Design
Write Buffer and Read Buffer Figure 11-2 Write Buffer and Read Buffer Block Diagram Élan™SC520 Microcontroller Write Buffer/Read Buffer Read Buffer rd_ad Address Latch [27–2] 6qq…r††ÃU htà 6qq…r††ÃU htà Read Buffer Data Latch doubleword 7 dram_ doubleword 6 rab_data[31–0] data[31–0] doubleword 5 x5_rd_ doubleword 4... -
Page 218: Registers
Write Buffer and Read Buffer are not shown in this table. When enabled, the multiplexed signals shown in Table 11-1 either disable or alter any other function that uses the same pin. Table 11-1 SDRAM Signals Shared with Other Interfaces Default Signal Alternate Function Control Bit Register... -
Page 219: Write Buffer
Write Buffer and Read Buffer 11.5.1 Write Buffer The ÉlanSC520 microcontroller’s SDRAM controller contains 32 4-byte write data buffers. The write buffer provides benefits beyond that of a standard posting FIFO. A standard FIFO blindly posts data without knowledge of data that already exists within the FIFO. The write buffer is more efficient in that each write access is snooped. - Page 220 Write Buffer and Read Buffer For read cycles, the snoop feature is used to determine if data associated with the same address of the read request already exists in the write buffer. If data is already present, that data is read-merged with data being returned from SDRAM. This enhances SDRAM system performance by not requiring the write buffer to be flushed prior to satisfying a read cycle.
-
Page 221: Figure 11-3 Write Buffer Merging Example
Write Buffer and Read Buffer Figure 11-3 Write Buffer Merging Example DMA Write, Byte, Adrs 0FBB000, Data 88h D[31:24] D[23:16] D[15:8] D[7:0] DMA Write, Byte, Adrs 0FBB000, Data 88h DMA Write, Byte, Adrs 0FBB001, Data 92h D[31:24] D[23:16] D[15:8] D[7:0] DMA Write, Byte, Adrs 0FBB000, Data 88h DMA Write, Byte, Adrs 0FBB001, Data 92h DMA Write, Byte, Adrs 0FBB002, Data 44h... -
Page 222: Figure 11-4 Write Buffer Collapsing Example
Write Buffer and Read Buffer Figure 11-4 Write Buffer Collapsing Example CPU Write, Low Word, Adrs 0A00X, Data 55AAh D[31:24] D[23:16] D[15:8] D[7:0] CPU Write, Low Word, Adrs 0A00X, Data 55AAh CPU Write, Doubleword, Adrs 0X, Data 12345678h D[31:24] D[23:16] D[15:8] D[7:0] CPU Write, Low Word, Adrs 0A00X, Data 55AAh... -
Page 223: Write Buffer Watermark
Write Buffer and Read Buffer Figure 11-5 Write Buffer Read-Merging Example Read Merge EE001122 EE00CDEF Logic xxxxCDEF Write Buffer (Data Segment) Master D[31:24] D[23:16] D[15:8] D[7:0] A[27:2] BE[3:0] SDRAM Write Buffer (Address Segment) Notes: This example illustrates a 32-bit master read of address A000000h, which causes a read hit in the write buffer. -
Page 224: Read Buffer And The Read-Ahead Feature
Write Buffer and Read Buffer The SDRAM controller’s arbiter supports a write buffer park feature, such that after the write buffer’s watermark is reached and requests SDRAM service, the SDRAM controller’s arbiter continues to grant the write buffer SDRAM service, until either a master read cycle is requested to SDRAM or a SDRAM refresh occurs. -
Page 225: Dma Considerations
Write Buffer and Read Buffer request to acquire the next cache line. The demanded read cycle implies that the first doubleword request by the master will be serviced first, such that the master can continue while the remainder of the cache line is prefetched. If the read-ahead feature of the read buffer is enabled, a prefetch occurs only for master read access that results in a burst of two or more doublewords. -
Page 226: Pci Considerations
Write Buffer and Read Buffer In a system configured with multiple active DMA channels, read buffer misses will most likely occur for each change of channel tenure. This is because each DMA channel accesses different SDRAM regions that will most likely miss the read buffer, which still contains the cache line of data fetched during the previous channel’s tenure. -
Page 227: Software Considerations
Write Buffer and Read Buffer Large PCI burst requests will benefit more from the read-ahead function than short, frequent independent PCI read transfers. Since the Am5 86 CPU is a major requestor of SDRAM read accesses, short and frequent independent PCI transfers may result in read-ahead thrashing. -
Page 228: Figure 11-6 Bus Thrashing With Write Buffer Disabled And Enabled
Write Buffer and Read Buffer Since the write buffer supports data read-merging, data coherency overhead is kept to a minimum. The write buffer’s read-merging capability is possible due to the write buffer’s ability to snoop its own contents during read and write cycles. In the special case of a read to an address contained in the write buffer, the overhead associated with flushing the entire contents of the write buffer to maintain data coherency is eliminated. -
Page 229: Initialization
Write Buffer and Read Buffer 11.6 INITIALIZATION The write buffer and read buffer are reset during a system reset. As a result of this system reset event, the write buffer and read-ahead feature of the read buffer are both disabled, and all associated state machines are returned to their idle states. - Page 230 Write Buffer and Read Buffer 11-16 Élan™SC520 Microcontroller User’s Manual...
-
Page 231: Chapter 12 Rom/Flash Controller
CHAPTER ROM/FLASH CONTROLLER 12.1 OVERVIEW The ÉlanSC520 microcontroller includes an integrated ROM controller that provides a high performance interface to ROMs, EPROMs, and Flash devices. Improved performance is achieved by supporting a full 32-bit data path and advanced page-mode devices. Note that in this document the term ROM is used interchangeably with Flash and EPROM for simplicity. -
Page 232: Block Diagram
ROM/Flash Controller 12.2 BLOCK DIAGRAM Figure 12-1 shows a block diagram of the ROM controller. Figure 12-1 ROM Controller Block Diagram CFG2–CFG0 Élan™SC520 Microcontroller Data Bus (GPD15–GPD0 or MD31–MD0) GPA25–GPA0 ROM Controller Reset Pinstrap data for BOOTCS Configuration Registers BOOTCS ROMCS1 ROMCS2 Configuration data... -
Page 233: Voltage Isolation
ROM/Flash Controller The ROMCS1 and ROMCS2 signals are provided to support two additional ROM chip selects. These pins are shared with general-purpose chip selects, GPCS1 and GPCS2, respectively, as shown in Table 12-2. When enabled, the multiplexed signals shown in Table 12-2 either disable or alter any other function that uses the same pin. -
Page 234: Figure 12-2 Voltage Isolation Examples
ROM/Flash Controller If the system has ROM devices on both the SDRAM data bus and the GP bus and data bus buffers are used (on either bus), ROMBUFOE should be qualified with the appropriate ROM chip selects and ROMRD, as needed, to prevent bus conflicts. For example, when SDRAM buffering is enabled, the SDRAM controller could be attempting to complete posted writes to the SDRAM. -
Page 235: Registers
ROM/Flash Controller 12.4 REGISTERS Table 12-3 shows the memory-mapped registers used to configure the ROM controller. Table 12-3 ROM Controller Registers—Memory-Mapped MMCR Offset Register Mnemonic Address Function BOOTCS Control BOOTCSCTL BOOTCS device select (SDRAM bus or GP bus), device data width, device operation mode, subsequent access delay, first access delay ROMCS1 Control ROMCS1CTL... -
Page 236: Supported Device Types
ROM/Flash Controller ROM devices are accessible by the Am5 86 CPU only. Normal operation of the ÉlanSC520 microcontroller is not guaranteed if an external PCI master or GP-DMA cycle results in a ROM access. The addresses for ROM devices are always provided via the GP bus, independently of whether the data pins of the ROM are connected to the GP bus or SDRAM bus. -
Page 237: Rom Control And Timing Configuration
ROM/Flash Controller 12.5.2 ROM Control and Timing Configuration The ÉlanSC520 microcontroller provides ROM device configuration per chip select for the following: ROM location (on GP data bus or SDRAM data bus) ROM width (8, 16, or 32 bits) Operating mode (page-mode or non-page-mode) Access timing 12.5.2.1 ROM Location... - Page 238 ROM/Flash Controller Figure 12-4 Non-Page-Mode ROM: Fetching Four Words from a 16-Bit ROM GPA25–GPA0 - - - 0h - - - 2h - - - 8h - - - 4h GPD15–GPD0, or MD15–MD0 ROMRD BOOTCS Figure 12-5 Page-Mode ROM: Fetching Four Doublewords (Aligned) from a 32-Bit ROM GPA25–GPA0 - - - 0h - - - 4h...
-
Page 239: Bus Cycles
ROM/Flash Controller Table 12-4 Example: ROM Access Timing and Wait States Wait States Access Timing (ns) Notes: 1. This example assumes that a 33.333-MHz crystal is being used in the system. 12.5.3 Bus Cycles The ROM controller always returns the amount of read data requested by the Am5 86 CPU, i.e., brdy is returned for all read transfers from ROM. -
Page 240: Page-Mode Read Access
ROM/Flash Controller Figure 12-7 Multiple Accesses: Data Amounts Smaller than One Doubleword (2 Bytes) from an 8-Bit ROM CPU clock GPA25–GPA0 ADR+0 ADR+1 GPD7–GPD0, or MD7–MD0 brdy blast ROMRD BOOTCS Notes: An 8-bit ROM is attached to the 16-bit GP bus. 12.5.3.2 Page-Mode Read Access The ROM controller also provides performance advantages for Am5... -
Page 241: Cache-Line Fill
ROM/Flash Controller Figure 12-9 Page Access for Fetching Two Doublewords from a 16-Bit ROM CPU clock start cycle GPA25–GPA2 - - - C - - - 8 GPA1–GPA0 GPD15–GPD0, or MD15–MD0 brdy blast BOOTCS ROMRD 12.5.3.3 Cache-Line Fill If a memory section is accessed that is cacheable, the ken signal is asserted to the Am5 CPU indicating a cache-line fill operation. -
Page 242: Software Considerations
ROM/Flash Controller width of the ROM device, e.g., if a 16-bit write is performed to an 8-bit ROM, two Am5 CPU write cycles are generated to complete the operation. All write access to Flash devices must occur in units no smaller than the data width of the device. -
Page 243: Latency
ROM/Flash Controller is an easy restriction to overcome, because programming Flash is usually done during non- performance critical periods, such as during user configuration. However, new “dual boot” Flash allows fetching instructions from one portion of the device while programming or erasing a sector in another portion. -
Page 244: Initialization
ROM/Flash Controller The lowest latency times can be achieved if fast 32-bit ROMs are implemented for Execute- In-Place (XIP) operating systems or for data structures that are accessed frequently. This ensures a rapid data transfer, which frees up the SDRAM resource for access by other masters. -
Page 245: Chapter 13 General-Purpose Bus Controller
In either case, the ROM access shares GPA25–GPA0 with the GP bus. For additional system diagrams using the GP bus, see “Interfacing with a Super I/O Controller” on page 13-13 and “Interfacing with an AMD Enhanced Serial Communications Controller (8 MHz)” on page 13-14. -
Page 246: Figure 13-1 Gp Bus Controller System Block Diagram
General-Purpose Bus Controller Figure 13-1 GP Bus Controller System Block Diagram Élan™SC520 Microcontroller UART1 UART2 GPRESET Reset GPIRQ10– GPIRQ0, Internal GP Bus INTA–INTD GP-DMA Timers GPA25–GPA0 GPD15–GPD0 GP Bus Controller GPDBUFOE* Echo mode select From CPU: m/io GPIOCS16* GPMEMCS16* GP Bus GPBHE* Control bs16... -
Page 247: Table 13-1 Gp Bus Signals Shared With Other Interfaces
General-Purpose Bus Controller Table 13-1 GP Bus Signals Shared with Other Interfaces Interface or Default Alternate Signal Function Control Bit Register TMROUT0 GPCS7 GPCS7_SEL Chip Select Pin Function Select (CSPFS) register (MMCR offset C24h) TMROUT1 GPCS6 GPCS6_SEL TMRIN0 GPCS5 GPCS5_SEL TMRIN1 GPCS4 GPCS4_SEL... -
Page 248: Gp Bus Loading
General-Purpose Bus Controller 13.3.1 GP Bus Loading ± As more external devices are connected to the GP bus, loading on GPA25 GPA0 and ± ± GPD15 GPD0 will increase. Therefore, the rise time and fall time of GPA25 GPA0 and ±... -
Page 249: Registers
General-Purpose Bus Controller Figure 13-3 Example: Using a Voltage Translator GPCSx GPDBUFOE Voltage Translator Élan™SC520 Microcontroller XCVR GPIORD GPMEMRD 5-V Data GPD15–GPD0 3-V Data Notes: GPCSx is the chip select for the 5-V peripheral. 13.4 REGISTERS Table 13-2 shows the memory-mapped registers used to configure the GP bus controller. Table 13-2 GP Bus Registers—Memory-Mapped MMCR... -
Page 250: Operation
General-Purpose Bus Controller Table 13-2 GP Bus Registers—Memory-Mapped (Continued) MMCR Offset Register Mnemonic Address Function GP Write Offset GPWROFF C0Eh Offset from the beginning of the bus cycle for GPIOWR and GPMEMWR GP ALE Pulse Width GPALEW C0Fh Width of the GPALE signal from the offset GP ALE Offset GPALEOFF C10h... -
Page 251: Programmable Bus Interface Timing
General-Purpose Bus Controller The GP bus also provides an echo mode that is useful for debugging. If GP bus echo mode enabled, the internal GP bus cycle is echoed out on the external pins to enable visibility of internal cycles. Accesses to internal peripherals that are “echoed” out utilize the programmed timing set to ensure that there is no timing conflict with other external peripherals. -
Page 252: Using Gprdy With Programmable Timing
General-Purpose Bus Controller Figure 13-4 GP Bus Timing Format – GPA25 GPA0 Address Valid GPCS GPCSOFF + 1 GPCSPW + 1 GPCSRT + 1 GPMEMRD or GPIORD GPRDOFF + 1 GPRDW + 1 GPMEMWR or GPIOWR GPWROFF + 1 GPWRW + 1 GPALE GPALEOFF + 1 GPALEW + 1... -
Page 253: I/O-Mapped And Memory-Mapped Device Support
General-Purpose Bus Controller Table 13-3 GP Bus Echo Mode Minimum Timing GPCSPW, GPRDW, GPCSOFF, GPRDOFF, GPALEW GPCSRT GPALEOFF (Offset) (Pulse Width) (Recovery Time) Signal Type Register Value Register Value Register Value GP chip select GP read — GP write — GPALE —... -
Page 254: Sharing The Address And Data Bus With The Rom/Flash Controller
General-Purpose Bus Controller register (MMCR offset C01h) and the state of the GPIOCS16 and GPMEMCS16 signals. The Am5 86 CPU then generates multiple 8-bit or 16-bit bus cycles until all 32-bit data is accessed; thus, the size is transparent to software. This is true for read accesses and write accesses. -
Page 255: Dma Interface
General-Purpose Bus Controller Note that accesses initiated by the GP bus DMA controller are not affected by enabling the GP bus echo mode, and therefore the GP bus DMA controller still asserts GPAEN as it does during normal operation.During an internal GPDMA access in GP bus echo mode, the external GP bus commands, GPIORD, GPMEMRD, GPIOWR, GPMEMWR, are not asserted. -
Page 256: Table 13-4 Cross-Reference Table Of Isa Signals And Gp Bus Signals
General-Purpose Bus Controller Table 13-4 Cross-Reference Table of ISA Signals and GP Bus Signals ISA Signal Name GP Bus Signal Name GPAEN BALE GPALE BCLK (Not Supported) DACK GPDACK GPDRQ IOCHK Supported through GPIRQ IOCHRDY GPRDY IOCS16 GPIOCS16 GPIORD GPIOWR GPIRQ LA23–LA17 GPA23–GPA17... -
Page 257: Interfacing With A Super I/O Controller
General-Purpose Bus Controller 13.5.8.2 Interfacing with a Super I/O Controller Figure 13-5 shows an example system diagram of the ÉlanSC520 microcontroller interfacing with a Super I/O controller. Figure 13-6 shows the interfacing timing example. In this example, the programmable interface timing registers can be programmed as shown in Table 13-5, using the equation from “Programmable Bus Interface Timing”... -
Page 258: Interfacing With An Amd Enhanced
3. This example assumes that a 33.333-MHz crystal is being used in the system. 13.5.8.3 Interfacing with an AMD Enhanced Serial Communications Controller (8 MHz) This slow version is depicted to illustrate an example of how the programmable timing can be used to function with various timing requirements. -
Page 259: Figure 13-7 Élansc520 Microcontroller Interfacing With An Am85C30
General-Purpose Bus Controller Table 13-6 Example AMD Enhanced Serial Communications Controller Interface Timing Pulse Recovery Offset Offset Chip Width Pulse Chip Time Recovery Chip GP Bus Register Time Require- Register Width Require- Register Timer Require- Signal Type Value (ns) ment (ns) -
Page 260: Bus Cycles
General-Purpose Bus Controller Figure 13-8 Timing Diagram of an Am85C30 Interface GPA1–GPA0 Address Valid GPCSx 30 ns 90 ns 150 ns GPIORD 90 ns 150 ns GPIOWR 90 ns GPALE (Not needed) 30 ns 30 ns GPD7–GPD0 Read Data GPD7–GPD0 Write Data 270 ns Beginning of a bus cycle... -
Page 261: 16-Bit Data Access Of A 16-Bit I/O Device
General-Purpose Bus Controller 13.5.9.2 16-Bit Data Access of a 16-Bit I/O Device A 16-bit data read/write access to 16-bit I/O devices are similar to the 8-bit I/O device accesses. In 16-bit accesses, all 16 bits of GPD are used. For memory-mapped I/O accesses, GPMEMRD and GPMEMWR are used instead of GPIORD and GPIOWR. -
Page 262: 32-Bit Data Access Of An 8-Bit I/O Device
General-Purpose Bus Controller 13.5.9.4 32-Bit Data Access of an 8-Bit I/O Device A 32-bit data access of an 8-bit I/O device requires four consecutive 8-bit data accesses of the 8-bit I/O device, but the consecutive 8-bit data accesses are resolved by the Am5 CPU transparent to software. -
Page 263: 8-Bit Data Access Of A 16-Bit I/O Device
General-Purpose Bus Controller 13.5.9.6 8-Bit Data Access of a 16-Bit I/O Device The GPA0 and GPBHE signals are required to determine which byte of a 16-bit peripheral is accessed during byte read or write cycles. Table 13-7 describes how to determine which byte is accessed. -
Page 264: Wait States
General-Purpose Bus Controller The latest assertion time for these two signals is the same as the timing for the GPRDY deassertion time (see “GPRDY Recognition” on page 13-20). Table 13-8 Dynamic Bus Sizing Override of Programmed Data Width GP Chip Select Data Width GPIOCS16 (GPCSDW) Register Setting GPMEMCS16 Assertion Resultant Bus Size... -
Page 265: Interrupts
General-Purpose Bus Controller command strobes will be deasserted after the GPRDY signal is internally synchronized and sampled asserted by the 33-MHz clock and after the programmed pulse width value for the strobe has expired. Figure 13-16 GPRDY Timing GPA25–GPA0 Address GPCSx GPMEMRD, GPMEMWR, GPIORD, or GPIOWR... -
Page 266: Initialization
General-Purpose Bus Controller 13.6 INITIALIZATION The GP bus controller is reset by a system reset. The internal GP bus is enabled, as are holes in the lower 1-Kbyte of I/O space; however, no chip selects are enabled. The external GP bus is disabled until the Programmable Address Region (PAR) registers are initialized. GP bus reset can be generated via a system reset or software write. -
Page 267: Chapter 14 Gp Bus Dma Controller
CHAPTER GP BUS DMA CONTROLLER 14.1 OVERVIEW The ÉlanSC520 microcontroller includes an integrated GP bus DMA (GP-DMA) controller. The GP-DMA controller is designed to transfer data between external GP bus peripherals and SDRAM. Transfers between the internal UART serial ports and SDRAM are also supported. -
Page 268: Figure 14-1 Gp-Dma Controller Block Diagram
GP Bus DMA Controller Figure 14-1 GP-DMA Controller Block Diagram Élan™SC520 Microcontroller GP-DMA Controller GPDRQ3–GPDRQ0 txdrq[1–0] rxdrq[1–0] txdack[1–0] UARTs rxdack[1–0] GPA25 – GPA0 dior Channel Configuration GPD15 – GPD0 diow Mapping Registers GP Bus dmemr GP Bus dmemw Initiator GPTC* (I/O) GPAEN* Control... -
Page 269: System Design
GP Bus DMA Controller Figure 14-2 Master and Slave Core Cascading Diagram ADDR[15–0] breq GP data HLDA DATA[7–0] bgnt dma0_cs ADDR[15:0] Master Core gpdrq7 Channel 7 gpdack7 DACK gpdrq6 Channel 6 gpdack6 DACK gpdrq5 Channel 5 gpdack5 DACK Interconnect Channel 4 daddr[27–0] DACK Logic... -
Page 270: Registers
GP Bus DMA Controller Table 14-1 GP-DMA Signals Shared with Other Interfaces (Default) Interface Signal Function Control Bit Register PIO12 GPDACK0 PIO12_FNC PIO15–PIO0 Pin Function Select (PIOPFS15_0) register (MMCR offset C20h) PIO11 GPDACK1 PIO11_FNC PIO10 GPDACK2 PIO10_FNC PIO9 GPDACK3 PIO9_FNC PIO8 GPDRQ0 PIO8_FNC... - Page 271 GP Bus DMA Controller Table 14-2 GP-DMA Controller Registers—Memory-Mapped (Continued) MMCR Offset Register Mnemonic Address Function GP-DMA Channel 1 GPDMAEXTPG1 D87h Bits 27–24 of the memory address for Extended Page Channel 1 GP-DMA Channel 2 GPDMAEXTPG2 D88h Bits 27–24 of the memory address for Extended Page Channel 2 GP-DMA Channel 3...
-
Page 272: Direct-Mapped Registers
GP Bus DMA Controller Table 14-2 GP-DMA Controller Registers—Memory-Mapped (Continued) MMCR Offset Register Mnemonic Address Function GP-DMA Channel 6 Next GPDMANXTADDL6 DA8h Address bits 0–15 of the next data buffer in Address Low memory used with Channel 6 (enhanced GP-DMA mode) GP-DMA Channel 6 Next GPDMANXTADDH6 DAAh... -
Page 273: Table 14-3 Gp-Dma Controller Registers—Direct-Mapped
GP Bus DMA Controller In addition to the registers used to control GP-DMA, there is a set of general-purpose registers. These registers are decoded in the same chip select region with the page registers. Table 14-3 GP-DMA Controller Registers—Direct-Mapped Register Mnemonic Address Function... -
Page 274: Operation
GP Bus DMA Controller Table 14-3 GP-DMA Controller Registers—Direct-Mapped (Continued) Register Mnemonic Address Function Master DMA Controller Reset MSTDMARST 00DAh GP-DMA controller reset Slave DMA Controller Reset SLDMARST 000Dh Master DMA Controller Temporary MSTDMATMP 00DAh Preserves PC/AT compatibility Slave DMA Controller Temporary SLDMATMP 000Dh Master DMA Mask Reset... -
Page 275: Gp-Dma Initiators
GP Bus DMA Controller Since the GP-DMA target is always SDRAM, the relevant address range must be currently mapped to be system SDRAM. If that portion of the address space is not mapped to SDRAM, erroneous operation will result. See Chapter 4, “System Address Mapping”, for more details on how to set up the system address mapping. -
Page 276: Gp-Dma Channel Mapping
GP Bus DMA Controller For a write transfer, the external I/O device asserts its request, waits for the acknowledge, and places the data on the GPD bus when the I/O command (GPIORD) is asserted. 14.5.1.1.3 External Memory-Mapped I/O Devices An external device on the GP bus can be mapped into memory address space. See Chapter 4, “System Address Mapping”, for more details. -
Page 277: Enhanced Gp-Dma Mode
GP Bus DMA Controller 14.5.2.2 Enhanced GP-DMA Mode Only channels 3, 5, 6, and 7 support enhanced GP-DMA mode. In enhanced GP-DMA mode: Each of these four channels can be configured to be either 8-bit or 16-bit channel. The other channels (0, 1, and 2) can still be used as normal 8-bit channels in conjunction with the enhanced GP-DMA mode channels. -
Page 278: Gp-Dma Transfer Modes
GP Bus DMA Controller Table 14-6 8-Bit GP-DMA Channel Address Generation GP-DMA Channel x Slave DMA Channel x Slave DMA Channel x Source Extended Page Registers Page Registers Memory Address Register Address A27–A24 A23–A16 A15–A0 Table 14-7 16-Bit GP-DMA Channel Address Generation GP-DMA Channel x Master DMA Channel x Master DMA Channel x... -
Page 279: Block Transfer Mode
GP Bus DMA Controller 14.5.4.3 Block Transfer Mode In block transfer mode , the GP-DMA initiator asserts GPDRQ and holds it active until acknowledged by the assertion of GPDACKx. The GP-DMA controller performs GP-DMA transfers until TC is reached, indicating the programmed number of transfers has been completed. -
Page 280: Automatic Initialization Control
GP Bus DMA Controller Figure 14-4 GP-DMA Write Transfer GPDRQx GPDACKx daddr[27:0] Address Valid GPAEN dmemw GPIORD, GPMEMRD GPD15–GPD0 Data Valid GPTC Figure 14-5 GP-DMA Verify Transfer GPDRQx GPDACKx daddr[27:0] Address Valid GPAEN dmemr GPIOWR, GPMEMWR dmemw GPIORD, GPMEMRD GPD15–GPD0 GPTC 14.5.4.5 Automatic Initialization Control... -
Page 281: Priority
GP Bus DMA Controller 14.5.4.6 Priority The GP-DMA controller offers two priority schemes for servicing multiple requests. After the recognition of any one channel for service, the other channels are prevented from generating DMA cycles until the current transfer has completed (i.e., the current channel’s DACKx has deasserted). -
Page 282: Bus Cycles
GP Bus DMA Controller The automatic initialization control mode cannot be used in conjunction with buffer chaining mode. 14.5.5 Bus Cycles Table 14-8 shows the four GP-DMA cycle types and the command strobes generated in each cycle. The GP bus command strobes GPMEMRD and GPMEMWR are asserted for memory-mapped I/O devices on this bus. -
Page 283: Gp-Dma Read With Cache Hit
GP Bus DMA Controller 14.5.5.2 GP-DMA Read with Cache Hit Figure 14-7 shows a read transfer with a cache hit (write-back cache). Figure 14-7 GP-DMA Read Transfer with Cache Hit (Write-Back Cache) GPDRQx GPDACKx daddr[27:0] Address Valid GPAEN GPDBUFOE eads hitm hold hlda... -
Page 284: Clocking Considerations
GP Bus DMA Controller 14.5.7 Clocking Considerations The GP-DMA controller can be programmed to operate at 4 MHz, 8 MHz, or 16 MHz. This option is specified in the GP-DMA Control (GPDMACTL) register (MMCR offset D80h). Note that these frequencies are derived from the 33-MHz clock. The exact frequency is an even fraction of the crystal (33.000-MHz or 33.333-MHz) being used in the system. -
Page 285: Preemptive Latency
GP Bus DMA Controller The operations of these buffers are described in detail in Chapter 11, “Write Buffer and Read Buffer”. 14.5.10.2 Preemptive Latency The following events could delay a GP-DMA acknowledgment. SDRAM refresh cycle (the acknowledgment is given; however, the transfer is delayed) PCI requests A higher priority GP-DMA request A cache write-back, if the GP-DMA target is in a dirty cache-line (the acknowledgment... -
Page 286: Configuring A 16-Bit Channel In Normal Gp-Dma Mode
GP Bus DMA Controller 14.6.1.2 Configuring a 16-Bit Channel in Normal GP-DMA Mode In normal GP-DMA mode, there are three 16-bit channels: 5, 6 and 7. Any external request can be mapped to one of these channels. The internal requests from the UART serial ports cannot be mapped to a 16-bit channel because they only support 8-bit data transfer. -
Page 287: Configuring A 16-Bit Channel In Enhanced Gp-Dma Mode
GP Bus DMA Controller 14.6.1.4 Configuring a 16-Bit Channel in Enhanced GP-DMA Mode In enhanced GP-DMA mode, Channel 3 can be configured to be a 16-bit channel. The 16-bit external devices can be mapped to channel 3, 5, 6, and 7. The following steps configure a 16-bit channel for an external request. - Page 288 GP Bus DMA Controller 14-22 Élan™SC520 Microcontroller User’s Manual...
-
Page 289: Chapter 15 Programmable Interrupt Controller
CHAPTER PROGRAMMABLE INTERRUPT CONTROLLER 15.1 OVERVIEW The ÉlanSC520 microcontroller’s programmable interrupt controller (PIC) consists of three industry-standard controllers, integrated with a highly programmable interrupt router. The programmable interrupt controller is configured so that two controllers are cascaded as slaves to a master controller that arbitrates interrupt requests from various sources to the Am5 86 CPU. -
Page 290: Block Diagram
Programmable Interrupt Controller 15.2 BLOCK DIAGRAM Figure 15-1 is a block diagram of the ÉlanSC520 microcontroller’s programmable interrupt controller showing interrupt sources and routing. The programmable interrupt controller consists of a system of three individual interrupt controllers (Master, Slave 1 and Slave 2), each of which has eight interrupt channels. Two of the interrupt channels on the Master controller are used to cascade the slave controllers. -
Page 291: Figure 15-1 Programmable Interrupt Controller (Pic) Block Diagram
Programmable Interrupt Controller Figure 15-1 Programmable Interrupt Controller (PIC) Block Diagram Élan™SC520 Microcontroller Programmable Interrupt Controller INTA INTB irq_p1 irq_p2 INTC INTD GPIRQ0 GPIRQ1 GPIRQ2 Slave 1 GPIRQ3 Controller GPIRQ4 irq_p3 IR0 (P3) GPIRQ5 irq_p4 IR1 (P4) GPIRQ6 irq_p5 s1_irq IR2 (P5) GPIRQ7 irq_p6... -
Page 292: Registers
Programmable Interrupt Controller 15.4 REGISTERS The programmable interrupt controller (PIC) is controlled by the registers listed in Table 15-2 and Table 15-3. Table 15-2 Programmable Interrupt Controller Registers—Memory-Mapped MMCR Offset Register Mnemonic Address Function PIO15–PIO0 Pin Function PIOPFS15_0 C20h PIO or interface function select: GPIRQ10– Select GPIRQ8 PIO31–PIO16 Pin Function... - Page 293 Programmable Interrupt Controller Table 15-2 Programmable Interrupt Controller Registers—Memory-Mapped (Continued) MMCR Offset Register Mnemonic Address Function UART 1 Interrupt Mapping UART1MAP D28h UART 1 interrupt mapping to any of 22 available interrupt channels or NMI UART 2 Interrupt Mapping UART2MAP D29h UART 2 interrupt mapping to any of 22 available interrupt channels or NMI...
-
Page 294: Table 15-3 Programmable Interrupt Controller Registers—Direct-Mapped
Programmable Interrupt Controller Table 15-2 Programmable Interrupt Controller Registers—Memory-Mapped (Continued) MMCR Offset Register Mnemonic Address Function GPIRQ7 Interrupt Mapping GP7IMAP D57h GPIRQ7 interrupt mapping to any of 22 available interrupt channels or NMI GPIRQ8 Interrupt Mapping GP8IMAP D58h GPIRQ8 interrupt mapping to any of 22 available interrupt channels or NMI GPIRQ9 Interrupt Mapping GP9IMAP... -
Page 295: Operation
Programmable Interrupt Controller Table 15-3 Programmable Interrupt Controller Registers—Direct-Mapped (Continued) Register Mnemonic I/O Address Function Master PIC Initialization MPICICW3 0021h Slave cascading channel select (MPICICW3) Control Word 3 (ICW3) S2PICICW3 0025h Slave 2 PIC Initialization S1PICICW3 00A1h Control Word 3 (ICW3) Slave 1 PIC Initialization Control Word 3 (ICW3) Master PIC Initialization... -
Page 296: Interrupt Sources
Programmable Interrupt Controller 4. The CPU reads the interrupt vector and services the interrupt corresponding to the vector read during the acknowledgment. 5. Before further interrupts for the same priority level can be serviced, an EOI (end-of- interrupt must be issued to the PIC to reset the In-Service (xISR) register bit of the currently active interrupt. -
Page 297: Figure 15-2 Interrupt Sources
Programmable Interrupt Controller 19 are generated from internal peripheral sources, including: – PCI host bridge/system arbiter (interrupt) – PCI host bridge (NMI) – SDRAM ECC single-bit error (interrupt) – SDRAM ECC multi-bit error (NMI) – Six timers (three GP timers and three PIT timers) –... -
Page 298: Interrupt Source Routing
Programmable Interrupt Controller 15.5.3 Interrupt Source Routing Figure 15-3 on page 15-11 shows the implementation of the interrupt router. None of the interrupt enable signals are shared across the interrupt channels. Each of the 32 hardware interrupt sources that come from peripherals (15 external and 17 internal) is fed into each of the 22 OR gates for the 22 interrupt channels. -
Page 299: Figure 15-3 Interrupt Source Routing
Programmable Interrupt Controller Figure 15-3 Interrupt Source Routing Channel 22 Router Channel 3 Router Channel 2 Router Channel 1 Router GPIRQ0 polarity0 src_enb0 GPIRQ10 polarity10 src_enb10 INTA polarity11 src_enb11 INTD irq_p22 polarity14 src_enb14 irq_p3 pit_tmr0_irq irq_p2 src_enb15 irq_p1 pit_timr1_irq src_enb16 pit_tmr2_irq src_enb17 gp_tmr0_irq... -
Page 300: Pc/At Compatibility
Programmable Interrupt Controller 15.5.3.2 PC/AT Compatibility For PC/AT-compatible systems, the microcontroller hardware does not automatically map legacy ISA interrupt signals to their respective Slave 1 and Master controllers. The user’s software must ensure that these interrupts are routed correctly to the appropriate PC/AT- compatible channels. -
Page 301: Disabling The Slave Controllers
Programmable Interrupt Controller and the internal ignne signal is subsequently deasserted. The interrupt request and ignne signal are also cleared by a system reset. 15.5.3.4 Disabling the Slave Controllers Each of the slave controllers can also be disabled via software, and interrupt requests can be easily routed to the associated interrupt channels of the Master controller. -
Page 302: Non-Maskable Interrupts And Routing
Programmable Interrupt Controller Since programmable inversion of the interrupt signal is available, the external device can generate an interrupt to the ÉlanSC520 microcontroller by either driving the interrupt request line Low and allowing a pullup resistor to generate the rising edge or by actively driving the line Low from its default High inactive state through a pullup resistor (as in PCI interrupt generation). -
Page 303: Figure 15-4 Nmi Routing
Programmable Interrupt Controller Figure 15-4 NMI Routing GPIRQ0 polarity0 nmi_enb0 GPIRQ10 polarity10 nmi_enb10 INTA polarity11 nmi_enb11 INTD polarity14 nmi_enb14 pit_tmr0_irq nmi_enb15 nmi_out pit_tmr1_irq NMI to CPU nmi_enb16 pit_tmr2_irq nmi_enb17 gp_tmr0_irq nmi_enb18 gp_tmr1_irq nmi_enb19 gp_tmr2_irq nmi_enb20 uart1_irq nmi_enb21 uart2_irq nmi_enb nmi_enb22 ssi_irq nmi_enb23 ecc_nmi... -
Page 304: Priority Types
Programmable Interrupt Controller 15.5.7 Priority Types Each individual interrupt controller prioritizes interrupt requests by their IR number, as shown in Figure 15-1 on page 15-3. This places IR0 as the highest priority and IR7 the lowest, which is the default ordering. In a cascaded environment, the full 22 priority level is as shown in Figure 15-1, with P1 being the highest and P22 the lowest priority. - Page 305 Programmable Interrupt Controller identifies which IR inputs are hooked up to slave controllers. For the slave controllers, it identifies the IR pin on the master to which that particular slave is connected. It is important to note that the ÉlanSC520 microcontroller’s PIC can be configured as a stand-alone master controller, one slave cascade (either Slave 1 or Slave 2), or cascading with both slave controllers.
-
Page 306: Pc/At Configuration
Programmable Interrupt Controller NMI (as indicated in Figure 15-1) polarity inversion of the interrupt sources if needed, different interrupt mode per channel, global interrupt mode enables, or master NMI enable. These registers are listed in Table 15-2 on page 15-4. It is recommended that EOIs be issued for all the channels prior to using the Set Interrupt- Enable Flag (STI) instruction. -
Page 307: Disabling The Slave Controllers
Programmable Interrupt Controller Although level-sensitive interrupt sharing generally works well, implementing edge- sensitive interrupt sharing is not recommended. 15.5.9.2 Disabling the Slave Controllers The ÉlanSC520 microcontroller’s PIC has the flexibility to allow removal of either or both the slave controllers logically from the cascade chain via software (see S2 and S5 bits in the Master PIC Initialization Control Word 3 (MPICICW3) register). -
Page 308: Initialization
Programmable Interrupt Controller 15.6 INITIALIZATION The programmable interrupt controller responds only to system reset. The Slave 1, Slave 2, and Master interrupt controllers are not affected by system reset. The interrupt controller direct-mapped registers, once configured, retain their values during a system reset. -
Page 309: Chapter 16 Programmable Interval Timer
Table 16-1 either disable or alter any other function that uses the same pin. Note: The CFG3 pinstrap associated with PITOUT2 is used for an AMD internal test mode. Do not pull this pin High during reset. -
Page 310: Registers
Programmable Interval Timer Figure 16-1 Programmable Interval Timer Block Diagram Élan™SC520 Microcontroller Programmable Interval Timer Always Enabled 1.1882 pit_tmr0_irq Channel 0 CLKTIMER pit_tmr1_irq gate 0 pit_tmr2_irq PITGATE2 Channel 1 gate 1 0061h[0] Channel 2 gate 2 Port 0061h[1] PITOUT2 0061h[5] Notes: Port B is addressed at 0061h in I/O space. -
Page 311: Operation
Programmable Interval Timer Table 16-3 Programmable Interval Timer Configuration Registers—Direct-Mapped Register Mnemonic I/O Address Function PIT Channel 0 Count PIT0CNT 0040h Current count value for Channel 0 PIT Channel 1 Count PIT1CNT 0041h Current count value for Channel 1 PIT Channel 2 Count PIT2CNT 0042h Current count value for Channel 2... -
Page 312: Pit Channel 2
Programmable Interval Timer 16.5.3 PIT Channel 2 The gate line for PIT Channel 2 is controlled by the PIT_GATE2 bit in the System Control Port B (SYSCTLB) register (Port 0061h) or the external input pin PITGATE2. PITGATE2 is a multiplexed pin; if it is disabled, the gate line is controlled only by the PIT_GATE2 bit in the System Control Port B (SYSCTLB) register. -
Page 313: Mode 2: Rate Generator
Programmable Interval Timer 16.5.4.3 Mode 2: Rate Generator When programmed in rate generator mode, the counters operate as divide by n counters, where n is the initial count. 1. The output signal starts off High until the initial count is decremented to one. 2. -
Page 314: Clocking Considerations
Programmable Interval Timer In this mode, the counter output behaves just as in mode 4, except for the triggering mechanism. This mode is supported on PIT Channel 2 only. 16.5.5 Clocking Considerations The PIT clock source can be either the derived 1.1882-MHz PIT clock or an external pin. This is configured in the CLK_PIN_DIR bit in the Clock Select (CLKSEL) register (MMCR offset C26h). -
Page 315: Initialization
Programmable Interval Timer Driving an external 1.19318-MHz clock on the CLKTIMER pin—A system designer can choose to supply an external clock source frequency of 1.19318 MHz on the CLKTIMER pin. This pin must be specifically configured for this functionality by the system boot code during the system boot process, prior to configuring the PIT. - Page 316 Programmable Interval Timer 16-8 Élan™SC520 Microcontroller User’s Manual...
-
Page 317: Chapter 17 General-Purpose Timers
CHAPTER GENERAL-PURPOSE TIMERS 17.1 OVERVIEW The general-purpose (GP) timers are intended for most generic timing or counting applications, such as generating periodic interrupts and measuring or counting external events. Features of the general-purpose timers include: Three 16-bit timers Two-stage cascading of timers, to allow a maximum of two 32-bit timer/counter elements Clock source from the system clock (33 MHz), an external pin, or a derived prescale clock. -
Page 318: Registers
General-Purpose Timers Figure 17-1 General-Purpose Timers Block Diagram Élan™SC520 Microcontroller General-Purpose Timers TMRIN0 TMROUT0 33 MHz GP Timer 0 TMRIN1 TMROUT1 33 MHz GP Timer 1 gpt_tmr0_irq gpt_tmr1_irq clk_pre gpt_tmr2_irq GP Timer 2 33 MHz 17.4 REGISTERS The general-purpose timers include the memory-mapped registers listed in Table 17-2. Table 17-2 General-Purpose Timer Registers—Memory-Mapped MMCR... -
Page 319: Operation
General-Purpose Timers Table 17-2 General-Purpose Timer Registers—Memory-Mapped (Continued) MMCR Offset Register Mnemonic Address Function GP Timer 1 Maxcount GPTMR1MAXC C7Eh Maxcount value A to compare with current count Compare A GP Timer 1 Maxcount GPTMR1MAXC C80h Maxcount value B, used in the alternate mode Compare B GP Timer 2 Mode/Control GPTMR2CTL... -
Page 320: Gp Timer 2
General-Purpose Timers 17.5.2 GP Timer 2 GP Timer 2 is a 16-bit timer that is not connected to any external pins. GP Timer 2 can be used by software to generate interrupts, or it can be polled for real-time coding and time- delay applications. -
Page 321: Configuration Information
General-Purpose Timers 17.5.4 Configuration Information The GP Timer x Count (GPTMRxCNT) registers contain the current value of a timer. These registers can be read or written at any time, regardless of whether the corresponding timer is running. The timer increments the value of the corresponding GP Timer x Count (GPTMRxCNT) register each time a timer event occurs. -
Page 322: External Clock
General-Purpose Timers 17.5.5.2 External Clock Separate external clock input pins, TMRIN0 and TMRIN1, are provided to each of the following two timers: GP Timer 0 and GP Timer 1, respectively. Table 17-4 specifies the external clock source frequency range for the TMRIN0 and TMRIN1 inputs for the general- purpose timers. - Page 323 General-Purpose Timers To test for rollover, software must read both timers two times in succession, reading the least significant timer value (i.e., GP Timer 2), followed by the most significant timer value. A very important assumption must be made that software is able to perform these four 16- bit reads in less one tick of the “most significant”...
-
Page 324: Initialization
General-Purpose Timers In this example, the second value read for GP Timer 2 (14h) is less than the first value (7997h), and both values read for GP Timer 0 are 0. So this falls under case 1, and the correct 32-bit value of the cascaded timer is: 32764 ms + (7997h * 121.2 ns) = 32767.8 ms = 32.7678 s 17.5.7.2.5 Example 2... -
Page 325: Chapter 18 Software Timer
CHAPTER SOFTWARE TIMER 18.1 OVERVIEW The software timer is intended to provide a millisecond timebase with microsecond resolution. Ideal applications for this function include providing a system wide software timebase, code profiling, and precise measurement of the time between events. Features of the software timer include: One 16-bit millisecond counter that increments with a period of one millisecond. -
Page 326: Registers
Software Timer 18.3 REGISTERS The software timer includes the registers listed in Table 18-1. Table 18-1 Software Timer Configuration Registers—Memory-Mapped MMCR Offset Register Mnemonic Address Function Software Timer Millisecond SWTMRMILLI C60h Current 10-bit count value (milliseconds) Count Software Timer Microsecond SWTMRMICRO C62h Current latched 16-bit count value... -
Page 327: Configuration Information
Software Timer For example, here is some example code that can be used to maintain a system timebase: typedef unsigned long int DWORD; // an unsigned 32-bit value typedef unsigned short int WORD: // an unsigned 16-bit value static volatile WORD* SWTMRMILLI = 0xA0000200; // volatile is essential static volatile WORD* SWTMRMICRO = 0xA0000202;... - Page 328 Software Timer 18-4 Élan™SC520 Microcontroller User’s Manual...
-
Page 329: Chapter 19 Watchdog Timer
CHAPTER WATCHDOG TIMER 19.1 OVERVIEW The ÉlanSC520 microcontroller includes an integrated watchdog timer (WDT). Features of the watchdog timer include: Distinct keyed write sequences are required to open the Watchdog Timer Control (WDTMRCTL) register for reconfiguration and to reset the current count. Supports up to a 30-second time-out period with a 33-MHz CPU clock Programmable to generate either a system reset or an interrupt request (maskable or non-maskable) on the first time-out. -
Page 330: Registers
Watchdog Timer Figure 19-1 Watchdog Timer Block Diagram Élan™SC520 Microcontroller Watchdog Timer Internal GP bus ice_mode System Configuration Configuration Registers Registers Detection Logic wdt_rst Reset cnt_reset Time-Out 33-MHz Clock Clock Counter wdt_irq 19.3 REGISTERS The watchdog timer is controlled by the memory-mapped registers listed in Table 19-1. Table 19-1 Watchdog Timer Registers—Memory-Mapped MMCR... -
Page 331: Operation
Watchdog Timer Table 19-1 Watchdog Timer Registers—Memory-Mapped (Continued) MMCR Offset Register Mnemonic Address Function Watchdog Timer Count High WDTMRCNTH CB4h Bits 30–16 of the WDT current count Watchdog Timer Interrupt WDTMAP D42h WDT interrupt mapping Mapping Reset Status RESSTA D74h Reset source status: watchdog timer time-out 19.4 OPERATION... -
Page 332: Interrupt Request Generation
Watchdog Timer Each individual write of these keyed sequences is not required to be written back-to-back as an atomic sequence. Any number of processor cycles, including memory and I/O reads and writes, can be inserted between the key and the writing of data, as long as they do not access the Watchdog Timer Control (WDTMRCTL) register. -
Page 333: Interrupts
Watchdog Timer 19.4.2 Interrupts An interrupt is asserted upon time-out if the watchdog timer interrupt condition is configured accordingly in the Watchdog Timer Control (WDTMRCTL) register. If the watchdog timer is configured for interrupts, the IRQ_FLG bit in the Watchdog Timer Control (WDTMRCTL) register is set when the interrupt is generated. -
Page 334: Initialization
Watchdog Timer Although both the Watchdog Timer Count High and Low registers can be read from a single 32-bit CPU instruction, 32-bit accesses are split into two 16-bit accesses. If it is necessary to read an accurate 32-bit value from the Watchdog Timer Counter, see Chapter 17, “General-Purpose Timers”, for suggestions on dealing with this issue. -
Page 335: Chapter 20 Real-Time Clock
CHAPTER REAL-TIME CLOCK 20.1 OVERVIEW The real-time clock (RTC) included on the ÉlanSC520 microcontroller is compatible with the MC146818A device used in PC/AT systems. The RTC consists of a time-of-day clock with alarm and a 100-year calendar. The clock/calendar has a programmable periodic interrupt and 114 bytes of static user RAM. -
Page 336: Figure 20-1 Real-Time Clock Block Diagram
Real-Time Clock Figure 20-2 on page 20-3 shows a block diagram of the RTC voltage monitor. The ÉlanSC520 microcontroller’s RTC voltage monitor is designed to signal the RTC core when the backup battery is not installed or is low. Additionally, the voltage monitor circuit signals the RTC core when the rest of the system is being powered down. -
Page 337: System Design
Real-Time Clock Figure 20-2 RTC Voltage Monitor Block Diagram 2.0 V Bandgap Amplifier Voltage RTC Reset Generator Shot – BBATSEN PWRGOOD Internal RTC Power-Down Flip- Flop 32 kHz 20.3 SYSTEM DESIGN 20.3.1 Backup Battery Considerations The behavior of the RTC when the primary power supply is turned off depends on whether or not an external backup battery is included in the system design. -
Page 338: System Without An External Backup Battery
Real-Time Clock Figure 20-3 Circuit with Backup Battery VCC_RTC 10 Ω BATT (3.3 V max) VCC_RTC BBATSEN Élan™SC520 Microcontroller Software can read the RTC_VRT bit in the RTC Status D (RTCSTAD) register (RTC index 0Dh) at system boot time to determine whether or not the RTC time, date, and user RAM are still valid since the last boot. -
Page 339: Selecting And Interfacing A 32.768-Khz Crystal
Real-Time Clock In this configuration, the RTC is reset after power-up, but is not reset by subsequent PWRGOOD assertions. The RTC is reset after a power-up—When power has been removed from the RTC, the contents are no longer valid. In this case, the RTC is reset. RTC is not reset—When a reset switch tied to PWRGOOD is pressed (V remains High) and PWRGOOD reasserts with BBATSEN High, the RTC is not reset. -
Page 340: Registers
Real-Time Clock microcontroller’s programmable interrupt inputs and program the interrupt steering logic to route the request to interrupt priority P8. Disabling the internal RTC does not disable or reset the core in any way. See “Disabling Internal Peripherals” on page 3-21 for more information. 20.4 REGISTERS The RTC is controlled by the configuration registers listed in Table 20-1, Table 20-2, and... -
Page 341: Operation
Real-Time Clock Table 20-3 Real-Time Clock Registers—RTC Indexed (Continued) Register Mnemonic I/O Address Function RTC Control A RTCCTLA 70h/71h Update status, divider chain control, and Index 0Ah periodic interrupt rate selection RTC Control B RTCCTLB 70h/71h Update override (SET); periodic interrupt, alarm Index 0Bh interrupt, and update-ended interrupt enables;... -
Page 342: Programming The Date And Time
Real-Time Clock register (RTC index 05h). When the 12-hour format is selected, the AM_PM bit and ALM_AM_PM bit in these two respective registers represent PM when they are a 1. 20.5.1.2 Programming the Date and Time A program can initialize the time, calendar, and alarm by writing to appropriate RAM location. Before initializing the internal registers, set the SET bit in the RTC Control B (RTCCTLB) register (RTC index 0Bh) to prevent time and calendar updates from occurring. -
Page 343: Using The Alarm Function
(RTCCURYR) register and the upper portion in the century CMOS memory location. This operation is handled properly by PC-style BIOS software that supports the ÉlanSC520 microcontroller. For information on what BIOS products are supported, see the AMD web site. For embedded systems, a simple set of software functions supports four-digit years with the RTC. -
Page 344: Software Considerations
Real-Time Clock 20.5.4 Software Considerations 20.5.4.1 Initializing the RTC Divider Chain An RTC reset event does not initialize either the divider chain or the Internal Oscillator Control (OSC_CTL) bit field in the RTC Control A (RTCCTLA) register (RTC index 0Ah). The internal RTC divider chain can be reset by writing a value of 110b or 111b to the OSC_CTL field. -
Page 345: Rtc Reset
Real-Time Clock 3. Initialize the ten time, calendar, and alarm registers in either binary or BCD data format. 4. Specify the format in the data mode via the DATE_MODE bit in the RTC Control B (RTCCTLB) register. All ten time, calendar, and alarm registers must use the same data mode, either binary or BCD. - Page 346 Real-Time Clock 20-12 Élan™SC520 Microcontroller User’s Manual...
-
Page 347: Chapter 21 Uart Serial Ports
CHAPTER UART SERIAL PORTS 21.1 OVERVIEW The ÉlanSC520 microcontroller includes two industry-standard 16550-compatible UARTs, both capable of running all existing 16450 and 16550 software. The UARTs power up in 16450-compatible UART mode (also called character mode or non-FIFO mode). Each UART can be switched between the 16550-compatible mode (also called FIFO mode ) and 16450-compatible mode under software control. -
Page 348: System Design
UART Serial Ports Figure 21-1 UART Block Diagram Élan™SC520 Microcontroller UART Transmitter SOUTx TX Hold Register TX shift register TX FIFO Prescaler 18.432 MHz Baud From Generator 1.8432 MHz clocks clk_uart Configuration (18.432 MHz) Registers Receiver GP Bus SINx RX FIFO RX shift register RX Buffer Register To/from DMA... -
Page 349: Registers
UART Serial Ports Each UART supports loopback mode. In this mode, the UART’s transmitter output is internally connected with the receiver input. It is useful for testing the operation of a local UART channel without affecting the states of the UART output pins and independently of the state of the UART input pins. -
Page 350: Table 21-4 Uart Registers—Direct-Mapped
UART Serial Ports Table 21-3 UART Registers—Memory-Mapped (Continued) MMCR Offset Register Mnemonic Address Function UART 2 Interrupt Mapping UART2MAP D29h UART 2 interrupt mapping Table 21-4 UART Registers—Direct-Mapped Register Mnemonic I/O Address Function UART 1 Transmit Holding UART1THR 02F8h Byte to be transmitted UART 2 Transmit Holding UART2THR 03F8h... -
Page 351: Operation
UART Serial Ports 21.5 OPERATION Each UART performs: Serial-to-parallel conversion on data characters received from a modem or a peripheral device Parallel-to-serial conversion on those data characters written by the CPU or DMA controller During communication, data is transmitted and received in frames . The frame format, as well as the baud rate, must be the same on the transmitter and receiver. -
Page 352: Data Transmission
UART Serial Ports For each UART, six handshaking signals are provided: DTRx (Data Terminal Ready) output—When the signal is Low, it informs the modem set that the UART is ready to establish a communications link. The DTRx output signal can be asserted and deasserted by the UART x Modem Control (UARTxMCR) register. -
Page 353: Compatible Uart Mode
UART Serial Ports The Transmitter Empty (TEMT) bit in the UART x Line Status (UARTxLSR) register is set in this mode if both the UART x Transmit Holding (UARTxTHR) register and internal transmitter shift register are empty. An application could write two bytes consecutively to the UART x Transmit Holding (UARTxTHR) register without checking THRE if TEMT is detected as set. -
Page 354: Error Handling
UART Serial Ports 16550-compatible mode, the Overrun Error (OE) bit is set if a new character is completely received into the shift register when the FIFO is already 100% full. Data in the FIFO is not overwritten by this overrun. However, the data in the shift register is lost. -
Page 355: Configuration Information
UART Serial Ports If receiver line status interrupts are enabled, any of the OE, PE, FE, or BI conditions trigger an interrupt. Note that the ERR_IN_FIFO cannot directly generate an interrupt. 21.5.4 Configuration Information 21.5.4.1 Baud Rate To generate the baud rate of the transfer, the UART clock is divided by a divisor value chosen by the programmer. -
Page 356: Dma Interface
UART Serial Ports When in 16550-compatible mode, the receiver and transmitter FIFO buffers can be cleared by the RF_CLR and TF_CLR bits in the UART x FIFO Control (UARTxFCR) register, respectively. The receiver FIFO trigger level can be programmed by RFRT field of the UART x FIFO Control (UARTxFCR) register. -
Page 357: Table 21-6 Uart Interrupt Programming Summary
UART Serial Ports Table 21-6 provides a summary of UART interrupt sources for both DMA and serial port interrupts. Interrupts generated by the UARTs are cleared in a variety of ways, depending on the source event. For details about clearing a particular event, see the event’s status bit description in the Élan™SC520 Microcontroller Register Set Manual , order #22005. -
Page 358: Serial Port Interrupts
UART Serial Ports 21.5.7.1 Serial Port Interrupts Each serial port supports the standard UART interrupts. These include: Received data available or FIFO trigger level reached Transmit Holding register empty (THRE) Modem status change (including clear-to-send, data-set-ready, ring indicator, data carrier detect) Line Status register receiver interrupts (including overrun error, parity error, framing error and break interrupt) In 16550-compatible mode, the FIFO time-out interrupt is also enabled when the received... -
Page 359: Interrupt Disable
UART Serial Ports 21.5.7.3 Interrupt Disable Each UART interrupt request can be disabled (gated low) prior to the programmable interrupt controller by clearing to 0 the OUT2 bit in the UART x Modem Control (UARTxMCR) register. Note that setting the LOOP bit in the MCR also disables the UART interrupt request. Therefore, interrupts are not propagated to the PIC while in loopback mode. - Page 360 UART Serial Ports 21-14 Élan™SC520 Microcontroller User’s Manual...
-
Page 361: Chapter 22 Synchronous Serial Interface
CHAPTER SYNCHRONOUS SERIAL INTERFACE 22.1 OVERVIEW The ÉlanSC520 microcontroller includes a synchronous serial interface (SSI). The SSI provides efficient full-duplex and half-duplex, bidirectional communication to peripheral devices. The interface can be used to configure and monitor the status of devices such as ISDN transceivers, EEPROMs, SLACs, audio CODECs, LCD drivers, DSPs, etc. -
Page 362: Registers
Synchronous Serial Interface Figure 22-1 SSI Block Diagram Élan™SC520 Microcontroller GPIRQx Programmable Interrupt PIOx Controller (PIC) Block SSI_DO ssi_irq shift register SSI Transmit Register SSI Control Register SSI Status Register Internal GP Bus SSI Clock SSI Command Register 33-MHz Generation Clock tri_do SSI_CLK... -
Page 363: Operation
Synchronous Serial Interface 22.5 OPERATION Synchronous serial interface describes a port that can be implemented in several ways. Typically, the microcontroller port is called the master and one or more peripheral device ports are slaves . The master port (ÉlanSC520 microcontroller) configures a slave by serial transmission of slave commands, addresses, and data. -
Page 364: Figure 22-2 Ssi Four-Pin Interface
Synchronous Serial Interface Figure 22-2 SSI Four-Pin Interface Four-Pin Slave Synchronous Serial Interface SSI_CLK Clock in SSI_DO Data in Élan™SC520 Microcontroller SSI_DI Data out PIOx Enable PIOx Four-Pin Slave Synchronous Serial Interface Clock in Data in Data out Enable Figure 22-3 SSI Simultaneous Transmit and Receive PIOx SSI_CLK... -
Page 365: Configuration Information
Synchronous Serial Interface 22.5.2 Configuration Information The MSBF_ENB, CLK_INV_ENB, and PHS_INV_ENB bits in the SSI Control (SSICTL) register (MMCR offset CD0h) define the order of the bits, the clock idle state, and the clock edge upon which data is transmitted/received (phase). The SSI should be configured to assert SSI_DO on the same clock edge that the slave uses to transmit. -
Page 366: Bit Read Cycle
Synchronous Serial Interface Figure 22-6 SSI Clock Phase and Clock Idle State: Effects on Data PIOx SSI_DI SSI_DO SSI_CLK PHS_INV_ENB=0 CLK_INV_ENB=0 SSI_CLK PHS_INV_ENB=0 CLK_INV_ENB=1 SSI_CLK PHS_INV_ENB=1 CLK_INV_ENB=0 SSI_CLK PHS_INV_ENB=1 CLK_INV_ENB=1 Transaction complete, Write three-state SSI_DO Read 22.5.3.1 4-Bit Read Cycle A 4-bit operation can be simulated by ignoring four of the eight bits transferred. -
Page 367: Burst, 16-Bit, And 32-Bit Cycles
Synchronous Serial Interface 22.5.3.2 Burst, 16-Bit, and 32-Bit Cycles Burst,16-bit, and 32-bit exchanges can be simulated by multiple 8-bit transactions. There is at least one CPU clock period idle time between transactions. Additional delay between each transaction is determined by software. Figure 22-8 shows an example of a 16-bit operation. -
Page 368: Software Considerations
Synchronous Serial Interface Figure 22-9 SSI Timing: TC_INT and BSY_STA Bits Write 1 to TC_INT Write 1 to TC_INT Write 1 to TC_INT TC_INT=0 TC_INT=0 TC_INT=0 Write SSI command Write SSI command BSY=0 BSY=0 BSY=0 BSY=1 TC_INT=1 BSY=1 TC_INT=1 TC_INT=1 SSI_CLK PHS_INV_ENB=0 CLK_INV_ENB=0... -
Page 369: Chapter 23 Programmable Input/Output
CHAPTER PROGRAMMABLE INPUT/OUTPUT 23.1 OVERVIEW The ÉlanSC520 microcontroller supports 32 programmable I/O signals (PIOs) that can be used on the system board to monitor signals or control devices that are not handled by the other functions in the ÉlanSC520 microcontroller. These signals can be programmed to be inputs or to be driven out High or Low as outputs. -
Page 370: System Design
Programmable Input/Output Figure 23-1 PIO Signal Block Diagram Élan™SC520 Microcontroller Interface Function Gate Data Register PIOx Direction Register Pin Function Select Register Interface Function PIO Set Register Logic PIO Clear Register Notes: A PIO has either a pullup or pulldown resistor, but not both. 23.3 SYSTEM DESIGN Because most of the PIOs share pins with other functions, designers are usually constrained... -
Page 371: Table 23-1 Pio Signals Shared With Other Interfaces
Programmable Input/Output After the assertion of PWRGOOD, all PIO signals default to be inputs with pullup or pulldown resistive termination, as shown in Table 23-1. The signals must be programmed before using them as outputs or the alternate interface function. See “Initialization” on page 23-6. Table 23-1 PIO Signals Shared with Other Interfaces Pin Configuration... -
Page 372: Registers
Programmable Input/Output 23.4 REGISTERS A summary listing of the memory-mapped configuration registers used to control the PIO signals is shown in Table 23-2. Table 23-2 PIO Registers—Memory-Mapped MMCR Offset Register Mnemonic Address Function PIO15–PIO0 Pin Function PIOPFS15_0 C20h PIO15–PIO0 or interface function select: Select GPIRQ10–GPIRQ8, GPDACK3–GPDACK0, GPDRQ3–GPDRQ3, GPTC, GPAEN, GPRDY,... -
Page 373: Configuration Information
Programmable Input/Output 23.5.1 Configuration Information 23.5.1.1 PIO Pins and Simple Input PIO pins are selected for simple input when the system powers up. The input value of the pins can be read using the PIOx Data registers. Only two actions disable simple input on the PIO pin: Selecting the pin’s interface function Setting the PIO’s PIOx_DIR bit in the PIOx Direction register to configure the PIO as an output... -
Page 374: Initialization
Programmable Input/Output Note that although the registers to set, clear, and read the PIO pins can be accessed with 32-bit instructions, 32-bit accesses are split into two 16-bit accesses. This means, for example, that it is impossible to simultaneously set PIO5 and PIO18. Similarly, it is impossible to sample the state of PIO12 and PIO23 simultaneously;... -
Page 375: Chapter 24 System Test And Debugging
CHAPTER SYSTEM TEST AND DEBUGGING 24.1 OVERVIEW This chapter describes various system-level test features included in the ÉlanSC520 microcontroller. These features are useful for debugging hardware and software in an ÉlanSC520 microcontroller-based system. Some of the system-level debugging features are useful in conjunction with the AMDebug interface for software debugging. This functionality is described in Chapter 26, “AMDebug™... -
Page 376: Loading
System Test and Debugging Table 24-1 System Test and Debugging Signals Shared with Other Interfaces Default Signal Alternate Function Control Bit Register CF_ROM_GPCS WBMSTR0 WB_TST_ENB SDRAM Control (DRCCTL) register (MMCR offset 10h) DATASTRB WBMSTR1 CF_DRAM WBMSTR2 24.2.1 Loading When a logic analyzer is connected to the ÉlanSC520 microcontroller pins, it presents an additional load that must be taken into consideration on critical buses, such as the SDRAM interface. -
Page 377: Operation
System Test and Debugging Table 24-2 System Test and Debugging Registers—Memory-Mapped (Continued) MMCR Offset Register Mnemonic Address Function Reset Status RESSTA D74h Reset source status: SCP reset, AMDebug hard reset detect, AMDebug system reset, watchdog timer time-out, CPU shutdown (soft reset), PRGRESET pin, and PWRGOOD pin 24.4 OPERATION... -
Page 378: Using The System Test Mode Interface
System Test and Debugging When High, this signal indicates that either a GP-DMA initiator or an external PCI bus master contributed to the current SDRAM write cycle (the CPU may also have contributed). A Low indicates that the CPU is the only master that contributed to this write cycle. 24.4.1.1.2 DATASTRB The DATASTRB signal is useful for the external in-circuit emulation system to latch data... -
Page 379: Sdram Read Cycle In System Test Mode
System Test and Debugging Figure 24-1 System Test Mode Timing During a SDRAM Write Cycle (Page Hit) CLKMEMIN BA1–BA0 MA12–MA0 Command MD31–MD0 DATASTRB CF_DRAM Valid on this clock edge 24.4.1.4 SDRAM Read Cycle in System Test Mode Figure 24-2 illustrates the timing of a page miss SDRAM read cycle (with a CAS Latency of 2) during system test mode. -
Page 380: Tracing Transactions On The Gp Bus Interface
System Test and Debugging configuration of the ROM array must be known, because the ROM data bus can be ± connected to either the SDRAM interface data pins (MD31 MD0), or the GP bus interface ± data pins (GPD15 GP0). Also, the timing of the ROM cycle will vary, depending on the device that has been connected to each of the ROM chip selects and the programming of the ROM controller configuration registers. -
Page 381: Write Buffer Test Mode
System Test and Debugging 24.4.2 Write Buffer Test Mode Write buffer test mode identifies which bus owners (Am5 86 CPU, PCI bus master, or GP- DMA controller) have contributed to the current SDRAM write cycle, and which bus owner is requesting the current SDRAM read cycle. The ÉlanSC520 microcontroller implements a 32-rank First-In-First-Out (FIFO) write buffer for improved memory performance. -
Page 382: Sdram Write Cycle In Write Buffer Test Mode
System Test and Debugging 24.4.2.2 SDRAM Write Cycle in Write Buffer Test Mode ± Table 24-3 describes the WBMSTR2 WBMSTR0 decoding during an SDRAM write operation. ± Table 24-3 WBMSTR2 WBMSTR0 Pin Definition During Write Buffer Write Cycles ± WBMSTR2 WBMSTR0 Pins GP-DMA 86 CPU... -
Page 383: Figure 24-4 Write Buffer Test Mode Timing During A Sdram Read Cycle (Page Miss)
System Test and Debugging ± In this case, the WBMSTR2 WBMSTR0 pins represent which bus initiators contributed to the rank of the write buffer that is being written to SDRAM. ± Table 24-4 WBMSTR2 WBMSTR0 Pin Definition During SDRAM Read Cycles ±... -
Page 384: Microcontroller
System Test and Debugging 24.4.3 Other Debugging Features on the Élan™SC520 Microcontroller 24.4.3.1 Nonconcurrent Arbitration Mode The ÉlanSC520 microcontroller’s system arbitration is comprised of an Am5 86 CPU bus arbiter and a PCI bus arbiter, which enables concurrent mode operation. In the concurrent arbitration mode, transactions on the Am5 86 CPU bus and the PCI bus can occur simultaneously. -
Page 385: Software Considerations
System Test and Debugging The ÉlanSC520 microcontroller’s address decode logic allows notification of violations of write-protected memory regions, which is useful when debugging a software task that is illegally attempting to modify a portion of memory modified as write-protected. See Chapter 4, “System Address Mapping”, for further details on enabling this feature. -
Page 386: Initialization
System Test and Debugging The Am5 86 CPU’s internal cache can greatly affect system performance. – When disabled, all Am5 86 CPU operations require an external bus cycle, which yields significantly less bus bandwidth for PCI bus masters and GP-DMA initiators. –... -
Page 387: Chapter 25 Boundary Scan Test Interface
CHAPTER BOUNDARY SCAN TEST INTERFACE 25.1 OVERVIEW The ÉlanSC520 microcontroller provides test and debug features compliant with IEEE Standard Test Access Port (TAP) and Joint Test Action Group (JTAG) (IEEE Std 1149.1- 1990). The test logic is provided to test and ensure that: Components function correctly Interconnections between various components are correct Various components interact correctly on the printed circuit board... -
Page 388: Registers
Device Identification A 32-bit register that contains AMD’s ID code for the ÉlanSC520 microcontroller. Serial Debug Port Data SDPD A 38 bit register that serves as a command/status/data interface with the 86 CPU processor. -
Page 389: Instruction Register
Boundary Scan Test Interface 25.4.1 Instruction Register The Instruction register is a 4-bit register that allows instructions to be serially shifted into the device. The instruction determines the test to be executed and the data register to be accessed. The least significant bit is nearest the JTAG_TDO output. When the test access port (TAP) controller is reset, the Instruction register is loaded with the default instruction IDCODE. -
Page 390: Configuration Information
Boundary Scan Test Interface When the TAP controller is in the Update-DR state, the SAMPLE/PRELOAD instruction preloads data to the device pins to be driven to the board by executing the EXTEST instruction. Data is preloaded to the pins from the Boundary Scan register on the falling edge of JTAG_TCK. -
Page 391: Bypass Path
Boundary Scan Test Interface 25.4.2.2 Bypass Path This path bypasses the test logic on the microcontroller by reducing the shift length of the device to one bit. Commands can still be entered in the Instruction register during this operation. 25.4.2.3 Main Data Scan Path Table 25-3 shows the main data scan path. - Page 392 Boundary Scan Test Interface Table 25-3 Main Data Scan Path (Continued) Pad Name Scan Type Boundary Scan Order MD19 Bidirectional 42, 43 MD18 Bidirectional 44, 45 MD17 Bidirectional 46, 47 MD16 Bidirectional 48, 49 MD15 Bidirectional 50, 51 MD14 Bidirectional 52, 53 MD13 Bidirectional...
- Page 393 Boundary Scan Test Interface Table 25-3 Main Data Scan Path (Continued) Pad Name Scan Type Boundary Scan Order SWEB Output SWEA Output Control SDQM3 Output SDQM2 Output SDQM1 Output SDQM0 Output Control BOOTCS Output Control ROMRD Output Control FLASHWR Output Control ROMBUFOE Output...
- Page 394 Boundary Scan Test Interface Table 25-3 Main Data Scan Path (Continued) Pad Name Scan Type Boundary Scan Order Bidirectional 175, 176 Bidirectional 177, 178 Bidirectional 179, 180 Bidirectional 181, 182 Bidirectional 183, 184 Bidirectional 185, 186 Bidirectional 187, 188 Bidirectional 189, 190 Bidirectional 191, 192...
- Page 395 Boundary Scan Test Interface Table 25-3 Main Data Scan Path (Continued) Pad Name Scan Type Boundary Scan Order REQ1 Input REQ0 Input Control GNT4 Output Control GNT3 Output Control GNT2 Output Control GNT1 Output Control GNT0 Output Control GPA25 Bidirectional 251, 252 GPA24 Bidirectional...
- Page 396 Boundary Scan Test Interface Table 25-3 Main Data Scan Path (Continued) Pad Name Scan Type Boundary Scan Order GPD13 Bidirectional 293, 294 GPD12 Bidirectional 295, 296 GPD11 Bidirectional 297, 298 GPD10 Bidirectional 299, 300 GPD9 Bidirectional 301, 302 GPD8 Bidirectional 303, 304 Control GPD7...
- Page 397 Boundary Scan Test Interface Table 25-3 Main Data Scan Path (Continued) Pad Name Scan Type Boundary Scan Order PIO19 Bidirectional 357, 358 Control PIO18 Bidirectional 360, 361 Control PIO17 Bidirectional 363, 364 Control PIO16 Bidirectional 366, 367 Control PIO15 Bidirectional 369, 370 Control PIO14...
- Page 398 Boundary Scan Test Interface Table 25-3 Main Data Scan Path (Continued) Pad Name Scan Type Boundary Scan Order Control RTS1 Output CTS1 Input DSR1 Input Control DTR1 Output DCD1 Input RIN1 Input Control SOUT2 Output SIN2 Input Control RTS2 Output Control PIO28 Bidirectional...
-
Page 399: Serial Debug Port Data Register
Boundary Scan Test Interface Table 25-3 Main Data Scan Path (Continued) Pad Name Scan Type Boundary Scan Order DATASTRB Bidirectional 467, 468 Control CPUACT Bidirectional 470, 471 Control PITOUT2 Bidirectional 473, 474 Control PITGATE2 Bidirectional 476, 477 Control TMRIN1 Bidirectional 479, 480 Control TMRIN0... -
Page 400: Test Access Port (Tap) Controller
Boundary Scan Test Interface value of the MINORSTEP field of the ÉlanSC520 Microcontroller Revision ID (REVID) register (MMCR offset 00h). Figure 25-3 Device Identification Register Format 28 27 Version Part Number Manufacturer Identity Name Function 31–28 VERSION Value of the MINORSTEP field of the ÉlanSC520 Microcontroller Revision ID (REVID) register 27–0... -
Page 401: Tap Controller States
Boundary Scan Test Interface Figure 25-4 Test Access Port Controller State Diagram JTAG_TRST Test-Logic-Reset Run-Test/Idle Select-DR-Scan Select-IR-Scan Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-DR Pause-IR Exit2-DR Exit2-IR Update-DR Update-IR 25.4.3.1 TAP Controller States 25.4.3.1.1 Test-Logic-Reset State In this state, the test logic is disabled so that normal operation of the device can continue unhindered. - Page 402 Boundary Scan Test Interface all test data registers retain their previous state. When JTAG_TMS is High and a rising edge is applied to JTAG_TCK, the controller moves to the Select-DR state. 25.4.3.1.3 Select-Data Register (DR)-Scan State This is a temporary controller state. The test data register selected by the current instruction retains its previous state.
-
Page 403: When The Tap Controller Is In This State And A Rising Edge Is Applied To Jtag_Tck, The
Boundary Scan Test Interface 25.4.3.1.8 Exit2-DR State This is a temporary state. While in this state, if JTAG_TMS is held High, a rising edge applied to JTAG_TCK causes the controller to enter the Update-DR state, which terminates the scanning process. If JTAG_TMS is held Low and a rising edge is applied to JTAG_TCK, the controller enters the Shift-DR state. -
Page 404: When The Tap Controller Is In This State And A Rising Edge Is Applied To Jtag_Tck, The
Boundary Scan Test Interface 25.4.3.1.13 Exit1-IR State This is a temporary state. In this state, if JTAG_TMS is held High, a rising edge applied to JTAG_TCK causes the controller to enter the Update-IR state, which terminates the scanning process. If JTAG_TMS is held Low and a rising edge is applied to JTAG_TCK, the controller enters the Pause-IR state. -
Page 405: Figure 25-5 Test Logic Operation: Data Scan
Boundary Scan Test Interface Figure 25-5 Test Logic Operation: Data Scan JTAG_TCK JTAG_TMS Controller State JTAG_TDI Data Input to IR IR Shift Register Parallel Output of IR Instruction IDCODE Data Input to BSR BSR Shift Register Parallel Output of BSR Old Data New Data Register Selected... -
Page 406: Clocking Considerations
Boundary Scan Test Interface Figure 25-6 Test Logic Operation: Instruction Scan JTAG_TCK JTAG_TMS Controller State JTAG_TDI Data Input to IR 0001 IR Shift Register Parallel Output of IR IDCODE New Instruction Data Input to BSR BSR Shift Register Parallel Output of BSR Register Selected Instruction Register JTAG_TDO Enable... -
Page 407: Chapter 26 Amdebug™ Technology
OVERVIEW The ÉlanSC520 microcontroller supports a full-featured, high-performance in-circuit emu- lation capability. This in-circuit emulation support was developed at AMD specifically to enable users to test and debug their software earlier in the design cycle. Utilizing this capability, the software can be more extensively exercised, and at full execution speeds. -
Page 408: Block Diagram
There are multiple ways of connecting the host computer to the ÉlanSC520 microcontroller’s AMDebug port, including through a host computer’s serial port, parallel port, or via an Ethernet connection. For specific tool and connection types, refer to AMD FusionE86 part- ners documentation on p. iii under Third-Party Support. -
Page 409: Figure 26-2 12-Pin Connector Format
AMDebug™ Technology There are two AMDebug connector formats specified: a 12-pin connector (Figure 26-2) and a 20-pin connector (Figure 26-3). They differ in maximum operating frequency and number of connector pins. They both have the same number of active signals, but the 20-pin version has a ground wire placed between each signal wire. -
Page 410: Mechanical Specifications For The Target Connector
AMDebug™ Technology When the serial connector is clocked at high speeds, e.g., above 10 MHz, there is danger of signal cross talk. To alleviate this problem, a 20-pin serial connector format is also available, as shown in Figure 26-3. The arrangement places a ground wire between each signal wire. -
Page 411: Locating The Connector On The Target System
AMDebug™ Technology 26.3.3 Locating the Connector on the Target System Because the AMDebug port can contain high-frequency signals, position the connector as close to the processor as possible. However, allowances should be made for the physical requirements of the AMDebug control unit. For systems that support JTAG-based boundary scanning, a jumper block should be provided for isolating from the rest of the JTAG scan chain (see Figure 26-5) the connection from the AMDebug port to the processor. -
Page 412: Operation
The AMD software debug strategy provides for a small on-chip trace cache that stores only critical information, such as the outcome of a branch decision. The compression techniques employed enable much of the execution path to be retained in the on-chip trace cache. -
Page 413: Software Performance Profiling
AMDebug™ Technology 26.4.2 Software Performance Profiling Software profiling refers to examining the execution times, frequencies, and calling patterns of different software procedures within a complete program. A variety of techniques are currently used, some based on statistical analysis, others based on measurements achieved without statistical sampling. - Page 414 AMDebug™ Technology 26-8 Élan™SC520 Microcontroller User’s Manual...
- Page 415 INDEX Numerics Configuration Base Address register, 4-11 GP bus I/O region, 4-14 32KXTAL2–32KXTAL1 signals PC/AT-compatible I/O peripherals region, 4-12 description, 2-10 PCI configuration space, 4-11 usage, 5-3, 5-8 PCI I/O space, 4-12 33MXTAL2–33MXTAL1 signals initialization, 4-20 description, 2-10 interrupts, 4-17 usage, 2-7, 5-3 memory and I/O space summary (table), 4-4 memory map (figure), 4-7...
- Page 416 Index CPU core identification, 3-7 BIOS. See system initialization. CPU PLL stabilization time, 7-4 bit fields CPU speed, 3-7 A10–A8, 15-18 documentation, xxiv A20G_CTL, 6-8 floating point unit (FPU), 7-3 AEOI, 15-18 initialization, 7-5 AINIT, 14-14 hard CPU reset, 7-5 ALM_AM_PM, 20-8 soft CPU reset, 6-7, 7-5 ALM_INT_ENB, 20-9...
- Page 417 Index bit fields (continued) bit fields (continued) GPCSx_SEL, 12-3, 13-3, 16-1, 17-1 S2_GINT_MODE, 3-19 HI_PRI_0_SEL, 8-8 S5, 15-17, 15-18, 15-19 HI_PRI_1_SEL, 8-8 SBIT_ERR, 10-27 HOUR_MODE_SEL, 20-7 SD_RST_DET, 6-8 ICE_HRST_DET, 6-8 SET, 20-7 ICE_ON_RST, 6-5, 6-7, 24-11 SFNM, 15-18 ICE_SRST_DET, 6-8 SGL_INT_ENB, 10-27 INT_ENB, 17-4 SNGL, 15-18...
- Page 418 Index BR/TC signal chip selects. See GPCS7–GPCS0 signals. control, 25-4 Class Code/Revision ID (PCICCREVID) register description, 2-12 function, 9-8 BSY bit field, 22-7 Clear To Send signals. See CTS2–CTS1 signals. Buffer Chaining Control (GPDMABCCTL) register CLK_INV_ENB bit field, 22-5 function, 14-5 CLK_PIN_DIR bit field, 5-3, 5-9, 16-1, 16-6, 16-7 usage, 14-15 CLK_PIN_ENB bit field, 5-9...
- Page 419 Index PLL lock time (table), 5-2 PLLs, 5-7 data buses registers, 5-6 boot device configuration, 12-7, 12-14 signal descriptions, 2-10 CFG2 pinstrap, 2-13 system design, 5-3 general-purpose (GP) bus data bus, 2-8 bypassing 32.768-kHz oscillator (figure), 5-5 loading, 10-9, 12-3, 13-4 bypassing 33-MHz oscillator (figure), 5-6 PCI data bus, 2-6 bypassing internal oscillators, 2-10, 5-5...
- Page 420 Index DGP bit field, 12-7 ECC. See SDRAM controller. DMA Buffer Chaining Interrupt Mapping ECC_CHK_POS bit field, 10-28 (DMABCINTMAP) register ECCCKBPOS register, 10-10 function, 14-4, 15-5 ECCCKTEST register, 10-10 DMA. See GP-DMA controller. ECCCTL register, 10-10 DMABCINTMAP register, 15-5 ECCMAP register, 15-4 documentation, xxiv ECCMBADD register, 10-10 Élan™SC520 microcontroller documentation, xxiv...
- Page 421 Index echo mode minimum timing (table), 13-9 GP bus reset, 6-7 FE bit field, 21-8 I/O space, 4-14 FERRMAP register, 15-5 I/O-mapped device support, 13-9 initialization, 13-22 fields. See bit fields. interrupts, 13-21 FIFO_ENB bit field, 21-9, 21-13 ISA bus compatibility, 13-11 FIRST_DLY bit field, 12-8 ISA signals and GP bus signals (table), 13-12 Flash memory.
- Page 422 Index operation, 17-3 GP Bus Reset signal. See GPRESET signal. registers, 17-2 GP Bus Terminal Count signal. See GPTC signal. signal descriptions, 2-10 GP Chip Select Data Width (GPCSDW) register software considerations, 17-6 function, 13-5 combining GP Timer Count elements, 17-6 usage, 13-9, 13-19, 13-20, 13-22 reading the cascaded 32-bit timer, 17-6 GP Chip Select Offset (GPCSOFF) register...
- Page 423 Index GPA25–GPA0 signals GP-DMA Channel x Next Transfer Count High description, 2-6, 2-7 (GPDMANXTTCHx) register usage, 2-8, 13-1, 13-4, 13-10, 24-5, 24-6 function, 14-6 usage, 14-15, 14-18 GPAEN signal control, 13-3, 13-6, 14-4 GP-DMA Channel x Next Transfer Count Low description, 2-8 (GPDMANXTTCLx) register usage, 13-10, 14-9, 14-17, 24-6...
- Page 424 Index master and slave core cascading (figure), 14-3 GPIORD signal operating modes, 14-10 control, 13-5 enhanced GP-DMA mode, 14-11 description, 2-8 normal GP-DMA mode, 14-10 usage, 13-4, 13-7, 13-9, 13-11, 13-20, 14-9, 14-17, operation, 14-8 24-6 overview, 14-1 GPIOWR signal PCI considerations, 14-9 control, 13-5 peer-to-peer transfers, 14-9...
- Page 425 Index programmable input/output (PIO), 23-6 programmable interrupt controller (PIC), 15-20 HBCTL register, 9-7 programmable interval timer (PIT), 16-7 HBMSTIRQCTL register, 9-7 read buffer, 11-15 real-time clock (RTC), 20-10 HBMSTIRQSTA register, 9-7 reset types, 6-3 HBTGTIRQCTL register, 9-7 ROM/Flash controller, 12-14 HBTGTIRQSTA register, 9-7 SDRAM controller, 10-29 Header Type (PCIHEADTYPE) register...
- Page 426 Index clocking considerations, 25-20 configuration information, 25-4 LF_PLL1 signal bypass path, 25-5 description, 2-10 instruction path, 25-4 usage, 5-2 main data scan path, 25-5 logic diagram Device Identification register (figure), 25-14 default pin function, 2-3 initialization, 25-20 instruction register, 25-3 interface, 2-2 BYPASS instruction, 25-4 LOOP bit field, 21-13...
- Page 427 Index Master DMA Controller Temporary (MSTDMATMP) MD31–MD0 signals register control, 10-10, 10-19, 23-4 function, 14-8 description, 2-5, 2-6 usage, 10-6, 10-9, 24-4, 24-6 Master DMA General Mask (MSTDMAGENMSK) register MECC6–MECC0 signals function, 14-8 control, 10-10, 10-19, 23-4 usage, 14-20 description, 2-5 usage, 10-9 Master DMA Mask Reset (MSTDMAMSKRST) register function, 14-8...
- Page 428 Index broken transactions, 8-19 bus arbitration, 8-3 OE bit field, 21-7, 21-8 configuration, 9-9 OPMODE_SEL bit field, 10-20, 10-30, 10-31, 10-32 generating configuration cycles, 9-10 configuration space, 4-11 OSC_CTL bit field, 20-7, 20-10 configuring PCI bus devices OUT2 bit field, 21-13 network adapter, 3-16 VGA controller on PCI bus, 3-15 host bridge as PCI bus master, 9-11...
- Page 429 Index external PCI bus master connection (figure), 9-4 PIO15–PIO0 Data (PIODATA15_0) register external PCI bus target connection (figure), 9-3 function, 23-4 PCI clocking, 9-5 usage, 23-5 SERR and PERR connection (figure), 9-5 PIO15–PIO0 Direction (PIODIR15_0) register unsupported configuration registers, 9-9 function, 23-4 unsupported functions, 9-8 usage, 23-5...
- Page 430 Index PIT x Interrupt Mapping (PITxMAP) register usage, 2-11, 3-8, 3-10, 4-5, 12-14, 13-6, 13-9, function, 15-4, 16-2 13-22, 15-9 worksheet (figure), 3-11 PIT x Status (PITxSTA) register write-protection, 3-12 function, 16-3 programmable input/output (PIO) PIT. See programmable interval timer (PIT). block diagram (figure), 23-2 PIT_GATE2 bit field, 16-4 configuration...
- Page 431 Index clocking considerations, 16-6 external clock source (table), 16-6 RAS_CAS_DLY bit field, 10-21 internal clock source (table), 16-6 RAS_PCHG_DLY bit field, 10-21 initialization, 16-7 interrupts, 16-6 RATE_SEL bit field, 20-8 operating modes, 16-4 read buffer. See write buffer and read buffer. hardware-retriggerable one-shot, 16-4 real-time clock (RTC) hardware-triggered strobe, 16-5...
- Page 432 Index registers (continued) registers (continued) DMA Buffer Chaining Interrupt Mapping GP-DMA Resource Channel Map B (DMABCINTMAP), 14-4, 15-5 (GPDMAEXTCHMAPB), 14-4 Drive Strength Control (DSCTL), 23-4 GPIRQx Interrupt Mapping (GPxIMAP), 15-5 ECC Check Bit Position (ECCCKBPOS), 10-10 Header Type (PCIHEADTYPE), 9-8 ECC Check Code Test (ECCCKTEST), 10-10 Host Bridge Control (HBCTL), 9-7 ECC Control (ECCCTL), 10-10...
- Page 433 Index registers (continued) registers (continued) Master Software DRQ(n) Request SDRAM Bank 0–3 Ending Address (MSTDMASWREQ), 14-7 (DRCBENDADR), 10-10 PCI Bus Arbiter Status (PCIARBSTA), 8-2 SDRAM Bank Configuration (DRCCFG), 10-10 PCI Configuration Address (PCICFGADR), 9-8 SDRAM Buffer Control (DBCTL), 11-4 PCI Configuration Data (PCICFGDATA), 9-8 SDRAM Control (DRCCTL), 10-10 PCI Host Bridge Interrupt Mapping SDRAM Timing Control (DRCTMCTL), 10-10...
- Page 434 Index registers (continued) PLL start-up timing (figure), 6-9 System Arbiter Control (SYSARBCTL), 8-2 power-on reset, 6-9 System Arbiter Master Enable power-on reset timing (figure), 6-9 (SYSARBMENB), 8-2 PRGRESET timing (figure), 6-6 System Board Information (SYSINFO), 6-3 programmable reset, 6-6, 10-29 registers, 6-3 System Control Port A (SYSCTLA), 6-3 System Control Port B (SYSCTLB), 16-3...
- Page 435 Index page-mode read access, 12-10 RST signal single CPU read access, 12-9 control, 9-29 word write cycle to Flash memory (figure), 12-12 description, 2-7 writing to Flash, 12-11 usage, 6-4, 6-7, 9-2, 9-3, 9-29 cacheability control, 3-12 RSTLD7–RSTLD0 signals code execution control, 3-12 description, 2-14 configuration, 12-7 usage, 6-3, 6-4, 6-5, 6-6...
- Page 436 Index RTCALMMIN register, 20-6 SDRAM Bank 0–3 Ending Address (DRCBENDADR) register RTCALMSEC register, 20-6 function, 10-10 RTCCMOS register, 20-7 usage, 10-32, 10-33, 10-35 RTCCTLA register, 20-7 SDRAM Bank Configuration (DRCCFG) register RTCCTLB register, 20-7 function, 10-10 RTCCURDOM register, 20-6 usage, 10-15, 10-33 RTCCURDOW register, 20-6 SDRAM Buffer Control (DBCTL) register RTCCURHR register, 20-6...
- Page 437 Index precharge command, 10-31 instruction, 15-7, 15-18, 15-20 sizing algorithm, 10-32 SFNM bit field, 15-18 external bank column number, 10-33 SGL_INT_ENB bit field, 10-27 internal bank number, 10-34 signal descriptions true external bank ending address, 10-35 AMDebug™ technology, 2-12 interrupts, 10-27 configuration, 2-13 multi-bit error, 10-27 descriptions (table), 2-5...
- Page 438 Index signals (continued) signals (continued) GPD15–GPD0, 2-6, 2-8 TRIG/TRACE, 2-12 GPDACK3–GPDACK0, 2-8 VCC_ANLG, 2-14 GPDBUFOE, 2-8 VCC_CORE, 2-14 GPDRQ3–GPDRQ0, 2-8 VCC_I/O, 2-14 VCC_RTC, 2-14 GPIOCS16, 2-8 GPIORD, 2-8 WBMSTR2–WBMSTR0, 2-13 GPIOWR, 2-8 SIN2–SIN1 signals GPIRQ10–GPIRQ0, 2-9 description, 2-9 GPMEMCS16, 2-9 usage, 21-2 GPMEMRD, 2-9 Slave DMA Channel 0–3 Control (SLDMACTL) register...
- Page 439 Index Slave x PIC Initialization Control Word 3 (SxPICICW3) Software Timer Configuration (SWTMRCFG) register register function, 5-6, 18-2 function, 15-7 usage, 5-8, 18-3 usage, 15-16, 15-17 Software Timer Microsecond Count (SWTMRMICRO) Slave x PIC Initialization Control Word 4 (SxPICICW4) register register function, 18-2 function, 15-7...
- Page 440 Index SSIRCV register, 22-2 initialization, 22-8 interrupts, 22-7 SSISTA register, 22-2 operation, 22-3 SSIXMIT register, 22-2 overview, 22-1 Status/Command (PCISTACMD) register registers, 22-2 function, 9-8 signal descriptions, 2-9 usage, 9-10, 9-18, 9-27 software considerations, 22-8 STOP signal system design, 22-1 description, 2-7 four-pin interface (figure), 22-4 usage, 9-3...
- Page 441 Index operation, 8-3 SDRAM regions, 3-18 PCI bus arbiter, 8-7 worksheet (figure), 3-11 arbitration protocol, 8-8 write-protection, 3-12 bus parking, 8-10 programmable I/O pins, 3-20 external PCI master queues (figure), 8-9 reset event, 3-4 host bridge master queue (figure), 8-9 reset vector and reset segment, 3-5 rearbitration, 8-10 initial near jump example (figure), 3-6...
- Page 442 Index Target Ready signal. See TRDY signal. DMA interface, 21-10 receive DMA, 21-10 TC_INT bit field, 22-7 transmit DMA, 21-10 TC_INT_ENB bit field, 22-7 UART as GP-DMA initiator, 14-9 technical support, iii error handling, 21-8 TEMT bit field, 21-7 break indication, 21-8 TERI bit field, 21-6 error reporting, 21-8 test access port (TAP) controller.
- Page 443 Index UART x Line Control (UARTxLCR) register VCC_RTC signal function, 21-4 usage, 2-10, 2-14, 6-9, 20-3, 20-4, 20-11 usage, 21-5, 21-8 UART x Line Status (UARTxLSR) register function, 21-4 usage, 21-6, 21-7, 21-8, 21-10, 21-11 watchdog timer (WDT) UART x Modem Control (UARTxMCR) register AMDebug™...
- Page 444 Index DMA considerations, 11-11 initialization, 11-15 operation, 11-4 PCI considerations, 11-12 read cycles, 11-12 write cycles, 11-12 read buffer, 11-10 disabled, 11-10 enabled, 11-10 registers, 11-4 SDRAM bandwidth improvements, 11-13 bus thrashing (figure), 11-14 software considerations, 11-13 system design, 11-3 shared signals (table), 11-4 write buffer, 11-5 disabled, 11-5...
Need help?
Do you have a question about the Elan SC520 and is the answer not in the manual?
Questions and answers