Page 1 Page 1 Monday, June 7, 1999 10:17 AM Am186 ™ CC/CH/CU Microcontroller Customer Development Platform User’s Manual Order #22002B...
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Page 5 Page v Monday, June 7, 1999 10:17 AM Contents About the Am186™CC/CH/CU Microcontroller Customer Development Platform 0DLQ %RDUG %ORFN 'LDJUDP [Y 'HYHORSPHQW 0RGXOH %ORFN 'LDJUDP [YL 7KHRU\ RI 2SHUDWLRQ [YLL )HDWXUHV [YLL 0DLQ %RDUG [YLL 'HYHORSPHQW 0RGXOH [YLLL...
Page 6 about.book Page vi Monday, June 7, 1999 10:17 AM 7URXEOHVKRRWLQJ ,QVWDOODWLRQ 3UREOHPV )RU 0RUH ,QIRUPDWLRQ Chapter 2 Main Board Functional Description 0DLQ %RDUG /D\RXW 0DLQ %RDUG )HDWXUHV $PŒ&&&+&8 0LFURFRQWUROOHU - 3RZHU 6XSSO\ $ 0HPRU\ ,QWHUIDFHV &RPPXQLFDWLRQ ,QWHUIDFHV 'HEXJ DQG &RQILJXUDWLRQ &LUFXLWU\ ...
Page 7 about.book Page vii Monday, June 7, 1999 10:17 AM Appendix A Default Jumper and Switch Settings 'HIDXOW -XPSHU DQG 6ZLWFK 6HWWLQJV $ Appendix B Platform Pin Usage 3ODWIRUP 3LQ 8VDJH% Appendix C Main Board Bill of Materials 0DLQ %RDUG %LOO RI 0DWHULDOV & Appendix D Development Module Bill of Materials 'HYHORSPHQW 0RGXOH %LOO RI 0DWHULDOV '...
Page 8 about.book Page viii Monday, June 7, 1999 10:17 AM List of Figures )LJXUH 0DLQ %RDUG %ORFN 'LDJUDP [Y )LJXUH 5RXWHU,6'1 'HYHORSPHQW 0RGXOH %ORFN 'LDJUDP [YL )LJXUH 0DLQ %RDUG %ORFN 'LDJUDP 6DPH DV )LJXUH )LJXUH 0DLQ %RDUG /D\RXW )LJXUH $P&&Œ...
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Page 10 about.book Page x Monday, June 7, 1999 10:17 AM List of Tables 7DEOH 1RWDWLRQDO &RQYHQWLRQV [[ 7DEOH 520,&( &RQILJXUDWLRQ 7DEOH ,QVWDOODWLRQ 7URXEOHVKRRWLQJ 7DEOH -XPSHUV 6ZLWFKHV DQG $GMXVWPHQWV 7DEOH &38 DQG 86% &ORFN 2SWLRQV 7DEOH 3RZHU (VWLPDWHV IRU WKH &'3 0DLQ %RDUG 7DEOH ...
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Page 12 about.book Page xii Monday, June 7, 1999 10:17 AM $PŒ&&&+&8 0LFURFRQWUROOHU &'3 8VHU¶V 0DQXDO...
Page 13 • Optional Test Interface Port (TIP) debug board • HP logic analyzer headers to provide access to the Am186CC communications controller signals • Expansion interface through the development module or the 104-pin Am186 processor expansion interface [LLL $PŒ&&&+&8 0LFURFRQWUROOHU &'3 8VHU¶V 0DQXDO...
Page 14 For more information about the Am186CC/CH/CU microcontrollers, refer to • Am186™CC/CH/CU Microcontroller User’s Manual, order #21914 • Am186™CC Communications Controller Data Sheet, order #21915 • Am186™CH HDLC Microcontroller Data Sheet, order #22024 • Am186™CU USB Microcontroller Data Sheet, order #22025 •...
Page 15 Page xv Monday, June 7, 1999 10:17 AM Main Board Block Diagram Figure 0-1 shows the block diagram for the main board on the CDP. Memory Interface Expansion Interface 256K x 16 SRAM Am186 Expansion Development Module Ã SRAM/ICE Socket SRAM/ICE Socket 256K x 16 DRAM...
Page 16 about.book Page xvi Monday, June 7, 1999 10:17 AM Development Module Block Diagram Figure 0-2 (or sheet 2 of the development module schematics included in your kit) shows the block diagram for the CDP’s development module. 6qq…r††Ã7ˆ† 6 () 7ˆssr…rqÃ6qq…r††Ã7ˆ† G@9†...
Page 17 about.book Page xvii Monday, June 7, 1999 10:17 AM Theory of Operation The Am186CC/CH/CU microcontroller CDP provides a comprehensive evaluation system to support Am186CC/CH/CU microcontroller-based designs. The combined features of the Am186CC/CH/CU microcontroller CDP offer designers a complete tool for hardware and software development with the Am186CC/CH/ CU microcontrollers.
Page 18 about.book Page xviii Monday, June 7, 1999 10:17 AM • Communication Interfaces – HDLC synchronous communications Four RS-422, DB-25 DCE/PCM connections clocked by the main board clock generator (Am186CH HDLC microcontroller supports only two connections) Dedicated 2 x 5 header for GCI (supported on Am186CC microcontroller only) –...
Page 19 Page xix Monday, June 7, 1999 10:17 AM Documentation The Am186™CC/CH/CU Microcontroller Customer Development Platform User’s Manual provides information on the design and function of the Am186CC/ CH/CU microcontroller CDP. About This Manual Chapter 1, “Quick Start” helps you quickly set up and start using the Am186CC/ CH/CU microcontroller CDP.
Page 20 • Am186™CU USB Microcontroller Data Sheet Advanced Micro Devices, order #22025 • Am186™CC/CH/CU Microcontroller Register Set Manual Advanced Micro Devices, order #21916 • Am186™ and Am188™ Family Instruction Set Manual Advanced Micro Devices, order #21076 • E86MON™ Software User’s Manual Advanced Micro Devices, order #21891 •...
Page 21 Quick Start This chapter provides information that will help you quickly set up and start using the Am186™CC/CH/CU Microcontroller CDP. The CDP is supported by the E86MON™ board-resident debugger. The E86MON boot monitor software enables you to load, run, and debug programs on the CDP.
Page 22 about.book Page 2 Monday, June 7, 1999 10:17 AM Connecting to a PC via a Serial Port Follow the steps below to connect the Am186CC/CH/CU microcontroller customer development platform to your PC via your PC’s serial port. Installation Requirements The items listed below are necessary to install and run the CDP: •...
Page 23 about.book Page 3 Monday, June 7, 1999 10:17 AM 2. Connect either of the CDP main board’s DB-9 serial ports to an available COM port. Use the serial cable included in the Am186CC/CH/CU microcontroller CDP kit and note that a DB-9 to DB-25 serial connector adapter is provided if your host system requires it.
Page 24 F-2 in Figure 2-2 on page 2-3) should be illuminated. If all of the LEDs are not illuminated, remove the power supply immediately and contact AMD technical support. See “If You Have Questions, We’re Here to Help You.” on page iii.
Page 25 Am186CC/CH/CU microcontroller CDP main board (see Figure 3-3 on page 3-5). 1. Orient the main board such that the AMD logo is in the lower right-hand corner, facing you. Orient the development module such that the AMD logo is in the lower leviathan corner, facing you.
Page 26 Follow the steps below to connect the test interface port (TIP) debug board to the Am186CC/CH/CU microcontroller CDP main board: 1. Orient the main board such that the AMD logo is in the lower righthand corner, facing you. 2. Place the TIP board to the left of the main board with the LCD display toward you.
Page 27 Follow the steps below to connect a ROM-ICE to the Am186CC/CH/CU microcontroller customer development platform main board: 1. Orient the main board such that the AMD logo is in the lower righthand corner, facing you. 2. Set the jumpers according to the configuration shown in Table 1-1 on page 1-7, and jumper your chip select on JP10 (see location F-9 in Figure 2-2 on page 2-3).
Page 28 about.book Page 8 Monday, June 7, 1999 10:17 AM Troubleshooting Installation Problems Table 1-2. Installation Troubleshooting 3UREOHP 6ROXWLRQ 1RWKLQJ KDSSHQV ZKHQ 6RPHWLPHV LW LV GLIILFXOW WR PDNH D JRRG FRQQHFWLRQ SXVKLQJ WKH 5(6(7 ZKHQ SXVKLQJ WKH VPDOO 5(6(7 EXWWRQ ,I DOO HOVH EXWWRQ IDLOV UHPRYH WKH SRZHU VXSSO\ IURP WKH $&...
Page 29 • The Am186CC/CH/CU microcontrollers, see the following documents, which are included in your kit: – Am186™CC Communications Controller Data Sheet – Am186™CH HDLC Microcontroller Data Sheet – Am186™CU USB Microcontroller Data Sheet –...
Page 30 about.book Page 10 Monday, June 7, 1999 10:17 AM $PŒ&&&+&8 0LFURFRQWUROOHU &'3 8VHU¶V 0DQXDO...
Page 31 about.book Page 1 Monday, June 7, 1999 10:17 AM Chapter 2 Main Board Functional Description The Am186CC/CH/CU microcontroller customer development platform (CDP) consists of two boards: a main board that contains an Am186CC communications controller and interfaces, and the development module, which you can use to develop ISDN and router applications.
Page 32 Table 2-1 lists the jumpers and switches. Note that the schematics referenced are in the separate schematic manual in your board kit. Memory Interface Expansion Interface 256K x 16 SRAM Am186 Expansion Development Module Ã SRAM/ICE Socket SRAM/ICE Socket 256K x 16 DRAM...
Page 33 about.book Page 3 Monday, June 7, 1999 10:17 AM Figure 2-2. Main Board Layout $PŒ&&&+&8 0LFURFRQWUROOHU &'3 8VHU¶V 0DQXDO...
Page 34 about.book Page 4 Monday, June 7, 1999 10:17 AM Table 2-1. Jumpers, Switches, and Adjustments 3DUW )XQFWLRQ 'HVFULSWLRQ 5HIHUHQFH LQ 6FKHPDWLF )LJXUH 5HIHUHQFH 6KHHW +'/& 8VHG WR URXWH '&( FORFNV IRU 0DLQ ERDUG +'/& &KDQQHO ' 6KHHW &KDQQHO ' DQG FORFN VHOHFW +'/&...
Page 35 about.book Page 5 Monday, June 7, 1999 10:17 AM Table 2-1. Jumpers, Switches, and Adjustments (Continued) 3DUW )XQFWLRQ 'HVFULSWLRQ 5HIHUHQFH LQ 6FKHPDWLF )LJXUH 5HIHUHQFH 6KHHW -3 65$0520 8VHG WR VHOHFW YDULRXV 65$0 0DLQ ERDUG ,&( GHYLFH VHOHFW DQG 520 FRQILJXUDWLRQV 6KHHW 5HVHW VZLWFK 8VHG WR UHVHW WKH &'3...
Page 36 about.book Page 6 Monday, June 7, 1999 10:17 AM Table 2-1. Jumpers, Switches, and Adjustments (Continued) 3DUW )XQFWLRQ 'HVFULSWLRQ 5HIHUHQFH LQ 6FKHPDWLF )LJXUH 5HIHUHQFH 6KHHW 6: )ODVK PHPRU\ 8VHG WR GHWHUPLQH )ODVK 0DLQ ERDUG GDWD EXV ZLGWK PHPRU\ ZLGWK DV RU ELWV 6KHHW VHOHFW 'HIDXOW ELWV...
Page 37 about.book Page 7 Monday, June 7, 1999 10:17 AM Table 2-1. Jumpers, Switches, and Adjustments (Continued) 3DUW )XQFWLRQ 'HVFULSWLRQ 5HIHUHQFH LQ 6FKHPDWLF )LJXUH 5HIHUHQFH 6KHHW 7HVW SRLQW 7HVW SRLQW IRU 86%' IURP 86% 0DLQ ERDUG 6KHHW FRQQHFWRU 3 "...
Page 38 • Communications interfaces, page 2-27 • Debug and configuration circuitry, page 2-39 • Expansion interfaces, page 2-49 Am186™CC/CH/CU Microcontroller (J14) The Am186CC/CH/CU microcontroller customer development platform supports a 160-pin PQFP Am186CC communications controller operating at 25, 40, or 50 MHz. The integrated features of the Am186CC communications controller provide a glueless interface to DRAM or SRAM system memory and Flash memory.
Page 39 Am186CH HDLC microcontroller block diagram; and Figure 2-5 on page 2-10 shows the Am186CU USB microcontroller block diagram. Serial Communications Peripherals Interrupt Synchronous High-Speed Chip PIOs Controller Am186 Watchdog Serial Selects UART UART with (48) (17 Ext. Timer Interface (SSI)
Page 40 Page 10 Monday, June 7, 1999 10:17 AM Serial Communications Peripherals Interrupt Chip High-Speed Synchronous PIOs Controller Am186 Watchdog Selects UART Serial UART with (48) (17 Ext. Timer (14) Interface (SSI) Autobaud Sources) Physical Interface SmartDMA Glueless General- DRAM...
Page 41 Page 11 Monday, June 7, 1999 10:17 AM Am186™CC/CH/CU Microcontroller Clocking Four types of input clocks are used on the main board: the system clock, USB clock (Am186CC and Am186CU microcontrollers only), UART clock, and HDLC clocks (Am186CC and Am186CH microcontrollers only).
Page 42 UART clock, you must drive the clock with a source that does not exceed the Am186CC/CH/CU microcontroller’s V 9&&$ 9&& " &38; PT8#ƒ Ecliptek EC1300HS-XX S) 8S`TU6GÃUC! Ecliptek EC2-24.000M-CL150 &38; S) Figure 2-6. Am186™CC/CH/CU Microcontroller System Clock $PŒ&&&+&8 0LFURFRQWUROOHU &'3 8VHU¶V 0DQXDO...
Page 43 about.book Page 13 Monday, June 7, 1999 10:17 AM USB Clock • The USB clock (shown in Figure 2-7or sheet 3 of the main board schematics included in your kit), which must be 48 MHz, may be derived from one of the following: •...
Page 44 about.book Page 14 Monday, June 7, 1999 10:17 AM The UCLK input at location Y4 (see location J11 in Figure 2-2 on page 2-3) is used to drive the UART or High-Speed UART with a unique clock source that is not derived from the system clock.
Page 45 DRAM, SRAM, and Flash memory components; the DCE and UART transceivers; the HDLC clock generator; and the 3.3-V LDO regulator. This power supply is also routed to the CDP development module, TIP connector, and Am186 processor expansion interface connectors. For details, see Figure 2-9 or sheet 14 of the main board schematics included in your kit.
Page 46 about.book Page 16 Monday, June 7, 1999 10:17 AM 3.3 V @ 500 mA The 3.3-V LDO regulator at location U29 generates the 3.3 V from the 5-V output. This power supply is used to provide power to the Am186CC communications controller, the USB detect circuitry, and to the optional external USB transceiver.
Page 47 about.book Page 17 Monday, June 7, 1999 10:17 AM –24 V @ 50 mA and –70 V @ 60 mA A switching flyback circuit from the 12-V source generates the –24 V and the – 70 V. These outputs are routed to the CDP development module and are used in the POTS interface.
Page 48 about.book Page 18 Monday, June 7, 1999 10:17 AM Table 2-3. Power Estimates for the CDP Main Board 9ROWDJH 9 'HYLFH 4W\ , P$ P$ 3 P: 3 P: $P&& FRPPXQLFDWLRQV FRQWUROOHU 86% WUDQVFHLYHU '5$0 . [ 65$0 .
Page 49 about.book Page 19 Monday, June 7, 1999 10:17 AM Table 2-4. Power Estimates for the CDP Development Module 9ROWDJH 9 'HYLFH 4W\ , P$ , P$ 3 P: 3 P: (WKHUQHW FRQWUROOHU ,6'1 67 WUDQVFHLYHU ,6'1 8 WUDQVFHLYHU '70) '6/$& ± 56/,&...
Page 50 about.book Page 20 Monday, June 7, 1999 10:17 AM Memory Interfaces The Am186CC/CH/CU microcontroller customer development platform main board supports DRAM or SRAM system main memory and Flash memory. Figure 2-13 shows the DRAM or SRAM system and Flash memory map, Figure 2-14 on page 2-21 shows the DRAM and SRAM circuitry, and Figure 2-15 on page 2-22 shows the Flash memory circuitry.
Page 51 about.book Page 21 Monday, June 7, 1999 10:17 AM An unpopulated component location, U18, is available for a 256K x 16 device for DRAM bank 1 to be used in the upper 512K of memory space (UCS space). This enables you to boot from Flash memory located in UCS space, and then remap UCS to DRAM bank 1.
Page 52 about.book Page 22 Monday, June 7, 1999 10:17 AM Flash Memory A single, surface-mount, TSOP Am29F800, 55-ns, 8-Mbit Flash memory device is populated on the CDP main board to allow for zero wait state operation at 50 MHz. See Figure 2-15 or sheet 4 of the main board schematics included in your kit.
Page 53 about.book Page 23 Monday, June 7, 1999 10:17 AM Configuration Overview This section describes the options associated with Flash memory and main system memory interfaces. Flash Memory • Flash memory banking select Populating R92 enables the highest order address bit to the Flash memory to be routed from A19 (default).
Page 54 about.book Page 24 Monday, June 7, 1999 10:17 AM Table 2-6. DIP x8/x16 SRAM, ROM-ICE Device Selection -3 -3 9LVXDO 'HWDLO 'HYLFH 3/% 36(/ 36(/ 36(/ 36(/ 3+% JP12 JP11 65$0 1& .[ 65$0 1& .[ 65$0 ...
Page 55 about.book Page 25 Monday, June 7, 1999 10:17 AM ‘'ÃÃ‘ %ÃTS6HÃ9r‰vprÃSPHÃD8@ S69b $d !"# ! " S6b (d !# ! " " SS69 S!'% S69 " SS69' S!%" S69' S!'$ S!%! SS69 SS69( S69( S6" SS69! S!'# S69! S6"...
Page 56 about.book Page 26 Monday, June 7, 1999 10:17 AM Table 2-7. SRAM and ROM Pinouts 65$0 65$0 . [ . [ . [ . [ . [ 1& &( &( &( &( &( &6 1& 9&&...
Page 57 about.book Page 27 Monday, June 7, 1999 10:17 AM Communication Interfaces This section describes the communication interfaces available on the Am186CC/ CH/CU microcontroller customer development platform’s main board. The communication interface I/O ports include two RS-232 DB-9 interfaces for the low- and high-speed serial ports derived from the integrated Am186CC communications controller UARTs, four RS-530 DB-25 DCE/PCM ports derived from the integrated Am186CC or Am186CH microcontroller HDLC interface, and a peripheral USB port derived from the integrated Am186CC or Am186CU...
Page 58 about.book Page 28 Monday, June 7, 1999 10:17 AM The high- or low-speed serial ports can also be configured to use up to four additional PIOs as additional hardware flow control at JP5 for the high-speed port, and JP3 for the low-speed port. The PIOs are defined in an RS232 serial port configuration as follows: •...
Page 59 about.book Page 29 Monday, June 7, 1999 10:17 AM Figure 2-17. RS-232 Serial Port Routing $PŒ&&&+&8 0LFURFRQWUROOHU &'3 8VHU¶V 0DQXDO...
Page 60 about.book Page 30 Monday, June 7, 1999 10:17 AM RS-530 DCE/PCM HDLC Ports Four HDLC DCE/PCM ports are available on the Am186CC microcontroller (two for the Am186CH microcontroller) via RS-530 DB-25 connectors configured as DCE devices from the integrated HDLC controllers in the two microcontrollers. Figure 2-18 (or sheet 6 of the main board schematics included in your kit) shows a single HDLC RS-530 circuit.
Page 61 about.book Page 31 Monday, June 7, 1999 10:17 AM NOTE: An HDLC interface being used as another function on the CDP must have that function’s RS-530 port transceiver shut down to prevent contention between the RS-530 port and the desired HDLC function. The CDP main board provides individual status LEDs for the four RS-530 DCE/ PCM ports A–D, at CR1–CR4, respectively.
Page 62 about.book Page 32 Monday, June 7, 1999 10:17 AM Table 2-8. Switch Options to Enable R-530 DCE Clocking +'/& 6: 6ZLWFK 6: 6ZLWFK 3RUW 6HJPHQW 6HJPHQW 9LVXDO 9LVXDO 'HWDLO 'HWDLO ± ± ± ± ± ± ± ± ± ± ±...
Page 63 about.book Page 33 Monday, June 7, 1999 10:17 AM PCM Mode PCM clocking mode configuration is controlled by the same switches as DCE clocking with the addition of SW10, which provides a variable PCM frame sync. The PCM data clock can be varied from 64 kHz to 8.192 MHz, and the frame sync can be 1, 2, 4, 8, or 16 data clocks wide with positive or negative polarity.
Page 64 about.book Page 34 Monday, June 7, 1999 10:17 AM Table 2-11. Switch Options to Set R-530 PCM Clocking Frequency 6: 6ZLWFK 3&0 &ORFN 6HJPHQW )UHTXHQF\ 9LVXDO 'HWDLO N+] ± N+] ± N+] ± N+] ± 0+] ±...
Page 65 about.book Page 35 Monday, June 7, 1999 10:17 AM Table 2-12. Switch Options to Set R-530 PCM Frame Sync 'DWD 6: 6ZLWFK &ORFN 6HJPHQW 3RODULW\ :LGWK 9LVXDO 'HWDLO ± ± ± ± " ± ± ± ± ± ± ± "...
Page 66 about.book Page 36 Monday, June 7, 1999 10:17 AM Table 2-13. HDLC DCE/PCM Clock Routing Options &ORFN +'/& 0RGH 9LVXDO 'HWDLO 6RXUFH '&( 3&0 ,QWHUQDO 7&/.$ )6&$ ± ² ² ² ,QWHUQDO 5&/.$ &/.$ ± ([WHUQDO 7&/.$ )6&$ ± ² ²...
Page 67 about.book Page 37 Monday, June 7, 1999 10:17 AM DCE Multidrop Mode Another feature of the CDP main board is the ability of the HDLC ports to operate in multidrop mode by using SW3, SW5, SW6, and SW7. When any of these switches are in the ON position, the transmit (TXD), receive (RXD), and CTS are shorted together.
Page 68 about.book Page 38 Monday, June 7, 1999 10:17 AM Attach 1. The Am186CC or Am186CU microcontroller polls PIO42 for logic High level to detect an active host/hub upstream connection (USBVCC is on). In the case where an active USB host/hub is connected to the CDP USB port and power is not applied to the CDP, Q2 isolates the USBVCC from the CDP to prevent damage to the Am186CC communications controller.
Page 69 about.book Page 39 Monday, June 7, 1999 10:17 AM Debug and Configuration Circuitry Several debug and configuration options make the Am186CC/CH/CU microcontroller customer development platform a useful tool for the development of specific applications. The CDP offers an interface to the Test Interface Port (TIP) debug card (not included in your kit) that provides status indicators and debug peripherals, debug headers to provide access to most critical pins on the microcontroller, a reset configuration switch to define specific system parameters,...
Page 70 about.book Page 40 Monday, June 7, 1999 10:17 AM • INT0 on the Am186CC communications controller is used as the TIP Ethernet interrupt signal. • INT7 on the Am186CC communications controller is used as the TIP serial port 1 interrupt signal. •...
Page 71 about.book Page 41 Monday, June 7, 1999 10:17 AM Figure 2-20. Test Interface Port Connector $PŒ&&&+&8 0LFURFRQWUROOHU &'3 8VHU¶V 0DQXDO...
Page 72 about.book Page 42 Monday, June 7, 1999 10:17 AM Debug Headers Eight 2 x 10 shrouded headers are used to directly interface to the HP 165xx series logic analyzer through HP series termination adapter to the CDP. Figure 2-21 on page 2-43 shows the header layout.
Page 73 about.book Page 43 Monday, June 7, 1999 10:17 AM HDLC_C,HDLC_D, HDLC_A,HDLC_B, RXD_HU, TXD_HU, UCLK DRQ1–DRQ0 Am186CC/CH/CU Controller AD0–AD15 MA0–MA15 Figure 2-21. HP Header Grouping $PŒ&&&+&8 0LFURFRQWUROOHU &'3 8VHU¶V 0DQXDO...
Page 74 about.book Page 44 Monday, June 7, 1999 10:17 AM CQÃ8‚ QP9Ã QP9Ã( " 6€ '%88 Avtˆ…rÃ! (ÃƒÃ!# & QP9Ã! QP9Ã! U‚ƒÃWvr Q8Tb&d !" ! " &/. S9Æ !#$ ! " !#$ ! " V8TÆ &/. G8TÆ !#$ ! " !# ! " H8T"Æ...
Page 75 about.book Page 45 Monday, June 7, 1999 10:17 AM Reset Configuration SW13 and SW15 are used to define the state of the RESCON register bits AD15– AD0. The RESCON register identifies a bit as a logic High when a switch segment is in the ON position.
Page 76 about.book Page 46 Monday, June 7, 1999 10:17 AM W88" IPU@)ÃV†rqÃ‡‚Ãqrsvr qhˆtu‡r…Ãi‚h…q NOTE: Used to define system options. ‚ƒ‡v‚† S69b $d TX $ 5$' !#$ ! " 5$' Q6C $ " 5$' Q6C % " 5$' Q6C & 5$' Q6C ' 5$' Q6C (...
Page 77 about.book Page 47 Monday, June 7, 1999 10:17 AM SW16 segments 3 and 4 are used for the pinstraps controlling the USB clock PLL mode on the CDP. The default setting for the USB PLL is 2x PLL mode to attain a 48-MHz USB frequency with the 24-MHz crystal input.
Page 78 about.book Page 48 Monday, June 7, 1999 10:17 AM Table 2-15. CPU and USB Clocking Options 3// 0RGH &ORFN 3// %\SDVV 2VFLOODWRU 6\VWHP FORFN ± 0+] ± 0+] ± 0+] ± 0+] ± 0+] ± 0K] 0+] ± 0+] 86% FORFN 6KDUHG V\VWHP...
Page 79 ISDN/router development module. Am186™ Processor Expansion Interface The Am186 processor local bus expansion interface, located at P26 and P27, supports the PC/104 form-factor expansion connector for additional prototyping and testing. The traditional PC/104 signals are not present on the board; however, the Am186 processor expansion interface enables you to attach wirewrap or prototype boards that have the same standard physical interface.
Page 80 MCS2 DRQ1 MCS1 MA15 DRQ0 MA14 MCS0 CLKOUT MA13 MA12 RTRU MA11 TXDU AD10 MA10 RXDU AD11 CTSU AD12 DT/R VCC5 AD13 INT4 AD14 INT3 AD15 HLDA VCC5 Figure 2-27. Am186™ Processor Expansion Interface $PŒ&&&+&8 0LFURFRQWUROOHU &'3 8VHU¶V 0DQXDO...
Page 81 about.book Page 51 Monday, June 7, 1999 10:17 AM Development Module Interface The development module interface, located at P19 and P12, is primarily used to provide an interface to the ISDN/router development module. This module enables the CDP to be used as a specific system application. The module connectors contain all the signals needed to develop particular applications based on the Am186CC communications controller.
Page 82 about.book Page 52 Monday, June 7, 1999 10:17 AM Q8Tb&d !" ! Æ Æ & Q8T% Q8T& Æ %& Æ Q8T# Q8T$ Æ Æ Q8T! Q8T" Æ %" Æ Q8T V8TÆ !#$ ! !#$ ! G8TÆ $& TS9` !# !...
Page 83 about.book Page 1 Monday, June 7, 1999 10:17 AM Chapter 3 Development Module Functional Description The Am186CC/CH/CU microcontroller customer development platform (CDP) consists of two boards: a main board that contains an Am186CC communications controller and interfaces, and the development module, which you can use to develop ISDN and router applications.
Page 84 about.book Page 2 Monday, June 7, 1999 10:17 AM Development Module Layout Figure 3-1 (or sheet 2 of the development module schematics included in your kit) shows a block diagram of the Am186CC/CH/CU microcontroller CDP development module; Figure 3-2 on page 3-3 shows the layout of the development module.
Page 85 about.book Page 3 Monday, June 7, 1999 10:17 AM Figure 3-2. Router/ISDN Development Module Layout Diagram $PŒ&&&+&8 0LFURFRQWUROOHU &'3 8VHU¶V 0DQXDO...
Page 86 The development module contains the system components used in developing ISDN terminal adapter/modem and low-end router applications that use many AMD-specific devices. This section describes the following development module features: • Main board interface on page 3-4 • 10BaseT Ethernet interface on page 3-7 •...
Page 87 about.book Page 5 Monday, June 7, 1999 10:17 AM Figure 3-3. Main Board and Development Module Connection $PŒ&&&+&8 0LFURFRQWUROOHU &'3 8VHU¶V 0DQXDO...
Page 88 about.book Page 6 Monday, June 7, 1999 10:17 AM Figure 3-4. Router/ISDN Development Module Connector Layout Diagram The interface between the Am186CC/CH/CU microcontroller CDP main board and development module incorporates the full Am186CC communications controller local bus address, data, and most control signals. The interface also supports the four external HDLC interfaces (see note), SSI, and the 3.3-V, 5-V, –...
Page 89 Typically, bidirectional buffering is not required for the address and control buses; however, because the module incorporates a bus mastering Ethernet controller (AMD Am79C961A), control of these buses is given to the bus mastering device. Control logic for the buffers is incorporated in a programmable logic device (PLD), U13, used on the development module (see Figure 3-4 on page 3-6).
Page 90 about.book Page 8 Monday, June 7, 1999 10:17 AM 1& 1& 1& 1& Figure 3-5. Front View of the RJ-45 Connector Table 3-1. RJ-45 Connector Pin Functions 3LQ 1XPEHU )XQFWLRQ 1RW XVHG 1RW XVHG 5;± 1RW XVHG 1RW XVHG $PŒ&&&+&8 0LFURFRQWUROOHU &'3 8VHU¶V 0DQXDO...
Page 91 about.book Page 9 Monday, June 7, 1999 10:17 AM Three LEDs (CR1–CR3) on the Ethernet controller interface provide status information for the port. The function of these LEDs is controlled by the ISA bus configuration registers on the PCnet-ISA II Ethernet controller and can be modified through software or the EEPROM.
Page 92 about.book Page 10 Monday, June 7, 1999 10:17 AM The PLD creates the Ethernet packet SRAM chip select, SRAMCS, from the MASTER output when the PCnet-ISA II Ethernet controller is the bus master. When the Am186CC communications controller is the bus master, the SRAMCS output is three-stated and MCS0 is used as the packet SRAM chip select.
Page 93 about.book Page 11 Monday, June 7, 1999 10:17 AM D†‚yh‡rÃs…‚€ÃW88$Ãƒyhr 8‚rp‡Ãh‡Ã†vtyrÃƒ‚v‡ W88$ W886@ v‡uÃ$Ã€vyÃ‡…hpr @pyvƒ‡rxÃ@8!HDUS !HC“ 8" !&ƒA !&ƒA @I@UY (& YU6G 8IUGb$d @I@UY! YU6G! !#$ S@TPVU 8IUG DIU" W88$ S@T@U DSR"Æ Q8T! !# Æ...
Page 94 The four-wire 2B+D S/T interface connects through an RJ-45 connection at P2 by using the Am186CC communications controller with the AMD Am79C32A DSC circuit. This connection provides the path between a TE (terminal equipment) and NT1 device, and is the ISDN interface commonly used in businesses and in Europe.
Page 95 about.book Page 13 Monday, June 7, 1999 10:17 AM ISDN S/T Interface The glueless connection between the Am186CC communications controller and the Am79C32A ISDN DSC circuit provides the four-wire 2B+D S/T interface. The DSC serial interface is capable of being configured as an IOM-2 or SBP serial microprocessor interface.
Page 96 about.book Page 14 Monday, June 7, 1999 10:17 AM The Am79C32A DSC circuit uses the PCS1 (peripheral chip select 1) signal, which asserts between addresses 100h and 1FFh, and the INT6 (interrupt 6) signal is edge triggered as an active Low interrupt. The Am79C32A DSC circuit’s MCLK output is programmed to be 4.096 MHz and is used to drive the MCLK input to the Am79C031 DSLAC device on the POTS interface through JP2.
Page 97 about.book Page 15 Monday, June 7, 1999 10:17 AM ISDN U Interface The Lucent T7256A NT1 device provides the two-wire 2B+D U interface to provide two-wire network termination. The NT1 device processes the ISDN BRI bit stream that consists of two 64-Kbit/s B channels and a single 16-Kbit/s D channel.
Page 98 about.book Page 16 Monday, June 7, 1999 10:17 AM Table 3-3. U Interface Configuration 5HIHUHQFH 8 ,QWHUIDFH 0RGH 7$ $P&$7$ & 'HSRSXODWH 3RSXODWH & 'HSRSXODWH 3RSXODWH & 'HSRSXODWH 3RSXODWH & 'HSRSXODWH 3RSXODWH 'HSRSXODWH 3RSXODWH 'HSRSXODWH 3RSXODWH 'HSRSXODWH 3RSXODWH 'HSRSXODWH 3RSXODWH 'HSRSXODWH 3RSXODWH 3RSXODWH...
Page 99 about.book Page 17 Monday, June 7, 1999 10:17 AM W 88$ 8"% ˆA U 88 S$& S$" "& &'F STSS GCSS "& S@T@U Æ PQU W9S " & 8h‡u‚qr & VQ96 IP9 " 6‚qr V8PH86 U C S#& W88$ 8S& !!H %I "( #%$67...
Page 100 about.book Page 18 Monday, June 7, 1999 10:17 AM POTS Interface The Am186CC/CH/CU microcontroller CDP development module provides two POTS connections on RJ-11 connectors at P5 and P4. These POTS connections are used to plug standard POTS telephones in an ISDN terminal adapter or router application.
Page 101 about.book Page 19 Monday, June 7, 1999 10:17 AM Figure 3-11. DSLAC™ Device Circuitry In the default configuration, the S/T or U transceiver provides the clock and frame sync for the PCM interface and transfers data directly between the ISDN interface and the POTS interface.
Page 102 about.book Page 20 Monday, June 7, 1999 10:17 AM S/T SBP Mode The DSLAC device’s PCLK and MCLK can be generated from the Am79C32A DSC circuit’s CLKA and FSCA outputs. In this case, PCLK is a 192-kHz data clock, and MCLK is configured as a 4.096-MHz master clock driven directly into the DSLAC device.
Page 103 about.book Page 21 Monday, June 7, 1999 10:17 AM U PCM The T7256 U transceiver generates a 2.048-MHz PCLK that can be directly connected to the DSLAC device’s PCLK and MCLK inputs. NOTE: HDLC channel C and GCI are supported only on the Am186CC communications controller.
Page 104 about.book Page 22 Monday, June 7, 1999 10:17 AM Because the Am186CC communications controller and the Am79C031 DSLAC device are both downstream devices to the ISDN controller, the PCM/GCI data is driven from the ISDN device transmit pin (TXD) to the Am186CC communications controller and the DSLAC receive pins (RXD) and vice-versa.
Page 105 Page 23 Monday, June 7, 1999 10:17 AM Table 3-6. Am186™CC Communications Controller/Am79C031 DSLAC™ Communication Configuration $P&& &RPPXQLFDWLRQV &RQWUROOHU$P& '6/$& &RPPXQLFDWLRQ &RPSRQHQW 0RGH 5HIHUHQFH 9DOXH 3&0 $ 3&0 ' *&, $ 'HSRSXODWH 3RSXODWH 'HSRSXODWH 3RSXODWH 3RSXODWH 3RSXODWH 'HSRSXODWH 3RSXODWH...
Page 106 about.book Page 24 Monday, June 7, 1999 10:17 AM RSLIC Device Interface The DSLAC device provides a direct connection to the Am79R79 RSLIC through two sets of data and control I/O signals used for each channel. The data signals are analog signals from the RSLIC device.
Page 107 about.book Page 25 Monday, June 7, 1999 10:17 AM Dual Tone Multiple Frequency (DTMF) Interface The two DTMF receivers are used to detect valid tone pairs from each POTS telephone interface, and then translate them into digital signaling. The digital signaling is used by the Am186CC communications controller to set up and place a call.
Page 108 Page 26 Monday, June 7, 1999 10:17 AM Low Noise Board (LNB) Interface The LNB interface can be used to connect Low Noise Boards developed in AMD’s Communication Products Division (CPD). The LNB’s are evaluation boards which contain different AMD SLAC and SLIC devices. This feature allows the user to disable the DSLAC and RSLIC used on the development module and use the LNB boards for the POTS interface.
Page 109 about.book Page 1 Monday, June 7, 1999 10:17 AM Appendix A Default Jumper and Switch Settings This appendix contains the default jumper and switch settings for the main board and development module. Table A-1. Main Board Default Jumper and Switch Settings 3DUW 1XPEHU 3RVLWLRQ...
Page 110 about.book Page 2 Monday, June 7, 1999 10:17 AM Table A-1. Main Board Default Jumper and Switch Settings (Continued) 3DUW 1XPEHU 3RVLWLRQ 6: 6: 6: 6: $PŒ&&&+&8 0LFURFRQWUROOHU &'3 8VHU¶V 0DQXDO...
Page 111 about.book Page 3 Monday, June 7, 1999 10:17 AM Table A-1. Main Board Default Jumper and Switch Settings (Continued) 3DUW 1XPEHU 3RVLWLRQ 6: 6: 6: 6: 1& 1& 1& 1& 1& 1& 575+8 &76+8 8&6 $PŒ&&&+&8 0LFURFRQWUROOHU &'3 8VHU¶V 0DQXDO...
Page 112 about.book Page 4 Monday, June 7, 1999 10:17 AM Table A-1. Main Board Default Jumper and Switch Settings (Continued) 3DUW 1XPEHU 3RVLWLRQ 1& 1& -3 -3 1& &RQQHFWHG 1& &RQQHFWHG &RQQHFWHG 1& $PŒ&&&+&8 0LFURFRQWUROOHU &'3 8VHU¶V 0DQXDO...
Page 113 about.book Page 5 Monday, June 7, 1999 10:17 AM Table A-1. Main Board Default Jumper and Switch Settings (Continued) 3DUW 1XPEHU 3RVLWLRQ -3 1& 1& &RQQHFWHG 1& &RQQHFWHG 1& Insert jumper on a signal pin for a no connect (NC). Table A-2.
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Page 115 about.book Page 1 Monday, June 7, 1999 10:17 AM Appendix B Platform Pin Usage This appendix provides the Am186CC/CH/CU microcontroller CDP pin usage information in the following tables. Table B-1. PIO Usage 0XOWLSOH[HG /RFDWLRQ 8VDJH ,VRODWLRQ 0HWKRG )XQFWLRQV 3,2 705,1 0DLQ 2SWLRQDO '&' -XPSHU EORFN -3 DQG -3...
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Page 118 about.book Page 4 Monday, June 7, 1999 10:17 AM Table B-1. PIO Usage (Continued) 0XOWLSOH[HG /RFDWLRQ 8VDJH ,VRODWLRQ 0HWKRG )XQFWLRQV 3,2 '&(B&76B$ 0RGXOH 56 SRUW $ +'/& $ WUDQVFHLYHU HQDEOH VZLWFK 6: 3&0B76&B$ 0RGXOH LQWHUIDFH 'R QRW DWWDFK PRGXOH '6/$& FKLS VHOHFW 3,2 '&(B575B$ 0RGXOH 56 SRUW $...
Page 119 about.book Page 5 Monday, June 7, 1999 10:17 AM Table B-1. PIO Usage (Continued) 0XOWLSOH[HG /RFDWLRQ 8VDJH ,VRODWLRQ 0HWKRG )XQFWLRQV 3,2 '&(B7&/.B& 0RGXOH 56 SRUW & +'/& & WUDQVFHLYHU HQDEOH VZLWFK 6: 3&0B)6&B& +'/& FORFN URXWLQJ +'/& FORFN URXWLQJ MXPSHU -3 0RGXOH LQWHUIDFH 'R QRW DWWDFK PRGXOH...
Page 120 about.book Page 6 Monday, June 7, 1999 10:17 AM Table B-1. PIO Usage (Continued) 0XOWLSOH[HG /RFDWLRQ 8VDJH ,VRODWLRQ 0HWKRG )XQFWLRQV 3,2 705,1 0DLQ 2SWLRQDO 5, KDUGZDUH -XPSHU EORFN -3 DQG -3 ERDUG IORZ FRQWURO IRU 8$57 RU +LJK6SHHG 8$57 $P SURFHVVRU 'R QRW DWWDFK $P H[SDQVLRQ LQWHUIDFH SURFHVVRU H[SDQVLRQ...
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Page 122 about.book Page 8 Monday, June 7, 1999 10:17 AM Table B-1. PIO Usage (Continued) 0XOWLSOH[HG /RFDWLRQ 8VDJH ,VRODWLRQ 0HWKRG )XQFWLRQV 3,2 '&(B5&/.B% 0DLQ 56 SRUW % +'/& % WUDQVFHLYHU HQDEOH ERDUG VZLWFK 6: 3&0B&/.B% +'/& FORFN URXWLQJ +'/& FORFN URXWLQJ MXPSHU PRGXOH 0RGXOH LQWHUIDFH 'R QRW DWWDFK PRGXOH...
Page 123 about.book Page 9 Monday, June 7, 1999 10:17 AM Table B-1. PIO Usage (Continued) 0XOWLSOH[HG /RFDWLRQ 8VDJH ,VRODWLRQ 0HWKRG )XQFWLRQV 3,2 &76B+8 0DLQ 56 SRUW ' +'/& ' WUDQVFHLYHU HQDEOH ERDUG VZLWFK 6: '&(B&76B' 3&0B76&B' +LJK6SHHG 8$57 +LJK6SHHG 8$57 WUDQVFHLYHU HQDEOH VZLWFK 6: 0RGXOH LQWHUIDFH 'R QRW DWWDFK PRGXOH...
Page 124 about.book Page 10 Monday, June 7, 1999 10:17 AM Table B-2. Chip Select Usage &KLS 0XOWLSOH[HG /RFDWLRQ 8VDJH 6HOHFW )XQFWLRQ /&6 5$6 0DLQ ERDUG '5$0 ORZHU EDQN 5$6 0&6 3,2^8&6;` 0DLQ ERDUG 65$0 DOWHUQDWH FKLS VHOHFW 0&6 &$6 0DLQ ERDUG '5$0 XSSHU &$6 0&6 &$6...
Page 125 about.book Page 11 Monday, June 7, 1999 10:17 AM Table B-3. Platform Interrupts Pin Usage ,QWHUUXSW 0XOWLSOH[HG /RFDWLRQ 8VDJH 3RODULW\ )XQFWLRQV ,17 ² 7,3 (WKHUQHW $FWLYH +LJK HGJH FRQWUROOHU ,17 ² 0RGXOH 7$ $FWLYH /RZ HGJH ,17 ² 0RGXOH 3&QHW,6$ $FWLYH +LJK HGJH ,17 ²...
Page 126 about.book Page 12 Monday, June 7, 1999 10:17 AM % $PŒ&&&+&8 0LFURFRQWUROOHU &'3 8VHU¶V 0DQXDO...
Page 127 about.book Page 1 Monday, June 7, 1999 10:17 AM Appendix C Main Board Bill of Materials This appendix provides the Am186CC/CH/CU microcontroller customer development platform bill of materials. Table C-1. Main Board Bill of Materials ,WHP 5HIHUHQFH 3DUW 3DFNDJH 3DUW 6SHF &5&5&5&5 /(' 627 627 /80(;...
Page 128 about.book Page 2 Monday, June 7, 1999 10:17 AM Table C-1. Main Board Bill of Materials (Continued) ,WHP 5HIHUHQFH 3DUW 3DFNDJH 3DUW 6SHF & µ) &&$6( 7DQWDOXP & &$6( 9 &&&& S) ;5 9 &&& & &&&& µ)
Page 129 about.book Page 3 Monday, June 7, 1999 10:17 AM Table C-1. Main Board Bill of Materials (Continued) ,WHP 5HIHUHQFH 3DUW 3DFNDJH 3DUW 6SHF *3*3*3*3 *1' 37 7+ $03 *3*3 -3-3-3-3-3 +HDGHU [ 7+[ $03 -3-3 -3-3 +HDGHU [ 7+[ $03 -3...
Page 130 about.book Page 4 Monday, June 7, 1999 10:17 AM Table C-1. Main Board Bill of Materials (Continued) ,WHP 5HIHUHQFH 3DUW 3DFNDJH 3DUW 6SHF 55555 . : 5555 555 555 5 55555 : 5555 555 55555 : 5555...
Page 131 about.book Page 5 Monday, June 7, 1999 10:17 AM Table C-1. Main Board Bill of Materials (Continued) ,WHP 5HIHUHQFH 3DUW 3DFNDJH 3DUW 6SHF 5555 ³ :´ 5555 5555 5555 5555 5555 5555 5555 5555 5555 555 555 555 555 555 555...
Page 132 about.book Page 6 Monday, June 7, 1999 10:17 AM Table C-1. Main Board Bill of Materials (Continued) ,WHP 5HIHUHQFH 3DUW 3DFNDJH 3DUW 6SHF 5555 : 555 555 555 555 . : : .
Page 133 about.book Page 7 Monday, June 7, 1999 10:17 AM Table C-1. Main Board Bill of Materials (Continued) ,WHP 5HIHUHQFH 3DUW 3DFNDJH 3DUW 6SHF 6:6:6: 6: ',3 7+ &. %' 737373 7(6737 607 6LQJOH 3LQ )O\EDFN %HFNPDQ +0 7UDQVIRUPHU 8888 '6&7 623 1DWLRQDO '6&70...
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Page 135 about.book Page 9 Monday, June 7, 1999 10:17 AM Table C-1. Main Board Bill of Materials (Continued) ,WHP 5HIHUHQFH 3DUW 3DFNDJH 3DUW 6SHF .LW 3DUWV 9 $ 6SHFWUH 36$3 3RZHU 6XSSO\ 0HWHU 86% 1HZQH[ 8) &DEOH 56 &DEOH 6DPH DV [[ IW 0DOHWR $03 ...
Page 136 about.book Page 10 Monday, June 7, 1999 10:17 AM & $PŒ&&&+&8 0LFURFRQWUROOHU &'3 8VHU¶V 0DQXDO...
Page 137 about.book Page 1 Monday, June 7, 1999 10:17 AM Appendix D Development Module Bill of Materials This appendix contains the Am186CC/CH/CU microcontroller customer development platform development module bill of materials. Table D-1. Router/ISDN Development Module Bill of Materials ,WHP 4W\ 5HIHUHQFH 3DUW 3DFNDJH...
Page 138 about.book Page 2 Monday, June 7, 1999 10:17 AM Table D-1. Router/ISDN Development Module Bill of Materials (Continued) ,WHP 4W\ 5HIHUHQFH 3DUW 3DFNDJH 3DUW 6SHF &&&&& µ) ;5 9 &&&& &&&& &&&& &&&& &&&& &&&& &&&& &&&& &&&& &...
Page 139 about.book Page 3 Monday, June 7, 1999 10:17 AM Table D-1. Router/ISDN Development Module Bill of Materials (Continued) ,WHP 4W\ 5HIHUHQFH 3DUW 3DFNDJH 3DUW 6SHF & S) &2* 9 &&&& S) ;5 9 '''' 'LRGH 627...
Page 140 about.book Page 4 Monday, June 7, 1999 10:17 AM Table D-1. Router/ISDN Development Module Bill of Materials (Continued) ,WHP 4W\ 5HIHUHQFH 3DUW 3DFNDJH 3DUW 6SHF 56/(: . : 56/(: 57%57$57 . : %57$ 55555 : 5555 5555...
Page 141 about.book Page 5 Monday, June 7, 1999 10:17 AM Table D-1. Router/ISDN Development Module Bill of Materials (Continued) ,WHP 4W\ 5HIHUHQFH 3DUW 3DFNDJH 3DUW 6SHF 0 'DOH &5&:- 'DOH &5&:- 55 'DOH &5&:5)) 55 . : 55 : 6: '3'7...
Page 142 about.book Page 6 Monday, June 7, 1999 10:17 AM Table D-1. Router/ISDN Development Module Bill of Materials (Continued) ,WHP 4W\ 5HIHUHQFH 3DUW 3DFNDJH 3DUW 6SHF 6079&$ 6*67KRPVRQ 6079&$ 7+ 3XOVH 7 7UDQVIRUPHU /+$% ',3 /XFHQW /+$% 36% '2 7HFFRU 36% RU 6*67KRPVRQ 603 88...
Page 143 about.book Page 7 Monday, June 7, 1999 10:17 AM Table D-1. Router/ISDN Development Module Bill of Materials (Continued) ,WHP 4W\ 5HIHUHQFH 3DUW 3DFNDJH 3DUW 6SHF 8QSRSXODWHG 3DUWV &&&& µ) ;5 9 56*/B56*/B : 5555 5555 55...
Page 144 about.book Page 8 Monday, June 7, 1999 10:17 AM $PŒ&&&+&8 0LFURFRQWUROOHU &'3 8VHU¶V 0DQXDO...
Page 145 If there shall, notwithstanding the above provisions, at any time be or arise any liability on the part of AMD by virtue of this agreement and/ or the materials furnished by AMD to you, you agree that in no event will the total aggregate liability of AMD for any claims, losses, or damages exceed $5,000.
Page 146 PLD (U13) Equations ““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““ “ U13 PLD code for the Am186CC CDP Development Module Revision 2.1 “ “ An AMD PLCC-28 PAL22V10 provides glue logic needed between the Am186CC and the“ “ PCNETISAII ethernet controller and ISDN devices. “ “...
Page 147 about.book Page 3 Monday, June 7, 1999 10:17 AM PLD (U13) Equations (continued) “““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““ “ Equations “ “““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““ reset = resout; “Inverted RESOUT driven to a 5V level for the “T7256A (U transceiver) bhlda = hlda + master; “Inverted Am186CC HLDA to the Am79C961A “DACK# that is latched to the end of the cycle bsclk = sclk;...
Page 148 ““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““ “ U20 PLD code for the Am186CC CDP Development Module Revision 2.1 “ “ An AMD PLCC-28 PAL22V10 provides synchronization of clocks between the Am79C031 DSLAC “ “ and the Am79C32A when running in SBP/PCM mode. “ “ Written: Feb. 1999 “...
Page 149 about.book Page 5 Monday, June 7, 1999 10:17 AM PLD (U20) Equations (continued) ““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““ “ “ Equations “ “““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““ STATE_MACHINE divider CLOCKED_BY mclk_c32 RESET_BY resout; “ This state machine generates 4.096MHz clock signal for the DSLAC. STATE one: mclk4=0; goto two; STATE two: mclk4=0;...
Page 150 about.book Page 6 Monday, June 7, 1999 10:17 AM PLD (U20) Equations (continued) STATE six: pclk=1; goto seven; STATE seven: pclk=1; goto eight; STATE eight: pclk=1; goto nine; STATE nine: pclk=1; goto ten; STATE ten: pclk=1; goto eleven; STATE eleven: pclk=1;...
Page 151 about.book Page 7 Monday, June 7, 1999 10:17 AM PLD (U20) Equations (continued) STATE seventeen: pclk=0; goto eighteen; STATE eighteen: pclk=0; goto nineteen; STATE nineteen: pclk=0; goto twenty; STATE twenty: pclk=0; goto twentyone; STATE twentyone: pclk=0; goto twentytwo; STATE twentytwo: pclk=0;...
Page 152 about.book Page 8 Monday, June 7, 1999 10:17 AM PLD (U20) Equations (continued) STATE twentyseven: pclk=0; goto twentyeight; STATE twentyeight: pclk=0; goto twentynine; STATE twentynine: pclk=0; goto thirty; STATE thirty: pclk=0; goto thirtyone; STATE thirtyone: pclk=0; goto thirtytwo; STATE thirtytwo: pclk=0;...
Page 153 about.book Page 9 Monday, June 7, 1999 10:17 AM PLD (U20) Equations (continued) STATE thirtyseven: pclk=0; goto thirtyeight; STATE thirtyeight: pclk=0; goto thirtynine; STATE thirtynine: pclk=0; goto forty; STATE forty: pclk=0; goto fortyone; STATE fortyone: pclk=0; goto fortytwo; STATE fortytwo: pclk=0;...
Page 154 about.book Page 10 Monday, June 7, 1999 10:17 AM PLD (U20) Equations (continued) STATE fortyseven: pclk=0; goto fortyeight; STATE fortyeight: pclk=0; goto fortynine; STATE fortynine: pclk=0; goto fifty; STATE fifty: pclk=0; goto fiftyone; STATE fiftyone: pclk=0; goto fiftytwo; STATE fiftytwo: pclk=0;...
Page 155 about.book Page 11 Monday, June 7, 1999 10:17 AM PLD (U20) Equations (continued) STATE fiftyseven: pclk=0; goto fiftyeight; STATE fiftyeight: pclk=0; goto fiftynine; STATE fiftynine: pclk=0; goto sixty; STATE sixty: pclk=0; goto sixtyone; STATE sixtyone: pclk=0; goto sixtytwo; STATE sixtytwo: pclk=0;...
Page 156 about.book Page 12 Monday, June 7, 1999 10:17 AM PLD (U20) Equations (continued) STATE sixtyfour: “ If the DPLL is synchronized, the state machine is reset to state one in this stage. IF pclk_c32=1 THEN pclk=0; goto sixtyfive; ELSE pclk=1; goto one;...
Page 157 ““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““ “ U20 PLD code for the Am186CC CDP Development Module Revision 2.1 “ “ An AMD PLCC-28 PAL22V10 provides clock synchronization between the Am79C031 DSLAC “ “ and the Am79C32A when running in IOM-2/GCI mode “ “ Written: Feb. 1999 “...
Page 158 about.book Page 14 Monday, June 7, 1999 10:17 AM PLD (20) Equations (Continued) STATE three: mclk4=1; goto one; END divider; STATE_MACHINE DPLL CLOCKED_BY mclk_c32 RESET_BY resout; “ Jitter reduction circuit, implemented as free running up-counter, that counts 15, 16 or 17 “...
Page 159 about.book Page 15 Monday, June 7, 1999 10:17 AM PLD (20) Equations (Continued) STATE nine: pclk=0; goto ten; STATE ten: pclk=0; goto eleven; STATE eleven: pclk=0; goto twelve; STATE twelve: pclk=0; goto thirteen; STATE thirteen: pclk=0; goto fourteen; STATE fourteen: pclk=0;...
Page 160 about.book Page 16 Monday, June 7, 1999 10:17 AM PLD (20) Equations (Continued) STATE sixteen: “If the DPLL is synchronized, the state machine is reset to state one in this stage. IF bclk_c32=1 THEN pclk=0; goto seventeen; ELSE pclk=1; goto one; “...
Page 161 PLD (U24) Equations ““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““ “ U24 PLD code for the Am186CC CDP Development Module Revision 2.1 “ “ “ “ An AMD PLCC-28 PAL22V10 provides glue logic needed for the POTS interface “ “ “ “ Written: Oct. 1998 “...
Page 162 about.book Page 18 Monday, June 7, 1999 10:17 AM PLD (U24) Equations (continued) “““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““ “ Equations “ “““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““““ dtmf2oe = pcs5; “Inverted pcs5# to create active high output enable for “the DTMF on POTS channel 2 dtmf1oe = pcs4; “Inverted pcs4# to create active high output enable for “the DTMF on POTS channel 1 txda = cctxda;...
Page 163 about.book Page 1 Monday, June 7, 1999 10:17 AM Index theory of operation, xvii Numerics troubleshooting, 1-8 Am186CC/CH/CU microcontroller, xvii block diagram, 2-9, 2-10 10BaseT Ethernet, 3-7 clocking, 2-11, 2-48 description, 2-8 power supply, 2-10 reset, 2-14 AD bus, 2-48 Am79C32A DSC circuit, 3-18 Am186CC/CH/CU CDP about, xiii...
Page 164 DCE, 2-31 10BaseT, 3-7 multidrop mode, 2-37 PCnet-ISA II, 3-9 debug and configuration circuitry, 2-39 expansion interfaces debug circuitry, 2-44 Am186, 2-49 debug headers, 2-42 development module, 2-51 development module 10BaseT Ethernet, 3-7 block diagram, 3-2 BOM, D-1 connecting to main board, 1-5...
Page 165 A-1 on main board, 2-4 installation main board, 1-2 quick start, 1-1 troubleshooting, 1-8 interface layout Am186, 2-49 development module, 3-3 development module, 2-51 main board, 2-2 DSLAC, 3-18 main board diagram, 2-3 DTMF, 3-25 expansion, 2-49 U interface status, 3-16...
Page 166 about.book Page 4 Monday, June 7, 1999 10:17 AM main, 2-20 SRAM, 2-20 microcontroller. See Am186CC/CH/CU microcontroller. main board block diagram, xv, 2-2 BOM, C-1 communication interface, 2-27 connecting a TIP, 1-6 notational conventions, xx connecting to a ROM-ICE, 1-7 connecting to the development module, debug and configuration, 2-39 panic bit, 2-45...
Page 167 about.book Page 5 Monday, June 7, 1999 10:17 AM SW11, 2-6 SW12, 2-6, 2-32, 2-33 SW13, 2-6, 2-45 SW14, 2-6 quick start, 1-1 SW15, 2-6, 2-45 SW16, 2-6 SW3, 2-5 SW4, 2-5 SW5, 2-5 R530 SW6, 2-5 DCE clocking, 2-32 SW7, 2-5 PCM clocking, 2-33 SW8, 2-5, 2-32...
Page 168 about.book Page 6 Monday, June 7, 1999 10:17 AM U interface, 3-15 LED status, 3-16 U20, 3-20 UART jumper settings, 2-4 UART. See RS-232 serial ports. circuit, 2-38 clock, 2-13 clock modes, 2-47 clocking, 2-48 external transceiver, 2-48 peripheral USB port, 2-37 pinstrap select, 2-6 using to connect to PC, 1-5 WWW support, iii...

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