AMD AM186EM User Manual
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AMD AM186EM User Manual

AMD AM186EM User Manual

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Am186™EM and Am188™EM
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Summary of Contents for AMD AM186EM

  • Page 1 Am186™EM and Am188™EM Microcontrollers User’s Manual...
  • Page 2 The information in this publication is believed to be accurate at the time of publication, but AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes at any time, without notice.
  • Page 3 Hotline and World Wide Web Support For answers to technical questions, AMD provides a toll-free number for direct access to our corporate applications hotline. Also available is the AMD World Wide Web home page and FTP site, which provides the latest E86 family product information, including technical information and data on upcoming product releases.

  • Page 5: Table Of Contents

    AMD DOCUMENTATION ........
  • Page 6 CHAPTER 5 CHIP SELECT UNIT OVERVIEW..........5-1 CHIP SELECT TIMING .
  • Page 7 7.4.1 Slave Mode Interrupt Nesting ......7-28 7.4.2 Slave Mode Interrupt Controller Registers ....7-28 7.4.3 Timer and DMA Interrupt Control Registers (T0INTCON, Offset 32h, T1INTCON, Offset 38h, T2INTCON, Offset 3Ah, DMA0CON, Offset 34h, DMA1CON, Offset 36h)
  • Page 8 CHAPTER 11 SYNCHRONOUS SERIAL INTERFACE 11.1 OVERVIEW..........11-1 11.1.1 Four-Pin Interface .
  • Page 9 LIST OF FIGURES Figure 1-1 Am186ES Microcontroller Block Diagram ......1-4 Figure 1-2 Am188ES Microcontroller Block Diagram .
  • Page 10 Figure 8-1 Timer 0 and Timer 1 Mode and Control Registers ..... . . 8-3 Figure 8-2 Timer 2 Mode and Control Register ........8-5 Figure 8-3 Timer Count Registers .
  • Page 11 LIST OF TABLES Table 2-1 Instruction Set ..........2-5 Table 2-2 Segment Register Selection Rules .
  • Page 12 Table of Contents...

  • Page 13: Preface

    PREFACE INTRODUCTION AND OVERVIEW DESIGN PHILOSOPHY AMD’s Am186 and Am188 family of microcontrollers is based on the architecture of the original 8086 and 8088 microcontrollers, and currently includes the 80C186, 80C188, ™ ™ 80L186, 80L188, Am186 EM, Am188 EM, Am186EMLV, Am188EMLV, Am186ES, Am188ES, Am186ESLV, Am188ESLV, Am186ER, and Am188ER microcontrollers.

  • Page 14: Amd Documentation

    To order literature, contact the nearest AMD sales office or call 800-222-9323 (in the U.S. and Canada) or direct dial from any location 512-602-5651. Literature is also available in postscript and PDF formats on the AMD web site. To access the AMD home page, go to http://www.amd.com. To download documents and software, ftp to ftp.amd.com and log on as anonymous using your E-mail address as a password.

  • Page 15: Features And Performance

    16-bit Reset Configuration register, enhanced chip-select functionality, 32 programmable I/Os, and additional interrupt signals. The Am186EM and Am188EM microcontrollers are part of the AMD E86 family of embedded microcontrollers and microprocessors based on the x86 architecture. The 16-bit members of the...

  • Page 16: Distinctive Characteristics

    The Am186EM and Am188EM microcontrollers are designed to meet the most common requirements of embedded products developed for the office automation, mass storage, communications, and general embedded markets. Applications include disk drives, hand- held terminals, fax machines, terminals, printers, photocopiers, feature phones, cellular phones, PBXs, multiplexers, modems, and industrial controls.
  • Page 17 Figure 1-1 Am186EM Microcontroller Block Diagram INT2/INTA0 INT3/INTA1/IRQ INT1/SELECT CLKOUTA INT4 INT0 TMROUT0 TMROUT1 TMRIN0 TMRIN1 DRQ0 DRQ1 CLKOUTB Timer Control Unit Unit 1 (WDT) Clock and Max Count B 20-Bit Source Interrupt Power Pointers Registers Control Unit Management 20-Bit Destination...
  • Page 18 Figure 1-2 Am188EM Microcontroller Block Diagram INT2/INTA0 INT3/INTA1/IRQ INT1/SELECT CLKOUTA INT4 INT0 TMROUT0 TMROUT1 TMRIN0 TMRIN1 DRQ0 DRQ1 CLKOUTB Timer Control Unit Unit 1 (WDT) Clock and Max Count B 20-Bit Source Interrupt Power Pointers Registers Control Unit Management Max Count A 20-Bit Destination Unit Registers...

  • Page 19: Application Considerations

    APPLICATION CONSIDERATIONS The integration enhancements of the Am186EM and Am188EM microcontrollers provide a high-performance, low-system-cost solution for 16-bit embedded microcontroller designs. The nonmultiplexed address bus (A19–A0) eliminates system-interface logic for memory devices, while the multiplexed address/data bus maintains the value of existing customer- specific peripherals and circuits within the upgraded design.

  • Page 20: Memory Interface

    1.3.2 Memory Interface The integrated memory controller logic of the Am186EM and Am188EM microcontrollers provides a direct address bus interface to memory devices. The use of an external address latch controlled by the address latch enable (ALE) signal is not required.

  • Page 21: Programming

    CHAPTER PROGRAMMING All members of the Am186 and Am188 family of microcontrollers, including the Am186EM and Am188EM, contain the same basic set of registers, instructions, and addressing modes, and are compatible with the original industry-standard 186/188 parts. REGISTER SET The base architecture of the Am186EM and Am188EM microcontrollers has 14 registers, as shown in Figure 2-1.

  • Page 22: Processor Status Flags Register

    Figure 2-1 Register Set 16-Bit Special Register 16-Bit Register Name Functions Register Name Code Segment Byte Multiply/Divide Addressable I/O Instructions Data Segment (8-Bit Loop/Shift/Repeat/Count Register Stack Segment Names Extra Segment Shown) Base Registers Segment Registers Base Pointer Source Index Index Registers Destination Index Processor Status Flags FLAGS...

  • Page 23: Memory Organization And Address Generation

    Bit 9: Interrupt-Enable Flag (IF)—When set, enables maskable interrupts to cause the CPU to transfer control to a location specified by an interrupt vector. Bit 8: Trace Flag (TF)—When set, a trace interrupt occurs after instructions execute. TF is cleared by the trace interrupt after the processor status flags are pushed onto the stack. The trace service routine can continue tracing by popping the flags back with an interrupt return (IRET) instruction.

  • Page 24: I/O Space

    I/O space with either an 8-bit port address specified in the instruction, or a 16-bit port address in the DX register. Eight-bit port addresses are zero-extended so that A15–A8 are Low. I/O port addresses 00F8h through 00FFh are reserved. The Am186EM and Am188EM microcontrollers provide specific instructions for addressing I/O space.

  • Page 25: Table 2-1 Instruction Set

    Table 2-1 Instruction Set Mnemonic Instruction Name ASCII adjust for addition ASCII adjust for division ASCII adjust for multiplication ASCII adjust for subtraction Add byte or word with carry Add byte or word Logical AND byte or word BOUND Detects values outside prescribed range CALL Call procedure Convert byte to word...
  • Page 26 Mnemonic Instruction Name JB/JNAE Jump if below/not above or equal JBE/JNA Jump if below or equal/not above Jump if carry JCXZ Jump if register CX = 0 JE/JZ Jump if equal/zero JG/JNLE Jump if greater/not less or equal JGE/JNL Jump if greater or equal/not less JL/JNGE Jump if less/not greater or equal JLE/JNG...
  • Page 27 Mnemonic Instruction Name Logical Inclusive OR byte or word Output byte or word Pop word off stack POPA Pop all general register off stack POPF Pop flags off stack PUSH Push word onto stack PUSHA Push all general registers onto stack PUSHF Push flags onto stack Rotate left through carry byte or word...

  • Page 28: Segments

    All string instruction references that use the DI register as an index DATA TYPES The Am186EM and Am188EM microcontrollers directly support the following data types: Integer—A signed binary numeric value contained in an 8-bit byte or a 16-bit word. All operations assume a two’s complement representation.

  • Page 29: Figure 2-5 Supported Data Types

    Pointer—A 16-bit or 32-bit quantity, composed of a 16-bit offset component or a 16-bit segment base component plus a 16-bit offset component. In general, individual data elements must fit within defined segment limits. Figure 2-5 graphically represents the data types supported by the Am186EM and Am188EM microcontrollers. Figure 2-5...

  • Page 30: Addressing Modes

    ADDRESSING MODES The Am186EM and Am188EM microcontrollers use eight categories of addressing modes to specify operands. Two addressing modes are provided for instructions that operate on register or immediate operands; six modes are provided to specify the location of an operand in a memory segment.

  • Page 31: System Overview

    CHAPTER SYSTEM OVERVIEW This chapter contains descriptions of the Am186EM and Am188EM microcontroller pins, the bus interface unit, the clock and power management unit, and power-save operation. PIN DESCRIPTIONS Pin Terminology The following terms are used to describe the pins: Input—An input-only pin.
  • Page 32 During a bus hold or reset condition, the address and data bus is in a high-impedance state. During a power-on reset, the address and data bus pins (AD15–AD0 for the Am186EM, AO15–AO8 and AD7–AD0 for the Am188EM) can also be used to load system configuration information into the internal Reset Configuration register.
  • Page 33 . BHE does not need to be latched. BHE floats during bus hold and reset. On the Am186EM microcontroller, WLB and WHB implement the functionality of BHE and AD0 for high and low byte write enables. BHE/ADEN also signals DRAM refresh cycles when using the multiplexed address and data (AD) bus.
  • Page 34 For more information, see the HLDA pin description. The Am186EM and Am188EM microcontrollers’ HOLD latency time, that is, the time between HOLD request and HOLD acknowledge, is a function of the activity occurring in the processor when the HOLD...
  • Page 35 HOLD latency can be as great as 4 bus cycles. This occurs if a DMA word transfer operation is taking place (Am186EM microcontroller only) from an odd address to an odd address. This is a total of 16 clock cycles or more if wait states are required.
  • Page 36 INT3/INTA1/IRQ Maskable Interrupt Request 3 (input, asynchronous) Interrupt Acknowledge 1 (output, synchronous) Slave Interrupt Request (output, synchronous) INT3—This pin indicates to the microcontroller that an interrupt request has occurred. If the INT3 pin is not masked, the microcontroller then transfers program execution to the location specified by the INT3 vector in the microcontroller interrupt vector table.
  • Page 37 MCS3/RFSH Midrange Memory Chip Select 3 (output, synchronous, internal pullup) Automatic Refresh (output, synchronous) MCS3—This pin indicates to the system that a memory access is in progress to the fourth region of the midrange memory block. The base address and size of the midrange memory block are programmable. MCS3 is held High during a bus hold condition.
  • Page 38 Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note: PCS4 is not available on the Am186EM and Am188EM micro- controllers. Note also that each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers.
  • Page 39 1. These pins are used by emulators. (Emulators also use S2–S0 , RES , NMI, CLKOUTA, BHE , ALE, AD15–AD0, and A16–A0. 2. These pins revert to normal operation if BHE/ADEN (Am186EM) or RFSH2/ADEN (Am188EM) is held Low during power-on reset.
  • Page 40 1. These pins are used by emulators. (Emulators also use S2–S0 , RES , NMI, CLKOUTA, BHE , ALE, AD15–AD0, and A16–A0. 2. These pins revert to normal operation if BHE/ADEN (Am186EM) or RFSH2/ADEN (Am188EM) is held Low during power-on reset.
  • Page 41 Read Strobe (output, synchronous, three-state) RD—This pin indicates to the system that the microcontroller is performing a memory or I/O read cycle. RD is guaranteed not to be asserted before the address and data bus is floated during the address- to-data transition.
  • Page 42 Bus Cycle Interrupt acknowledge Read data from I/O Write data to I/O Halt Instruction fetch Read data from memory Write data to memory None (passive) S6/CLKDIV2 Bus Cycle Status Bit 6 (output, synchronous) Clock Divide by 2 (input, internal pullup) S6—During the second and remaining periods of a cycle (t , and t this pin is asserted High to indicate a DMA-initiated bus cycle.
  • Page 43 SRDY Synchronous Ready (input, synchronous, level-sensitive) This pin indicates to the microcontroller that the addressed memory space or I/O device will complete a data transfer. The SRDY pin accepts an active-High input synchronized to CLKOUTA. Using SRDY instead of ARDY allows a relaxed system timing because of the elimination of the one-half clock period required to internally synchronize ARDY.
  • Page 44 This pin should be allowed to float or should be pulled High at reset. If this pin is Low at the negation of reset, the Am186EM and Am188EM microcontrollers will enter a reserved clock test mode.

  • Page 45: Pins That Are Used By Emulators

    Emulators require that S6/CLKDIV2 and UZI be configured in their normal functionality, that is, as S6 and UZI. If BHE/ADEN (on the Am186EM) or RFSH2/ADEN (on the Am188EM) is held Low during the rising edge of RES, S6 and UZI are configured in their normal functionality, instead of as PIOs, at reset.

  • Page 46: Bus Operation

    For systems where power consumption is a concern, it is possible to disable the address from being driven on the AD bus on the Am186EM microcontroller and on the AD and AO buses on the Am188EM microcontroller during the normal address portion of the bus cycle for accesses to UCS and/or LCS address spaces.
  • Page 47 A19–A0 Address AD15–AD0 Address Data (Read) AD15–AD0 Address Data (Write) LCS or UCS MCSx, PCSx Figure 3-2 Am186EM Microcontroller—Read and Write with Address Bus Disable In Effect Address Data Phase Phase CLKOUTA A19–A0 Address AD7–AD0 Data (Read) AD15–AD8 Data (Read) AD15–AD0...
  • Page 48 Figure 3-3 Am188EM Microcontroller Address Bus—Normal Read and Write Operation Address Data Phase Phase CLKOUTA A19–A0 Address AD7–AD0 Address Data (Read) AO15–AO8 Address (Read or Write) AD7–AD0 Address Data (Write) LCS or UCS MCSx, PCSx Figure 3-4 Am188EM Microcontroller—Read and Write with Address Bus Disable In Effect Address Data Phase...

  • Page 49: Bus Interface Unit

    Am188EM microcontrollers provide an enhanced bus interface unit with the following features: A nonmultiplexed address bus Separate byte write enables for high and low bytes in the Am186EM microcontroller Pseudo-Static RAM (PSRAM) support The standard 80C186 multiplexed address and data bus requires system-interface logic and an external address latch.

  • Page 50: Clock And Power Management Unit

    In a traditional 80C186/188 design, the crystal frequency is twice that of the desired internal clock. Because of the internal PLL on the Am186EM and Am188EM microcontrollers, the internal clock generated by the microcontroller (CLKOUTA) is the same frequency as the crystal.

  • Page 51: Figure 3-5 Oscillator Configurations

    C must be determined by the designer and are dependent on the characteristics of the chosen crystal and board design. Figure 3-5 Oscillator Configurations Crystal Crystal Am186EM/ Am188EM Note 1 Microcontroller a. Inverting Amplifier Configuration 200 pF b. Crystal Configuration...

  • Page 52: External Source Clock

    3.4.3 External Source Clock Alternately, the internal oscillator can be driven from an external clock source. This source should be connected to the input of the inverting amplifier (X1) with the output (X2) not connected. 3.4.4 System Clocks Figure 3-6 shows the organization of the clocks. The 80C186 microcontroller system clock has been renamed CLKOUTA.

  • Page 53: Peripheral Control Block

    Reads to the PCB should be done as word reads. Code written in this manner will run correctly on the Am188EM microcontroller and on the Am186EM microcontroller. Unaligned reads and writes to the PCB result in unpredictable behavior on both the Am186EM and Am188EM microcontrollers.
  • Page 54 Figure 4-1 Peripheral Control Block Register Map Offset (Hexadecimal) Register Name Peripheral Control Block Relocation Register Reset Configuration Register Chapter 4 Processor Release Level Register PDCON Register Enable RCU Register Chapter 6 Clock Prescaler Register Memory Partition Register DMA 1 Control Register DMA 1 Transfer Count Register DMA 1 Destination Address High Register DMA 1 Destination Address Low Register...
  • Page 55 Offset (Hexadecimal) Register Name PIO Data 1 Register PIO Direction 1 Register PIO Mode 1 Register Chapter 12 PIO Data 0 Register PIO Direction 0 Register PIO Mode 0 Register Timer 2 Mode/Control Register Timer 2 Maxcount Compare A Register Timer 2 Count Register Timer 1 Mode/Control Register Timer 1 Maxcount Compare B Register...

  • Page 56: Peripheral Control Block Relocation Register

    4.1.1 Peripheral Control Block Relocation Register (RELREG, Offset FEh) The peripheral control block is mapped into either memory or I/O space by programming the Peripheral Control Block Relocation (RELREG) register (see Figure 4-2). This register is a 16-bit register at offset FEh from the control block base address. The RELREG register provides the upper 12 bits of the base address of the control block.

  • Page 57: Reset Configuration Register (Rescon, Offset F6H)

    The Reset Configuration (RESCON) register (see Figure 4-3) in the peripheral control block latches system-configuration information that is presented to the processor on the address/ data bus (AD15–AD0 for the Am186EM or AO15–AO8 and AD7–AD1 for the Am188EM) during the rising edge of reset. The interpretation of this information is system-specific. The processor does not impose any predetermined interpretation, but simply provides a means for communicating this information to software.

  • Page 58: Processor Release Level Register (Prl, Offset F4H)

    Bits 15–8: Processor Release Level (PRL)—This field is an 8-bit, read-only identification number that specifies the processor release level. The values of the PRL field for the Am186EM and Am188EM microcontrollers are shown in Table 4-1. Each release level is numbered one higher than the previous level.

  • Page 59: Power-Save Control Register (Pdcon, Offset F0H)

    4.1.4 Power-Save Control Register (PDCON, Offset F0h) Figure 4-5 Power-Save Control Register (PDCON, offset F0h) 0 0 0 0 0 0 0 0 PSEN The value of the PDCON register is 0000h at reset. Bit 15: Enable Power-Save Mode (PSEN)—When set to 1, enables Power-Save mode and divides the internal operating clock by the value in F2–F0.

  • Page 60: Initialization And Processor Reset

    Processor initialization or startup is accomplished by driving the RES input pin Low. RES must be Low during power-up to ensure proper device initialization. RES forces the Am186EM and Am188EM microcontrollers to terminate all execution and local bus activity. No instruction or bus activity occurs as long as RES is active.

  • Page 61: Table 4-1 Table

    Table 4-2 Initial Register State After Reset Value at Register Name Mnemonic Reset Comments Processor Status Flags F002h Interrupts disabled Instruction Pointer 0000h Code Segment FFFFh Boot address is FFFF0h Data Segment 0000h DS = ES = SS = 0000h Extra Segment 0000h Stack Segment...
  • Page 62 4-10 Peripheral Control Block...

  • Page 63: Chapter 5 Chip Select Unit

    CPU or by the integrated DMA unit. The Am186EM and Am188EM microcontrollers provide six chip select outputs for use with memory devices and six more for use with peripherals in either memory space or I/O space.

  • Page 64: Chip Select Timing

    The MCS3–MCS0 and PCS chip selects assert with the AD bus. READY AND WAIT-STATE PROGRAMMING The Am186EM and Am188EM microcontrollers can be programmed to sense a ready signal for each of the peripheral or memory chip select lines. The ready signal can be either the ARDY or SRDY signal.

  • Page 65: Chip Select Registers

    When overlapping an additional chip select with either the LCS or UCS chip selects, it must be noted that setting the Disable Address (DA) bit in the LMCS or UMCS register will disable the address from being driven on the AD bus for all accesses for which the associated chip select is asserted, including any accesses for which multiple chip selects assert.

  • Page 66: Upper Memory Chip Select Register (Umcs, Offset A0H)

    5.5.1 Upper Memory Chip Select Register (UMCS, Offset A0h) The Am186EM and Am188EM microcontrollers provide the UCS chip select pin for the top of memory. On reset, the microcontroller begins fetching and executing instructions starting at memory location FFFF0h, so upper memory is usually used as instruction memory. To...
  • Page 67 DA bit is set to 1 in either the UMCS or LMCS register. If BHE/ADEN (on the Am186EM) or RFSH2/ADEN (on the Am188EM) is held Low on the rising edge of RES, then AD15–AD0 is always driven regardless of the DA setting. This configures AD15–AD0 to be enabled regardless of the setting of DA.

  • Page 68: Low Memory Chip Select Register (Lmcs, Offset A2H)

    LMCS register is reduced compared to the 80C186 and 80C188 microcontrollers. Consequently, the number of programmable bits has been reduced from eight bits in the 80C186 and 80C188 microcontrollers to three bits in the Am186EM and Am188EM microcontrollers.
  • Page 69 Memory Chip Select register (UMCS) or the Low Memory Chip Select register (LMCS). If BHE/ADEN (on the Am186EM) or RFSH2/ADEN (on the Am188EM) is held Low on the rising edge of RES, then AD15–AD0 is always driven regardless of the DA setting. This configures AD15–AD0 to be enabled regardless of the setting of DA.

  • Page 70: Midrange Memory Chip Select Register (Mmcs, Offset A6H)

    5.5.3 Midrange Memory Chip Select Register (MMCS, Offset A6h) The Am186EM and Am188EM microcontrollers provide four chip select pins, MCS3–MCS0, for use within a user-locatable memory block. The base address of the memory block can be located anywhere within the 1-Mbyte memory address space, exclusive of the areas associated with the UCS and LCS chip selects (and, if they are mapped to memory, the address range of the Peripheral Chip Selects, PCS6–PCS5 and PCS3–PCS0).
  • Page 71 Bits 8–3: Reserved—Set to 1. Bit 2: Ready Mode (R2)—The R2 bit is used to configure the ready mode for the MCS chip selects. If R2 is set to 0, external ready is required. If R2 is set to 1, external ready is ignored.

  • Page 72: Pcs And Mcs Auxiliary Register (Mpcs, Offset A8H)

    5.5.4 PCS and MCS Auxiliary Register (MPCS, Offset A8h) The PCS and MCS Auxiliary (MPCS) register (see Figure 5-4) differs from the other chip select control registers in that it contains fields that pertain to more than one type of chip select.
  • Page 73 Bit 7: Pin Selector (EX)—This bit determines whether the PCS6–PCS5 pins are configured as chip selects or as alternate outputs for A2–A1. When this bit is set to 1, PCS6–PCS5 are configured as peripheral chip select pins. When EX is set to 0, PCS5 becomes address bit A1 and PCS6 becomes address bit A2.

  • Page 74: Peripheral Chip Select Register (Pacs, Offset A4H)

    The Am186EM and Am188EM microcontrollers provide six chip selects, PCS6–PCS5 and PCS3–PCS0, for use within a user-locatable memory or I/O block. (PCS4 is not implemented on the Am186EM and Am 188EM microcontrollers.) The base address of the memory block can be located anywhere within the 1-Mbyte memory address space, exclusive of the areas associated with the UCS, LCS, and MCS chip selects, or they can be configured to access the 64-Kbyte I/O space.

  • Page 75: Table 4-3 Table

    Table 5-5 PCS Address Ranges Range PCS Line High PCS0 Base Address Base Address+255 PCS1 Base Address+256 Base Address+511 PCS2 Base Address+512 Base Address+767 PCS3 Base Address+768 Base Address+1023 Reserved N/A PCS5 Base Address+1280 Base Address+1535 PCS6 Base Address+1536 Base Address+1791 Bits 6–4: Reserved—Set to 1.
  • Page 76 5-14 Chip Select Unit...

  • Page 77: Chapter 6 Refresh Control Unit

    CHAPTER REFRESH CONTROL UNIT OVERVIEW The Refresh Control Unit (RCU) automatically generates refresh bus cycles. After a programmable period of time, the RCU generates a memory read request to the bus interface unit. The RCU is fixed to three wait states for the PSRAM auto refresh mode. The Refresh Control Unit operates off the processor internal clock.

  • Page 78: Clock Prescaler Register (Cdram, Offset E2H)

    6.1.2 Clock Prescaler Register (CDRAM, Offset E2h) Figure 6-2 Clock Prescaler Register (CDRAM, offset E2h) 0 0 0 0 0 RC8–RC0 The CDRAM register is undefined on reset. Bits 15–9: Reserved—Read back as 0. Bits 8–0: Refresh Counter Reload Value (RC8–RC0)—Contains the value of the desired clock count interval between refresh cycles.

  • Page 79: Interrupt Control Unit

    The internal interrupt controller arranges these requests by priority and presents them one at a time to the CPU. There are six external interrupt sources on the Am186EM and Am188EM microcontrollers— five maskable interrupt pins (INT4–INT0) and the non-maskable interrupt (NMI) pin. There are six internal interrupt sources that are not connected to external pins—three timers, two...
  • Page 80 Interrupt types 00h through 07h and all software interrupts (the INT instruction) are non- maskable. The non-maskable interrupts are not affected by the setting of the IF flag. The Am186EM and Am188EM microcontrollers provide two methods for masking and unmasking the maskable interrupt sources. Each interrupt source has an interrupt control register that contains a mask bit specific to that interrupt.
  • Page 81 Interrupt types 00h, 01h, 03h, 04h, 05h, 06h, and 07h are software exception interrupts. Software exceptions are not maskable and are not affected by the setting of the IF flag. Table 7-1 Am186EM and Am188EM Microcontroller Interrupt Types Interrupt Vector Table Overall...

  • Page 82: Interrupt Conditions And Sequence

    7.1.2 Interrupt Conditions and Sequence Interrupts are generally serviced as follows. 7.1.2.1 Non-Maskable Interrupts Non-maskable interrupts—the trace interrupt, the NMI interrupt, and software interrupts [both user-defined (INT) and software exceptions]—are serviced regardless of the setting of the interrupt enable flag (IF) in the processor status flags. 7.1.2.2 Maskable Hardware Interrupts In order for maskable hardware interrupt requests to be serviced, the IF flag must be set...

  • Page 83: Interrupt Priority

    7.1.3 Interrupt Priority Table 7-1 shows the predefined types and overall priority structure for the Am186EM and Am188EM microcontrollers. Non-maskable interrupts (interrupt types 0–7) are always higher priority than maskable interrupts. Maskable interrupts have a programmable priority that can override the default priorities relative to one another.

  • Page 84: Software Exceptions, Traps, And Nmi

    ESC instruction that caused the exception. If a segment override prefix preceded the ESC instruction, the return address points to the segment override prefix. Note: All numeric coprocessor opcodes cause a trap. The Am186EM and Am188EM microcontrollers do not support the numeric coprocessor interface.

  • Page 85: Interrupt Acknowledge

    Interrupt acknowledge bus cycles have the following characteristics: The two interrupt acknowledge cycles are internally locked. (There is no LOCK pin on the Am186EM and Am188EM microcontrollers.) Two idle states are always inserted between the two cycles. Wait states are inserted if READY is not returned to the processor.

  • Page 86: Interrupt Controller Reset Conditions

    7.1.6 Interrupt Controller Reset Conditions On reset, the interrupt controller performs the following nine actions: 1. All special fully nested mode (SFNM) bits are reset, implying fully nested mode. 2. All priority (PR) bits in the various control registers are set to 1. This places all sources at the lowest priority (level 7).

  • Page 87: Master Mode Operation

    Figure 7-2 Fully Nested (Direct) Mode Interrupt Controller Connections Interrupt Source INT0 Interrupt Source INT1 Am186EM or Am188EM Microcontroller Interrupt Source INT2 Interrupt Source INT3 Interrupt Source...

  • Page 88: Cascade Mode

    7.2.2 Cascade Mode The Am186EM and Am188EM microcontrollers have five interrupt pins, two of which (INT2 and INT3) have dual functions. In fully nested mode, the five pins are used as direct interrupt inputs and the corresponding interrupt types are generated internally. In cascade mode, four of the five pins can be configured into interrupt input and dedicated acknowledge signal pairs.

  • Page 89: Special Fully Nested Mode

    Am186EM or Am188EM microcontroller interrupt request pin. As a result, if the external interrupt controller receives a higher-priority interrupt, its interrupt is not recognized by the microcontroller until the in-service bit is reset.

  • Page 90: Master Mode Interrupt Controller Registers

    MASTER MODE INTERRUPT CONTROLLER REGISTERS The interrupt controller registers for master mode are shown in Table 7-2. All the registers can be read and written unless otherwise specified. Registers can be redefined in slave mode. See section 7.4 on page 7-28 for detailed information regarding slave mode register usage.

  • Page 91: Int0 And Int1 Control Registers (I0Con, Offset 38H, I1Con, Offset 3Ah) (Master Mode)

    7.3.1 INT0 and INT1 Control Registers (I0CON, Offset 38h, I1CON, Offset 3Ah) (Master Mode) The INT0 interrupt is assigned to interrupt type 0Ch. The INT1 interrupt is assigned to interrupt type 0Dh. When cascade mode is enabled for INT0 by setting the C bit of I0CON to 1, the INT2 pin becomes INTA0, the interrupt acknowledge for INT0.

  • Page 92: Table 7-3 Priority Level

    Table 7-3 Priority Level Priority PR2–PR0 (High) 0 0 0 0b 0 0 1b 0 1 0b 0 1 1b 1 0 0b 1 0 1b 1 1 0b (Low) 7 1 1 1b 7-14 Interrupt Control Unit...

  • Page 93: Int2 And Int3 Control Registers (I2Con, Offset 3Ch, I3Con, Offset 3Eh) (Master Mode)

    7.3.2 INT2 and INT3 Control Registers (I2CON, Offset 3Ch, I3CON, Offset 3Eh) (Master Mode) The INT2 interrupt is assigned to interrupt type OEh. The INT3 interrupt is assigned to interrupt type 0Fh. The INT2 and INT3 pins can be configured as interrupt acknowledge pins INTA0 and INTA1 when cascade mode is implemented.

  • Page 94: Int4 Control Register (I4Con, Offset 40H) (Master Mode)

    INT4 Control Register (I4CON, Offset 40h) (Master Mode) The Am186EM and Am188EM microcontrollers provide INT4, an additional external interrupt pin. This input behaves like INT3–INT0 on the 80C186/188 microcontroller with the exception that INT4 is only intended for use as a nested-mode interrupt source.

  • Page 95: Timer And Dma Interrupt Control Registers (Tcucon, Offset 32H, Dma0Con, Offset 34H, Dma1Con, Offset 36H) (Master Mode)

    7.3.4 Timer and DMA Interrupt Control Registers (TCUCON, Offset 32h, DMA0CON, Offset 34h, DMA1CON, Offset 36h) (Master Mode) The three timer interrupts are assigned to interrupt type 08h, 12h, and 13h. All three timer interrupts are configured through TCUCON, offset 32h. The DMA0 interrupt is assigned to interrupt type 0Ah.

  • Page 96: Watchdog Timer Interrupt Control Register

    The value of WDCON at reset is 000Fh. Bits 15–5: Reserved—Set to 0. Bit 4: Reserved— Must be set to 0 to ensure proper operation of the Am186EM and Am188EM microcontrollers. Bit 3: Mask (MSK)—This bit determines whether the watchdog timer can cause an interrupt.

  • Page 97: Serial Port Interrupt Control Register (Spicon, Offset 44H)

    7.3.6 Serial Port Interrupt Control Register (SPICON, Offset 44h) (Master Mode) The Serial Port Interrupt Control register controls the operation of the asynchronous serial port interrupt source (SPI, bit 10 in the Interrupt Request register). This interrupt is assigned to interrupt type 14h. The control register format is shown in Figure 7-9. Figure 7-9 Serial Port Interrupt Control Register (SPICON, offset 44h) Reserved...

  • Page 98: Interrupt Status Register (Intsts, Offset 30H)

    7.3.7 Interrupt Status Register (INTSTS, Offset 30h) (Master Mode) The Interrupt Status (INTSTS) register indicates the interrupt request status of the three timers. Figure 7-10 Interrupt Status Register (INTSTS, offset 30h) Reserved DHLT TMR2 TMR0 TMR1 Bit 15: DMA Halt (DHLT)—When set to 1, halts any DMA activity. This pin is automatically set to 1 when non-maskable interrupts occur and is reset when an IRET instruction is executed.

  • Page 99: Interrupt Request Register (Reqst, Offset 2Eh)

    A read from this register yields the status of these bits. The Interrupt Request register is a read-only register. The format of the REQST register is shown in Figure 7-11. The Am186EM and Am188EM microcontrollers define three new bits to report the state of INT4, the Watchdog Timer, and the asynchronous serial port.

  • Page 100: In-Service Register (Inserv, Offset 2Ch)

    In-Service Register (INSERV, Offset 2Ch) (Master Mode) The Am186EM and Am188EM microcontrollers define three new bits to report the in-service state of INT4, the Virtual Watchdog Timer, and the asynchronous serial port. The format of the modified In-Service register is shown in Figure 7-12.

  • Page 101: Priority Mask Register (Primsk, Offset 2Ah) (Master Mode)

    7.3.10 Priority Mask Register (PRIMSK, Offset 2Ah) (Master Mode) The Priority Mask (PRIMSK) register provides the value that determines the minimum priority level at which maskable interrupts can generate an interrupt. Figure 7-13 Priority Mask Register (PRIMSK, offset 2Ah) 0 0 0 0 0 0 PRM2 PRM1...

  • Page 102: Interrupt Mask Register (Imask, Offset 28H) (Master Mode)

    7.3.11 Interrupt Mask Register (IMASK, Offset 28h) (Master Mode) The Am186EM and Am188EM microcontrollers define three new bits to report the mask state of the INT4 Control, Watchdog Timer Interrupt Control, and Serial Port Interrupt Control registers. The Interrupt Mask (IMASK) register is a read/write register. Programming a bit in the IMASK register has the effect of programming the MSK bit in the associated control register.

  • Page 103: Poll Status Register (Pollst, Offset 26H) (Master Mode)

    7.3.12 Poll Status Register (POLLST, Offset 26h) (Master Mode) The Poll Status (POLLST) register mirrors the current state of the Poll register. The POLLST register can be read without affecting the current interrupt request. But when the Poll register is read, the current interrupt is acknowledged and the next interrupt takes its place in the Poll register.

  • Page 104: Poll Register (Poll, Offset 24H) (Master Mode)

    7.3.13 Poll Register (POLL, Offset 24h) (Master Mode) When the Poll register is read, the current interrupt is acknowledged and the next interrupt takes its place in the Poll register. The Poll Status register mirrors the current state of the Poll register, but the Poll Status register can be read without affecting the current interrupt request.

  • Page 105: End-Of-Interrupt Register (Eoi, Offset 22H) (Master Mode)

    7.3.14 End-of-Interrupt Register (EOI, Offset 22h) (Master Mode) The End-of-Interrupt (EOI) register is a write-only register. The in-service flags in the In- Service register (see section 7.3.9 on page 7-22) are reset by writing to the EOI register. Before executing the IRET instruction that ends an interrupt service routine (ISR), the ISR should write to the EOI register to reset the IS bit for the interrupt.

  • Page 106: Slave Mode Operation

    SLAVE MODE OPERATION When slave mode is used, the microcontroller’s internal interrupt controller is used as a slave controller to an external master interrupt controller. The internal interrupts are monitored by the internal interrupt controller, while the external controller functions as the system master interrupt controller.

  • Page 107: Timer And Dma Interrupt Control Registers

    7.4.3 Timer and DMA Interrupt Control Registers (T0INTCON, Offset 32h, T1INTCON, Offset 38h, T2INTCON, Offset 3Ah, DMA0CON, Offset 34h, DMA1CON, Offset 36h) (Slave Mode) In slave mode, there are three separate registers for the three timers. In master mode, all three timers are masked and prioritized in one register, TCUCON.

  • Page 108: Interrupt Status Register (Intsts, Offset 30H) (Slave Mode)

    7.4.4 Interrupt Status Register (INTSTS, Offset 30h) (Slave Mode) The Interrupt Status register controls DMA activity when non-maskable interrupts occur and indicates the current interrupt status of the three timers. Figure 7-20 Interrupt Status Register (INTSTS, offset 30h) Reserved DHLT TMR1 TMR2 TMR0...

  • Page 109: Interrupt Request Register (Reqst, Offset 2Eh) (Slave Mode)

    7.4.5 Interrupt Request Register (REQST, Offset 2Eh) (Slave Mode) The internal interrupt sources have interrupt request bits inside the interrupt controller. A read from this register yields the status of these bits. The Interrupt Request register is a read-only register. The format of the Interrupt Request register is shown in Figure 7-21. For internal interrupts (D1, D0, TMR2, TMR1, and TMR0), the corresponding bit is set to 1 when the device requests an interrupt.

  • Page 110: In-Service Register (Inserv, Offset 2Ch) (Slave Mode)

    7.4.6 In-Service Register (INSERV, Offset 2Ch) (Slave Mode) The format of the In-Service register is shown in Figure 7-22. The bits in the In-Service register are set by the interrupt controller when the interrupt is taken. The in-service bits are cleared by writing to the End-of-Interrupt (EOI) register. Figure 7-22 In-Service Register (INSERV, offset 2Ch) Reserved...

  • Page 111: Priority Mask Register (Primsk, Offset 2Ah) (Slave Mode)

    7.4.7 Priority Mask Register (PRIMSK, Offset 2Ah) (Slave Mode) The format of the Priority Mask register is shown in Figure 7-23. The Priority Mask register provides the value that determines the minimum priority level at which maskable interrupts can generate an interrupt. Figure 7-23 Priority Mask Register (PRIMSK, offset 2Ah) Reserved...

  • Page 112: Interrupt Mask Register (Imask, Offset 28H) (Slave Mode)

    7.4.8 Interrupt Mask Register (IMASK, Offset 28h) (Slave Mode) The format of the Interrupt Mask register is shown in Figure 7-24. The Interrupt Mask register is a read/write register. Programming a bit in the Interrupt Mask register has the effect of programming the MSK bit in the associated control register.

  • Page 113: Specific End-Of-Interrupt Register (Eoi, Offset 22H)

    7.4.9 Specific End-of-Interrupt Register (EOI, Offset 22h) (Slave Mode) In slave mode, a write to the EOI register resets an in-service bit of a specific priority. The user supplies a three-bit priority-level value that points to an in-service bit to be reset. The command is executed by writing the correct value in the Specific EOI register at offset 22h.

  • Page 114: Interrupt Vector Register (Intvec, Offset 20H) (Slave Mode)

    7.4.10 Interrupt Vector Register (INTVEC, Offset 20h) (Slave Mode) Vector generation in slave mode is exactly like that of an 8259A or 82C59A slave. The interrupt controller generates an 8-bit interrupt type that the CPU shifts left two bits (multiplies by four) to generate an offset into the interrupt vector table. Figure 7-26 Interrupt Vector Register (INTVEC, offset 20h) T4–T0...

  • Page 115: Timer Control Unit

    TIMER CONTROL UNIT OVERVIEW There are three 16-bit programmable timers in the Am186EM and Am188EM microcontrollers. Timers 0 and 1 are highly versatile and are each connected to two external pins (each one has an input and an output). These two timers can be used to count or time external events, or they can be used to generate nonrepetitive or variable-duty-cycle waveforms.

  • Page 116: Timer Operating Frequency

    Each timer also has a corresponding maximum-count register that defines the maximum value for the timer. When the timer reaches the maximum value, it resets to 0 during the same clock cycle. (The value in the timer-count register never equals the maximum-count register.) In addition, timers 0 and 1 have a secondary maximum-count register.

  • Page 117: Timer 0 And Timer 1 Mode And Control Registers (T0Con, Offset 56H, T1Con, Offset 5Eh)

    8.2.2 Timer 0 and Timer 1 Mode and Control Registers (T0CON, Offset 56h, T1CON, Offset 5Eh) These registers control the functionality of timer 0 and timer 1. See Figure 8-1. Figure 8-1 Timer 0 and Timer 1 Mode and Control Registers (T0CON, T1CON, offsets 56h and 5Eh) 0 0 0 0 0 CONT...
  • Page 118 Bit 2: External Clock Bit (EXT)—When set to 1, an external clock is used. When set to 0, the internal clock is used. Bit 1: Alternate Compare Bit (ALT)—When set to 1, the timer counts to maxcount compare A, then resets the count register to 0. Then the timer counts to maxcount compare B, resets the count register to zero, and starts over with maxcount compare A.

  • Page 119: Timer 2 Mode And Control Register (T2Con, Offset 66H)

    8.2.3 Timer 2 Mode and Control Register (T2CON, Offset 66h) This register controls the functionality of timer 2. See Figure 8-2. Figure 8-2 Timer 2 Mode and Control Register (T2CON, offset 66h) 0 0 0 0 0 CONT The value of T2CON at reset is 0000h. Bit 15: Enable Bit (EN)—When EN is set to 1, the timer is enabled.

  • Page 120: Timer Count Registers (T0Cnt, Offset 50H, T1Cnt, Offset 58H, T2Cnt, Offset 60H)

    8.2.4 Timer Count Registers (T0CNT, Offset 50h, T1CNT, Offset 58h, T2CNT, Offset 60h) These registers can be incremented by one every four internal processor clocks. Timer 0 and timer 1 can also be configured to increment based on the TMRIN0 and TMRIN1 external signals, or they can be prescaled by timer 2.

  • Page 121: Timer Maxcount Compare Registers (T0Cmpa, Offset 52H, T0Cmpb, Offset 54H, T1Cmpa, Offset 5Ah, T1Cmpb, Offset 5Ch, T2Cmpa, Offset 62H)

    8.2.5 Timer Maxcount Compare Registers (T0CMPA, Offset 52h, T0CMPB, Offset 54h, T1CMPA, Offset 5Ah, T1CMPB, Offset 5Ch, T2CMPA, Offset 62h) These registers serve as comparators for their associated count registers. Timer 0 and timer 1 each have two maximum count compare registers. See Figure 8-4. Timer 0 and timer 1 can be configured to count and compare to register A and then count and compare to register B.
  • Page 122 Timer Control Unit...

  • Page 123: Dma Controller

    (e.g., memory to I/O) or within the same space (e.g., memory-to-memory or I/O-to-I/O). Either bytes or words can be transferred to or from even or odd addresses on the Am186EM. (The Am188EM microcontroller does not support word transfers.) Two bus cycles (a minimum of eight clocks) are necessary for each data transfer.

  • Page 124: Programmable Dma Registers

    Figure 9-1 DMA Unit Block Diagram Adder Control 20-bit Adder/Subtractor Logic Timer Request DRQ1 Request Selection DRQ0 Logic Transfer Counter Ch. 1 Destination Address Ch. 1 Source Address Ch. 1 Control Transfer Counter Ch. 0 Logic Destination Address Ch. 0 Interrupt Source Address Ch.

  • Page 125: Dma Control Registers

    9.3.1 DMA Control Registers (D0CON, Offset CAh, D1CON, Offset DAh) The DMA control registers (see Figure 9-2) determine the mode of operation for the DMA channels. These registers specify the following options: Whether the destination address is memory or I/O space Whether the destination address is incremented, decremented, or maintained constant after each transfer Whether the source address is memory or I/O space...

  • Page 126: Table 9-2 Synchronization Type

    1. This bit can be modified only when the CHG bit is set to a 1 during the same register write. Bit 0: Byte/Word Select (B/W)—On the Am186EM microcontroller, when B/W is set to 1, word transfers are selected. When B/W is set to 0, byte transfers are selected. Word transfers are not supported on the Am188EM microcontroller.

  • Page 127: Dma Transfer Count Registers

    9.3.2 DMA Transfer Count Registers (D0TC, Offset C8h, D1TC, Offset D8h) Each DMA channel maintains a 16-bit DMA Transfer Count register (DTC). This register is decremented after every DMA cycle, regardless of the state of the TC bit in the DMA Control register.

  • Page 128: Dma Destination Address High Register (High Order Bits) (D0Dsth, Offset C6H, D1Dsth, Offset D6H)

    Higher transfer rates can be achieved on the Am186EM microcontroller if all word transfers are performed to or from even addresses so that accesses occur in single, 16-bit bus cycles.

  • Page 129: Dma Destination Address Low Register (Low Order Bits) (D0Dstl, Offset C4H, D1Dstl, Offset D4H)

    9.3.4 DMA Destination Address Low Register (Low Order Bits) (D0DSTL, Offset C4h, D1DSTL, Offset D4h) Figure 9-5 shows the DMA Destination Address Low register. The sixteen bits of this register are combined with the four bits of the DMA Destination Address High register (see Figure 9-4) to produce a 20-bit destination address.

  • Page 130: Dma Source Address High Register (High Order Bits) (D0Srch, Offset C2H, D1Srch, Offset D2H)

    Higher transfer rates can be achieved on the Am186EM microcontroller if all word transfers are performed to or from even addresses so that accesses occur in single, 16-bit bus cycles.

  • Page 131: Dma Source Address Low Register (Low Order Bits) (D0Srcl, Offset C0H, D1Srcl, Offset D0H)

    9.3.6 DMA Source Address Low Register (Low Order Bits) (D0SRCL, Offset C0h, D1SRCL, Offset D0h) Figure 9-7 shows the DMA Source Address Low register. The sixteen bits of this register are combined with the four bits of the DMA Source Address High register (see Figure 9-6) to produce a 20-bit source address.

  • Page 132: Dma Requests

    DMA REQUESTS Data transfers can be either source or destination synchronized—either the source of the data or the destination of the data can request the data transfer. DMA transfers can also be unsynchronized (i.e., the transfer takes place continually until the correct number of transfers has occurred).

  • Page 133: Synchronization Timing

    9.4.1 Synchronization Timing DRQ1 or DRQ0 must be deasserted before the end of the DMA transfer to prevent another DMA cycle from occurring. The timing for the required deassertion depends on whether the transfer is source-synchronized or destination-synchronized. 9.4.1.1 Source Synchronization Timing Figure 9-8 shows a typical source-synchronized DMA transfer.

  • Page 134: Dma Acknowledge

    Figure 9-9 Destination Synchronized DMA Transfers Fetch Cycle Deposit Cycle CLKOUT (First case) (Second case) Notes: 1. This destination-synchronized transfer is not followed immediately by another DMA transfer. 2. This destination-synchronized transfer is immediately followed by another DMA transfer because DRQ is not deasserted soon enough.

  • Page 135: Dma Channels On Reset

    Each DMA register can be modified while the channel is operating. If the CHG bit is set to 0 when the control register is written, the ST bit of the control register will not be modified by the write. If multiple channel registers are modified, an internally LOCKed string transfer should be used to prevent a DMA transfer from occurring between updates to the channel registers.
  • Page 136 9-14 DMA Controller...

  • Page 137: Asynchronous Serial Port

    CHAPTER ASYNCHRONOUS SERIAL PORT 10.1 OVERVIEW The Am186EM and Am188EM microcontrollers provide an asynchronous serial port. The asynchronous serial port is a two-pin interface that permits full-duplex bidirectional data transfer. The asynchronous serial port supports the following features: Full-duplex operation...

  • Page 138: Serial Port Control Register (Spct, Offset 80H)

    10.2.1 Serial Port Control Register (SPCT, Offset 80h) The Serial Port Control register controls both the transmit and receive sections of the serial port. The format of the Serial Port Control register is shown in Figure 10-1. Figure 10-1 Serial Port Control Register (SPCT, offset 80h) Reserved RMODE TXIE...

  • Page 139: Table 10-4 Table

    Bits 6–5: Parity Mode (PMODE)—This field specifies how parity generation and checking are performed during transmission and reception, as shown in Table 10-2. Table 10-2 Parity Mode Bit Settings Parity PMODE None (No parity bit in frame) Odd (Odd number of 1s in frame) Even (Even number of 1s in frame) If parity checking and generation is selected, a parity bit is received or sent in addition to the specified number of data bits.

  • Page 140: Serial Port Status Register (Spsts, Offset 82H)

    10.2.2 Serial Port Status Register (SPSTS, Offset 82h) The Serial Port Status register indicates the status of the transmit and receive sections of the serial port. The format of the Serial Port Status register is shown in Figure 10-2. Figure 10-2 Serial Port Status Register (SPSTS, offset 82h) Reserved TEMT...

  • Page 141: Serial Port Transmit Data Register (Sptd, Offset 84H)

    10.2.3 Serial Port Transmit Data Register (SPTD, Offset 84h) Software writes this register (Figure 10-4) with data to be transmitted on the serial port. The transmitter is double-buffered, and the transmit section copies data from the transmit data register to the transmit shift register (which is not accessible to software) before transmitting the data.

  • Page 142: Serial Port Receive Data Register (Sprd, Offset 86H)

    10.2.4 Serial Port Receive Data Register (SPRD, Offset 86h) This register (Figure 10-4) contains data received over the serial port. The receiver is double-buffered, and the receive section can be receiving a subsequent frame of data in the receive shift register (which is not accessible to software) while the receive data register is being read by software.

  • Page 143: Serial Port Baud Rate Divisor Register (Spbaud, Offset 88H)

    10.2.5 Serial Port Baud Rate Divisor Register (SPBAUD, Offset 88h) This register (Figure 10-5) specifies a clock divisor for the generation of the serial clock that controls the serial port. The serial clock rate is 16 times the baud rate of transmission or reception of data.
  • Page 144 10-8 Asynchronous Serial Port...

  • Page 145: Synchronous Serial Interface

    SYNCHRONOUS SERIAL INTERFACE 11.1 OVERVIEW The synchronous serial interface lets the Am186EM and Am188EM microcontrollers communicate with application-specific integrated circuits (ASICs) that require programmability but are short on pins. The four-pin interface permits half-duplex, bidirectional data transfer at speeds of up to 20 Mbit/s with a 40-MHz CPU clock.

  • Page 146: Four-Pin Interface

    Four-Pin Interface The SDEN1–SDEN0 enable pins can be enabled for up to two peripheral devices. Transmit and receive operations are synchronized between the master (Am186EM or Am188EM microcontroller) and slave (peripheral) by means of the SCLK output. SCLK is derived from the processor internal clock divided by 2, 4, 8, or 16, as specified by the SSC register.

  • Page 147: Synchronous Serial Status Register (Sss, Offset 10H)

    11.2.1 Synchronous Serial Status Register (SSS, Offset 10h) This read-only register indicates the state of the SSI port. The format of the Synchronous Serial Status register is shown in Figure 11-1. Figure 11-1 Synchronous Serial Status Register (SSS, offset 10h) Reserved RE/TE DR/DT...

  • Page 148: Synchronous Serial Control Register (Ssc, Offset 12H)

    11.2.2 Synchronous Serial Control Register (SSC, Offset 12h) This read/write register controls the operation of the SDEN0–SDEN1 outputs and the transfer rate of the SSI port. The SDEN0 and SDEN1 outputs are asserted when a 1 is written to the corresponding bit. However, in the case when both DE0 and DE1 are set, only SDEN0 will be asserted.

  • Page 149: Synchronous Serial Transmit 1 Register (Ssd1, Offset 14H) Synchronous Serial Transmit 0 Register (Ssd0, Offset 16H)

    11.2.3 Synchronous Serial Transmit 1 Register (SSD1, Offset 14h) Synchronous Serial Transmit 0 Register (SSD0, Offset 16h) The Synchronous Serial Transmit 1 and 0 registers contain data to be transferred from the processor to the peripheral on a write operation. Only the least-significant 8 bits of the register are used.

  • Page 150: Synchronous Serial Receive Register (Ssr, Offset 18H)

    11.2.4 Synchronous Serial Receive Register (SSR, Offset 18h) The Synchronous Serial Receive (SSR) register contains the data transferred from the peripheral to the processor on a read operation. Only the least-significant 8 bits of the register are used. The format of the SSR register is shown in Figure 11-4. A receive data transmission is initiated by reading the SSR register while the port is not busy (PB bit in SSS register is 0) and one or both of the enable bits (DE1–DE0 in the SSC register) is set.

  • Page 151: Ssi Programming

    11.3 SSI PROGRAMMING The SSI interface allows for a variety of software and hardware protocols. Signaling a read/write—In general, software uses the first write to the SSI to transmit an address or count to the peripheral. This value can include a read/write flag in the case where the device supports both reads and writes.
  • Page 152 Figure 11-5 Synchronous Serial Interface Multiple Write PB=0 PB=1 PB=0 PB=1 PB=0 PB=1 PB=0 PB=0 DR/DT=0 DR/DT=0 DR/DT=1 DR/DT=0 DR/DT=1 DR/DT=0 DR/DT=1 DR/DT=0 SDEN SCLK SDATA Poll SSS for Poll SSS for Poll SSS for PB=0 PB=0 PB=0 Write to SSD Write to SSD Write to SSD Write to SSC bit...

  • Page 153: Programmable I/O Pins

    12.1 OVERVIEW Thirty-two pins on the Am186EM and Am188EM microcontrollers are available as user- programmable I/O signals (PIOs). Each of these pins can be used as a PIO if the normal function of the pin is not needed. If a pin is enabled to function as a PIO signal, the normal function is disabled and does not affect the pin.
  • Page 154 1. These pins are used by emulators. (Emulators also use S2–S0 , RES , NMI, CLKOUTA, BHE , ALE, AD15–AD0, and A16–A0.) 2. These pins revert to normal operation if BHE/ADEN (Am186EM) or RFSH2/ADEN (Am188EM) is held Low during power-on reset.

  • Page 155: Pio Mode Registers

    Table 12-2 shows the possible settings for the PIO Mode and PIO Direction bits. The Am186EM and Am188EM microcontrollers default the 32 PIO pins to either 00b (normal operation) or 01b (PIO input with weak internal pullup or pulldown enabled).

  • Page 156: Pio Direction Registers

    12.3 PIO DIRECTION REGISTERS Each PIO is individually programmed as an input or output by a bit in one of the PIO Direction registers (see Figure 12-4 and Figure 12-5). Table 12-2 on page 12-3 shows the values that the PIO mode bits and the PIO direction bits can encode. The column titled Power-On Reset State in Table 12-1 lists the reset default values for the PIOs.

  • Page 157: Pio Data Registers

    12.4 PIO DATA REGISTERS If a PIO pin is enabled as an output, the value in the corresponding bit in one of the PIO Data registers (see Figure 12-6 and Figure 12-7) is driven on the pin with no inversion (Low=0, High=1).
  • Page 158 12-6 Programmable I/O Pins...

  • Page 159: Register Summary

    APPENDIX REGISTER SUMMARY This appendix summarizes the peripheral control block registers. Table A-1 lists all the registers. Figure A-1 shows the layout of each of the internal registers. The column titled Comment in Table A-1 is used to identify the specific use of interrupt registers when there is a mix of master mode and slave mode usage.

  • Page 160: Table A-1 Internal Register Summary

    Table A-1 Internal Register Summary Hex Offset Mnemonic Register Description Comment RELREG Peripheral control block relocation register RESCON Reset configuration register Processor release level register PDCON Power-save control register EDRAM Enable RCU register CDRAM Clock prescaler register MDRAM Memory partition register D1TC DMA 1 transfer count register D1DSTH...

  • Page 161: Table

    Table A-1 Internal Register Summary (continued) Hex Offset Mnemonic Register Description Comment T1CMPB Timer 1 maxcount compare B register T1CMPA Timer 1 maxcount compare A register T1CNT Timer 1 count register T0CON Timer 0 mode/control register T0CMPB Timer 0 maxcount compare B register T0CMPA Timer 0 maxcount compare A register T0CNT...

  • Page 162: Figure 4-1 Peripheral Control Block Relocation Register

    Figure A-1 Internal Register Summary Offset (Hexadecimal) R19–R8 Res S/M Res M/IO Peripheral Control Block Relocation Register (RELREG) Page 4-4 Reset Configuration Register (RESCON) Page 4-5 Reserved Processor Release Level Register (PRL) Page 4-6 F2–F0 CAF CAD PSEN Power-Save Control Register (PDCON) Page 4-7 T8–T0 Enable RCU Register (EDRAM)
  • Page 163 Figure A-1 Internal Register Summary (continued) M6–M0 RA19 RA13 Memory Partition Register (MDRAM) Page 6-1 TDRQ DM/IO DINC SDEC DDEC SINC SM/IO DMA 1 Control Register (D1CON) Page 9-3 TC15–TC0 DMA 1 Transfer Count Register (D1TC) Page 9-5 Reserved DDA19–DDA16 DMA 1 Destination Address High Register (D1DSTH) Page 9-6 DDA15–DDA0...
  • Page 164 Figure A-1 Internal Register Summary (continued) TDRQ DM/IO DINC SDEC DDEC SINC SM/IO DMA 0 Control Register (D0CON) Page 9-3 TC15–TC0 DMA 0 Transfer Count Register (D0TC) Page 9-5 Reserved DDA19–DDA16 DMA 0 Destination Address High Register (D0DSTH) Page 9-6 DDA15–DDA0 DMA 0 Destination Address Low Register (D0DSTL) Page 9-7...
  • Page 165 Figure A-1 Internal Register Summary (continued) M6–M0 R1–R0 PCS and MCS Auxiliary Register (MPCS) Page 5-10 BA19–BA13 R1–R0 Midrange Memory Chip Select Register (MMCS) Page 5-8 BA19–BA11 R1–R0 Peripheral Chip Select Register (PACS) Page 5-12 UB2–UB0 R1–R0 Low Memory Chip Select Register (LMCS) Page 5-6 LB2–LB0 R1–R0...
  • Page 166 Figure A-1 Internal Register Summary (continued) RDATA Reserved Serial Port Receive Data Register (SPRD) Page 10-6 TDATA Reserved Serial Port Transmit Data Register (SPTD) Page 10-5 Reserved TEMT THRE BRKI Serial Port Status Register (SPSTS) Page 10-4 Reserved PMODE RSIE TXIE WLGN TMODE...
  • Page 167 Figure A-1 Internal Register Summary (continued) PMODE31–PMODE16 PIO Mode 1 Register (PIOMODE1) Page 12-3 PDATA15–PDATA0 PIO Data 0 Register (PDATA0) Page 12-5 PDIR15–PDIR0 PIO Direction 0 Register (PDIR0) Page 12-4 PMODE15–PMODE0 PIO Mode 0 Register (PIOMODE0) Page 12-3 CONT Timer 2 Mode/Control Register (T2CON) Page 8-5 TC15–TC0 Timer 2 Maxcount Compare A Register (T2CMPA)
  • Page 168 Figure A-1 Internal Register Summary (continued) TC15–TC0 Timer 2 Count Register (T2CNT) Page 8-6 Timer 1 Mode/Control Register (T1CON) CONT Page 8-3 TC15–TC0 Timer 1 Maxcount Compare B Register (T1CMPB) Page 8-7 TC15–TC0 Timer 1 Maxcount Compare A Register (T1CMPA) Page 8-7 TC15–TC0 Timer 1 Count Register (T1CNT)
  • Page 169 Figure A-1 Internal Register Summary (continued) TC15–TC0 Timer 0 Maxcount Compare A Register (T0CMPA) Page 8-7 TC15–TC0 Timer 0 Count Register (T0CNT) Page 8-6 Reserved PR2–PR0 Serial Port Interrupt Control Register (SPICON) Master Mode Page 7-19 Reserved PR2–PR0 Watchdog Timer Interrupt Control Register (WDCON) Master Mode Page 7-18 Reserved...
  • Page 170 Figure A-1 Internal Register Summary (continued) Reserved PR2–PR0 INT2 Control Register (I2CON) Master Mode Page 7-15 Reserved PR2–PR0 SFNM INT1 Control Register (I1CON) Master Mode Page 7-13 Reserved PR2–PR0 Timer 2 Interrupt Control Register (T2INTCON) Slave Mode Page 7-29 Reserved PR2–PR0 SFNM INT0 Control Register (I0CON)
  • Page 171 Figure A-1 Internal Register Summary (continued) Reserved PR2–PR0 DMA 0 Interrupt Control Register (DMA0CON) Master Mode—Page 7-17 Slave Mode—Page 7-29 Reserved PR2–PR0 Timer Interrupt Control Register (TCUCON) Master Mode—Page 7-17 Timer 0 Interrupt Control Register (T0INTCON) Slave Mode—Page 7-29 TMR2–TMR0 Reserved DHLT Interrupt Status Register (INTSTS)
  • Page 172 Figure A-1 Internal Register Summary (continued) Reserved Res TMR In-Service Register (INSERV) Master Mode Page 7-22 Reserved TMR2 TMR1 TMR0 In-Service Register (INSERV) Slave Mode Page 7-32 Reserved PRM2–PRM0 Priority Mask Register (PRIMSK) Master Mode—Page 7-23 Slave Mode—Page 7-33 Reserved Interrupt Mask Register (IMASK) Master Mode Page 7-24...
  • Page 173 Figure A-1 Internal Register Summary (continued) Reserved S4–S0 IREQ Poll Status Register (POLLST) Master Mode Page 7-25 Reserved S4–S0 IREQ Poll Register (POLL) Master Mode Page 7-26 Reserved S4–S0 NSPEC End-of-Interrupt Register (EOI) Master Mode Page 7-27 Reserved L2–L0 Specific End-of-Interrupt Register (EOI) Slave Mode Page 7-35 Reserved...
  • Page 174 Figure A-1 Internal Register Summary (continued) Reserved Synchronous Serial Receive Register (SSR) Page 11-6 Reserved Synchronous Serial Transmit 0 Register (SSD0) Page 11-5 Reserved Synchronous Serial Transmit 1 Register (SSD1) Page 11-5 Reserved DE1 DE0 SCLKDIV Synchronous Serial Control Register (SSC) Page 11-4 Reserved RE/TE...
  • Page 175 Timer 0 Mode/Control Register 8-4 D1-D0 (DMA Channel Interrupt InService) 7-22, 7- Timer 1 Mode/Control Register 8-4 32, 7-34 Am186EM microcontroller D1-D0 (DMA Channel Interrupt Masks) 7-24 design philosophy xiii D1-D0 (DMA Channel Interrupt Request) 7-21, 7-31 product support iii...
  • Page 176 FER (Framing Error) 10-4 RE/TE (Receive/Transmit Error Detect) 11-3 I4-I0 (Interrupt InService) 7-22 RIU (Register in Use) 8-3 I4-I0 (Interrupt Mask) 7-24 RMODE (Receive Mode) 10-3 I4-I0 (Interrupt Requests) 7-21 RSIE (Receive Status Interrupt Enable) 10-3 INH (Inhibit Bit) 8-3, 8-5 RTG (Retrigger Bit) 8-3 INT (Interrupt Bit) 8-3, 8-5 RXIE (Receive Data Ready Interrupt Enable) 10-2...
  • Page 177 9-5 D1-D0 field (DMA Channel Interrupt Masks) 7-24 documentation D1-D0 field (DMA Channel Interrupt Request) 7-21, 7- AMD E86 Family publications xiv ordering documentation and literature iii DDA15-DDA0 field (DMA Destination Address Low) 9-7 DR/DT bit (Data Receive/Transmit Complete) 11-3...
  • Page 178 Timer 2 Mode/Control Register 8-5 InService Register E bit (Enable RCU) 6-2 description EN bit (Enable Bit) Master mode 7-22 Timer 0 Mode/Control Register 8-3 Slave mode 7-32 Timer 1 Mode/Control Register 8-3 Instruction exceptions 7-3 Timer 2 Mode/Control Register 8-5 INT bit (Interrupt Bit) EN bit (Enable PowerSave Mode) 4-7 Timer 0 Mode/Control Register 8-3...
  • Page 179 Interrupt mask bit 7-2 Interrupt Mask Register L2-L0 field (Interrupt Type) 7-35 description LB2-LB0 field (Lower Boundary) 5-4 Master mode 7-24 LCS signal (Lower Memory Chip Select) Slave mode 7-34 definition 3-6 Interrupt priority 7-2, 7-5 LOOP bit (Loopback) 10-2 Interrupt Request Register Low Memory Chip Select Register description...
  • Page 180 INT1 Control Register 7-13 physical dimensions xiv INT2 Control Register 7-15 pin description xiv INT3 Control Register 7-15 PIO Data 0 Register INT4 Control Register 7-16 description 12-5 Serial Port Interrupt Control Register 7-19 PIO Data 1 Register Timer Interrupt Control Registers 7-29 description 12-5 Virtual Watchdog Timer Interrupt Control Register PIO Direction 0 Register...
  • Page 181 Slave mode 7-33 C4h) 9-7 PRM2-PRM0 field (Priority Field Mask) 7-23, 7-33 DMA 1 Destination Address Low (D1DSTL, Offset D4h) 9-7 Processor Release Level Register DMA 1 Interrupt Control (DMA1CON, Offset 36h) 7- description 4-6 17, 7-29 product support DMA 1 Source Address High (D1SRCH, Offset bulletin board service iii D2h) 9-8 documentation and literature iii...
  • Page 182 Serial Port Baud Rate Divisor (SPBAUD, Offset description 4-5 88h) 10-7 RFSH signal (Automatic Refresh) Serial Port Control (SPCT, Offset 80h) 10-2 definition 3-7 Serial Port Interrupt Control (SPICON, Offset 44h) RFSH2/ADEN signal Master mode 7-19 definition 3-11 Serial Port Receive Data (SPRD, Offset 86h) 10-6 RIU bit (Register in Use) Serial Port Status (SPSTS, Offset 82h) 10-4 Timer 0 Mode/Control Register 8-3...
  • Page 183 Serial Port Status Register RFSH2/ADEN (Refresh 2/Address Enable) 3-11 description 10-4 RXD (Receive Data) 3-11 Serial Port Transmit Data Register S2-S0 (Bus Cycle Status 2-0) 3-11 description 10-5 S6 (Bus Cycle Status 6) 3-12 SFNM bit (Special Fully Nested Mode) 7-13 SCLK (Serial Clock) 3-12 signal description SDATA (Serial Data) 3-12...
  • Page 184 Synchronous Serial Transmit 1 Register Timer 2 Maxcount Compare B Register description 11-5 description 8-7 Timer 2 Mode and Control Register description 8-5 TImer Interrupt Control Register T4-T0 field (Interrupt Type) 7-36 description T8-T0 field (Refresh Count) 6-2 Master mode 7-17 Table timing characteristics xiv interrupt controller registers in master mode 7-12...
  • Page 185 Watchdog Timer Interrupt Control Register description Master mode 7-18 WB signal (Write Byte) definition 3-14 WD bit (Virtual Watchdog Timer Interrupt InService) 7- WD bit (Virtual Watchdog Timer Interrupt Mask) 7-24 WD bit (Virtual Watchdog Timer Interrupt Request) 7-21 WHB signal (Write High Byte) definition 3-14 WLB signal (Write Low Byte) definition 3-14...
  • Page 186 I-12 Index...

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