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Am186 ES
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AMD Am186 ES User Manual
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Contents
Table of Contents
Bookmarks
Table of Contents
Table of Contents
Design Philosophy
Intended Audience
Preface
Purpose of this Manual
User's Manual Overview
Amd Documentation
E86 Family
Introduction and Overview
Chapter 1 Features and Performance
Key Features and Benefits
Distinctive Characteristics
Figure 1-1 Am186Es Microcontroller Block Diagram
Figure 1-2 Am188Es Microcontroller Block Diagram
Application Considerations
Clock Generation
Memory Interface
Figure 1-3 Basic Functional System Design
Chapter 2 Programming
Register Set
Processor Status Flags Register
Figure 2-1 Register Set
Figure 2-2 Processor Status Flags Register (F)
Memory Organization and Address Generation
Figure 2-3 Physical Address Generation
Figure 2-4 Memory and I/O Space
I/O Space
Instruction Set
Table 2-1 Instruction Set
Data Types
Segments
Table 2-2 Segment Register Selection Rules
Figure 2-5 Supported Data Types
Addressing Modes
Table 2-3 Memory Addressing Mode Examples
Chapter 3 System Overview
Bus Operation
Figure 3-1 Am186Es Microcontroller Address Bus-Normal Read and
Figure 3-2 Am186Es Microcontroller-Read and Write with Address Bus
Figure 3-3 Am188Es Microcontroller Address Bus-Normal Read
Figure 3-4 Am188Es Microcontroller-Read and Write with Address
Bus Interface Unit
Nonmultiplexed Address Bus
Static Bus Sizing
Byte Write Enables
Pseudo Static RAM (PSRAM) Support
Table 3-3 Programming Am186Es Microcontroller Bus Width
Clock and Power Management Unit
Phase-Locked Loop (PLL)
Crystal-Driven Clock Source
Figure 3-5 Oscillator Configurations
External Source Clock
System Clocks
Power-Save Operation
Figure 3-6 Clock Organization
Chapter 4 Peripheral Control Block
Figure 4-5 System Configuration Register
Figure 7-17 End-Of-Interrupt Register
Table 4-1 Peripheral Control Block Register Map
Peripheral Control Block Relocation Register
(RELREG, Offset Feh)
Figure 4-1 Peripheral Control Block Relocation Register
Figure 4-2 Reset Configuration Register
Reset Configuration Register (RESCON, Offset F6H)
Figure 4-3 Processor Release Level Register
Processor Release Level Register (PRL, Offset F4H)
Table 4-2 Processor Release Level (PRL) Values
Auxiliary Configuration Register (AUXCON, Offset F2H)
Figure 4-4 Auxiliary Configuration Register
System Configuration Register (SYSCON, Offset F0H)
Initialization and Processor Reset
Table 4-3 Initial Register State after Reset
Pin Descriptions
Table 3-1 Numeric PIO Pin Designations
Table 3-2 Alphabetic PIO Pin Designations
Pins that Are Used by Emulators
Overview
Chapter 5 Chip Select Unit
Overview
Table 5-1 Chip Select Register Summary
Chip Select Timing
Ready and Wait-State Programming
Chip Select Overlap
Chip Select Registers
Upper Memory Chip Select Register (UMCS, Offset A0H)
Figure 5-1 Upper Memory Chip Select Register
Table 5-2 UMCS Block Size Programming Values
Low Memory Chip Select Register (LMCS, Offset A2H)
Figure 5-2 Low Memory Chip Select Register
Table 5-3 LMCS Block Size Programming Values
Midrange Memory Chip Select Register (MMCS, Offset A6H)
Figure 5-3 Midrange Memory Chip Select Register
PCS and MCS Auxiliary Register (MPCS, Offset A8H)
Figure 5-4 PCS and MCS Auxiliary Register
Table 5-4 MCS Block Size Programming
Peripheral Chip Select Register (PACS, Offset A4H)
Figure 5-5 Peripheral Chip Select Register
Table 5-5 PCS Address Ranges
Table 5-6 PCS3-PCS0 Wait-State Encoding
Chapter 6 Refresh Control Unit
Overview
Memory Partition Register (MDRAM, Offset E0H)
Figure 6-1 Memory Partition Register
Clock Prescaler Register (CDRAM, Offset E2H)
Enable RCU Register (EDRAM, Offset E4H)
Figure 6-2 Clock Prescaler Register
Figure 6-3 Enable RCU Register
Watchdog Timer Control Register (WDTCON, Offset E6H)
Figure 6-4 Watchdog Timer Control Register
Table 6-1 Watchdog Timer COUNT Settings
Table 6-2 Watchdog Timer Duration
Chapter 7 Interrupt Control Unit
Overview
Definitions of Interrupt Terms
Table 7-1 Am186Es and Am188Es Microcontroller Interrupt Types
Interrupt Conditions and Sequence
Interrupt Priority
Software Exceptions, Traps, and NMI
Interrupt Acknowledge
Figure 7-1 External Interrupt Acknowledge Bus Cycles
Interrupt Controller Reset Conditions
Master Mode Operation
Fully Nested Mode
Figure 7-2 Fully Nested (Direct) Mode Interrupt Controller Connections
Cascade Mode
Figure 7-3 Cascade Mode Interrupt Controller Connections
Special Fully Nested Mode
Operation in a Polled Environment
End-Of-Interrupt Write to the EOI Register
Master Mode Interrupt Controller Registers
Table 7-2 Interrupt Controller Registers in Master Mode
INT0 and INT1 Control Registers
(I0CON, Offset 38H, I1CON, Offset 3Ah)
Figure 7-4 INT0 and INT1 Control Registers
INT2 and INT3 Control Registers
(I2CON, Offset 3Ch, I3CON, Offset 3Eh)
Figure 7-5 INT2 and INT3 Control Registers
Figure 7-6 INT4 Control Register
INT4 Control Register (I4CON, Offset 40H)
Figure 7-7 Timer/Dma Interrupt Control Registers
Timer and DMA Interrupt Control Registers (TCUCON, Offset 32H, DMA0CON/INT5CON, Offset 34H, DMA1CON/INT6CON, Offset 36H)
Serial Port 0/1 Interrupt Control Registers
(SP0CON/SP1CON, Offset 44H/42H)
Figure 7-8 Serial Port 0/1 Interrupt Control Register
Table 7-3 Priority Level
Figure 7-9 Interrupt Status Register
Interrupt Status Register (INTSTS, Offset 30H)
Figure 7-10 Interrupt Request Register
Interrupt Request Register (REQST, Offset 2Eh)
Figure 7-11 Interrupt In-Service Register
Interrupt In-Service Register (INSERV, Offset 2Ch)
Figure 7-12 Priority Mask Register
Priority Mask Register (PRIMSK, Offset 2Ah)
Table 7-4 Priority Level
Figure 7-13 Interrupt Mask Register
Interrupt Mask Register (IMASK, Offset 28H)
Figure 7-14 Poll Status Register
Poll Status Register (POLLST, Offset 26H)
Figure 7-15 Poll Register
Poll Register (POLL, Offset 24H)
End-Of-Interrupt Register (EOI, Offset 22H)
Figure 7-16 Example EOI Assembly Code
Slave Mode Operation
Slave Mode Interrupt Nesting
Slave Mode Interrupt Controller Registers
Table 7-5 Interrupt Controller Registers in Slave Mode
Timer and DMA Interrupt Control Registers
Figure 7-18 Timer and DMA Interrupt Control Registers
Interrupt Status Register (INTSTS, Offset 30H)
Figure 7-19 Interrupt Status Register
Interrupt Request Register (REQST, Offset 2Eh)
Figure 7-20 Interrupt Request Register
Interrupt In-Service Register (INSERV, Offset 2Ch)
Figure 7-21 Interrupt In-Service Register
Priority Mask Register (PRIMSK, Offset 2Ah)
Table 7-6 Priority Level
Interrupt Mask Register (IMASK, Offset 28H)
Specific End-Of-Interrupt Register (EOI, Offset 22H)
Interrupt Vector Register (INTVEC, Offset 20H)
Chapter 8 Timer Control Unit
Overview
Pulse Width Demodulation
Programmable Registers
Timer Operating Frequency
Table 8-1 Timer Control Unit Register Summary
Timer 0 and Timer 1 Mode and Control Registers (T0CON, Offset 56H, T1CON, Offset 5Eh)
Timer 2 Mode and Control Register (T2CON, Offset 66H)
Timer Count Registers (T0CNT, Offset 50H, T1CNT, Offset 58H, T2CNT, Offset 60H)
Timer Maxcount Compare Registers (T0CMPA, Offset 52H, T0CMPB, Offset 54H, T1CMPA, Offset 5Ah, T1CMPB, Offset 5Ch, T2CMPA, Offset 62H)
Chapter 9 Dma Controller
Overview
Dma Operation
Table 9-1 DMA Controller Register Summary
Programmable Dma Registers
DMA Control Registers (D0CON, Offset Cah, D1CON, Offset Dah)
Table 9-2 Synchronization Type
Serial Port/Dma Transfers
DMA Transfer Count Registers (D0TC, Offset C8H, D1TC, Offset D8H)
DMA Destination Address High Register (High Order Bits) (D0DSTH, Offset C6H, D1DSTH, Offset D6H)
DMA Destination Address Low Register (Low Order Bits) (D0DSTL, Offset C4H, D1DSTL, Offset D4H)
DMA Source Address High Register (High Order Bits) (D0SRCH, Offset C2H, D1SRCH, Offset D2H)
DMA Source Address Low Register (Low Order Bits) (D0SRCL, Offset C0H, D1SRCL, Offset D0H)
Dma Requests
Table 9-3 Maximum DMA Transfer Rates
Synchronization Timing
DMA Acknowledge
DMA Priority
DMA Programming
DMA Channels on Reset
Chapter 10 Asynchronous Serial Ports
Overview
Serial Port Flow Control
Table 10-1 Serial Port External Pins
Programmable Registers
Table 10-2 Asynchronous Serial Port Register Summary
Serial Port 0/1 Control Registers (SP0CT/SP1CT, Offset 80H/10H)
Table 10-3 DMA Control Bits
Table 10-4 Serial Port MODE Settings
Serial Port 0/1 Status Registers (SP0STS/SP1STS, Offset 82H/12H)
Serial Port 0/1 Transmit Registers (SP0TD/SP1TD, Offset 84H/14H)
Serial Port 0/1 Receive Registers (SP0RD/SP1RD, Offset 86H/16H)
Serial Port 0/1 Baud Rate Divisor Registers (SP0BAUD/SP1BAUD, Offset 88H/18H)
Table 10-5 Common Baud Rates
Chapter 11 Programmable I/O Pins
Overview
Table 11-1 PIO Pin Assignments
Pio Mode Registers
PIO Mode 1 Register (PIOMODE1, Offset 76H)
PIO Mode 0 Register (PIOMODE0, Offset 70H)
Table 11-2 PIO Mode and PIO Direction Settings
Pio Direction Registers
PIO Direction 1 Register (PDIR1, Offset 78H)
PIO Direction 0 Register (PDIR0, Offset 72H)
Pio Data Registers
Open-Drain Outputs
Register Summary
Table A-1 Internal Register Summary
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