AMD Am186 ES User Manual
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AMD Am186 ES User Manual

AMD Am186 ES User Manual

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Am186™ES and Am188™ES
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Summary of Contents for AMD Am186 ES

  • Page 1 Am186™ES and Am188™ES User’s Manual...
  • Page 2 The information in this publication is believed to be accurate at the time of publication, but AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes at any time, without notice.
  • Page 3 Hotline and World Wide Web Support For answers to technical questions, AMD provides a toll-free number for direct access to our corporate applications hotline. Also available is the AMD World Wide Web home page and FTP site, which provides the latest E86 family product information, including technical information and data on upcoming product releases.

  • Page 5: Table Of Contents

    AMD DOCUMENTATION ........
  • Page 6 INITIALIZATION AND PROCESSOR RESET ..... 4-8 CHAPTER 5 CHIP SELECT UNIT OVERVIEW..........5-1 CHIP SELECT TIMING .
  • Page 7 7.4.3 Timer and DMA Interrupt Control Registers (T0INTCON, Offset 32h, T1INTCON, Offset 38h, T2INTCON, Offset 3Ah, DMA0CON/INT5, Offset 34h, DMA1CON/INT6, Offset 36h)......... . 7-29 7.4.4 Interrupt Status Register (INTSTS, Offset 30h).
  • Page 8 10.2.3 Serial Port 0/1 Transmit Registers (SP0TD/SP1TD, Offset 84h/14h) ..... . . 10-11 10.2.4 Serial Port 0/1 Receive Registers (SP0RD/SP1RD, Offset 86h/16h) ..... . . 10-12 10.2.5 Serial Port 0/1 Baud Rate Divisor Registers (SP0BAUD/SP1BAUD, Offset 88h/18h) .
  • Page 9 LIST OF FIGURES Figure 1-1 Am186ES Microcontroller Block Diagram ......1-4 Figure 1-2 Am188ES Microcontroller Block Diagram .
  • Page 10 Figure 8-1 Typical Waveform Behavior ........8-1 Figure 8-2 Timer 0 and Timer 1 Mode and Control Registers .
  • Page 11 LIST OF TABLES Table 2-1 Instruction Set ..........2-5 Table 2-2 Segment Register Selection Rules .
  • Page 12 Table of Contents...

  • Page 13: Preface

    PREFACE INTRODUCTION AND OVERVIEW DESIGN PHILOSOPHY The Am186™ES and Am188™ES microcontrollers provide a low-cost, high-performance solution for embedded system designers who wish to use the x86 architecture. By integrating multiple functional blocks with the CPU, the Am186ES and Am188ES microcontrollers eliminate the need for off-chip system-interface logic.

  • Page 14: Amd Documentation

    Technical documentation for the E86 family is included on the CD in PDF format. To order literature, contact the nearest AMD sales office or call (800) 222-9323 (in the U.S. and Canada) or direct dial from any location (512) 602-5651.

  • Page 15: Features And Performance

    Am186ES and Am188ES microcontrollers reduce the cost of existing 80C186/188 designs. x86 software compatibility—80C186/188-compatible and upward-compatible with the other members of the AMD E86 family. The x86 architecture is the most widely used and supported computer architecture in the world.

  • Page 16: Distinctive Characteristics

    DISTINCTIVE CHARACTERISTICS A block diagram of each microcontroller is shown in Figure 1-1 and Figure 1-2. The Am186ES microcontroller uses a 16-bit external bus, while the Am188ES microcontroller has an 8-bit external bus. The Am186ES and Am188ES microcontrollers include the following features: E86™...
  • Page 17 — Programmable memory and peripheral chip-select logic — Programmable wait state generator — Power-save clock divider Software-compatible with the 80C186 and 80C188 microcontrollers with widely available native development tools, applications, and system software A compatible evolution of the Am186™EM and Am188™EM microcontrollers Available in the following packages: —...

  • Page 18: Figure 1-1 Am186Es Microcontroller Block Diagram

    Figure 1-1 Am186ES Microcontroller Block Diagram INT2/INTA0** INT3/INTA1/IRQ INT1/SELECT CLKOUTA TMROUT0 TMROUT1 INT6–INT4** INT0 PWD** TMRIN0 TMRIN1 DRQ0** DRQ1** CLKOUTB Timer Control Unit Unit Pulse Width Clock and Max Count B 20-Bit Source Interrupt Power Demod- Registers Pointers Management Control Unit ulator Max Count A 20-Bit Destination...

  • Page 19: Figure 1-2 Am188Es Microcontroller Block Diagram

    Figure 1-2 Am188ES Microcontroller Block Diagram INT2/INTA0** INT3/INTA1/IRQ INT1/SELECT CLKOUTA TMROUT0 TMROUT1 INT6–INT4** INT0 PWD** TMRIN0 TMRIN1 DRQ0** DRQ1** CLKOUTB Timer Control Unit Unit Pulse Clock and Width Max Count B 20-Bit Source Power Interrupt Demod- Registers Pointers Control Unit Management ulator 20-Bit Destination...

  • Page 20: Application Considerations

    APPLICATION CONSIDERATIONS The integration enhancements of the Am186ES and Am188ES microcontrollers provide a high-performance, low-system-cost solution for 16-bit embedded microcontroller designs. The nonmultiplexed address bus eliminates the need for system-support logic to interface memory devices, while the multiplexed address/data bus maintains the value of previously engineered, customer-specific peripherals and circuits within the upgraded design.
  • Page 21 chip-select signals is increased to 512 Kbytes to facilitate the use of high-density memory devices. Improved memory timing specifications enables the use of no-wait-state memories with 70-ns access times at 40-MHz CPU operation. This reduces overall system cost significantly by allowing the use of commonly available memory devices. Figure 1-3 illustrates an Am186ES microcontroller-based SRAM configuration.
  • Page 22 Features and Performance...

  • Page 23: Programming

    CHAPTER PROGRAMMING All members of the Am186 and Am188 family of microcontrollers, including the Am186ES and Am188ES, contain the same basic set of registers, instructions, and addressing modes, and are compatible with the original industry-standard 186/188 parts. REGISTER SET The base architecture of the Am186ES and Am188ES microcontrollers has 14 registers, as shown in Figure 2-1.

  • Page 24: Processor Status Flags Register

    Figure 2-1 Register Set 16-Bit Special Register 16-Bit Register Name Functions Register Name Code Segment Byte Multiply/Divide Addressable I/O Instructions Data Segment (8-Bit Loop/Shift/Repeat/Count Stack Segment Register Names Extra Segment Shown) Base Registers Segment Registers Base Pointer Source Index Index Registers Destination Index Processor Status Flags FLAGS...

  • Page 25: Memory Organization And Address Generation

    Bit 9: Interrupt-Enable Flag (IF)—When set, enables maskable interrupts to cause the CPU to transfer control to a location specified by an interrupt vector. Bit 8: Trace Flag (TF)—When set, a trace interrupt occurs after instructions execute. TF is cleared by the trace interrupt after the processor status flags are pushed onto the stack. The trace service routine can continue tracing by popping the flags back with an interrupt return (IRET) instruction.

  • Page 26: I/O Space

    Figure 2-3 Physical Address Generation Shift Left 4 Bits Segment Base Logical Address Offset Physical Address To Memory I/O SPACE The I/O space consists of 64K 8-bit or 32K 16-bit ports. The IN and OUT instructions address the I/O space with either an 8-bit port address specified in the instruction, or a 16-bit port address in the DX register.

  • Page 27: Table 2-1 Instruction Set

    Table 2-1 Instruction Set Mnemonic Instruction Name ASCII adjust for addition ASCII adjust for division ASCII adjust for multiplication ASCII adjust for subtraction Add byte or word with carry Add byte or word Logical AND byte or word BOUND Detects values outside prescribed range CALL Call procedure Convert byte to word...
  • Page 28 Mnemonic Instruction Name JB/JNAE Jump if below/not above or equal JBE/JNA Jump if below or equal/not above Jump if carry JCXZ Jump if register CX = 0 JE/JZ Jump if equal/zero JG/JNLE Jump if greater/not less or equal JGE/JNL Jump if greater or equal/not less JL/JNGE Jump if less/not greater or equal JLE/JNG...
  • Page 29 Mnemonic Instruction Name Logical inclusive OR byte or word Output byte or word Pop word off stack POPA Pop all general register off stack POPF Pop flags off stack PUSH Push word onto stack PUSHA Push all general registers onto stack PUSHF Push flags onto stack Rotate left through carry byte or word...

  • Page 30: Segments

    SEGMENTS The Am186ES and Am188ES use four segment registers: 1. Data Segment (DS): The processor assumes that all accesses to the program’s variables are from the 64K space pointed to by the DS register. The data segment holds data, operands, etc. 2.

  • Page 31: Figure 2-5 Supported Data Types

    Pointer—A 16-bit or 32-bit quantity, composed of a 16-bit offset component or a 16-bit segment base component in addition to a 16-bit offset component. String—A contiguous sequence of bytes or words. A string can contain from 1 byte up to 64 Kbytes. In general, individual data elements must fit within defined segment limits.

  • Page 32: Addressing Modes

    ADDRESSING MODES The Am186ES and Am188ES microcontrollers use eight categories of addressing modes to specify operands. Two addressing modes are provided for instructions that operate on register or immediate operands; six modes are provided to specify the location of an operand in a memory segment.

  • Page 33: System Overview

    CHAPTER SYSTEM OVERVIEW This chapter contains descriptions of the Am186ES and Am188ES microcontroller pins, the bus interface unit, the clock and power management unit, and power-save operation. PIN DESCRIPTIONS Pin Terminology The following terms are used to describe the pins: Input—An input-only pin.
  • Page 34 AO15–AO8 Address-Only Bus, Am188ES Microcontroller (output, three-state, synchronous, level-sensitive) AO15–AO8—On the Am188ES microcontroller, the address-only bus (AO15–AO8) contains valid high-order address bits from bus cycles t – . When address generation is disabled (AD = 1), the address on this bus is not valid during t .
  • Page 35 BHE/ADEN Bus High Enable, Am186ES Microcontroller Only (three-state, output, synchronous) Address Enable, Am188ES Microcontroller Only (input, internal pullup) BHE—During a memory access, this pin and the least-significant address bit (AD0 or A0) indicate to the system which bytes of the data bus (upper, lower, or both) participate in a bus cycle.
  • Page 36 All AC timing specs that use a clock relate to CLKOUTA. CLKOUTB Clock Output B (output, synchronous) This pin supplies an additional clock with a delayed output compared to CLKOUTA. Depending upon the value of the system configuration register (SYSCON), CLKOUTB operates at either the crystal input frequency (X1), the power-save frequency, or is three-stated.
  • Page 37 request. INT5 shares the DMA 0 interrupt type (0Ah) and register control bits. INT5 is edge-triggered only and must be held until the interrupt is acknowledged. DRQ1/INT6/PIO13 DMA Request 1 (input, synchronous, level-sensitive) Maskable Interrupt Request 6 (input, asynchronous, edge-triggered) DRQ1—This pin indicates to the microcontroller that an external device is ready for DMA channel 1 to perform a transfer.
  • Page 38 requests in priority of activity requests received by the processor. This implies that if a HOLD request is received just as a DMA transfer begins, the HOLD latency can be as great as 4 bus cycles. This occurs if a DMA word transfer operation is taking place (Am186ES microcontroller only) from an odd address to an odd address.
  • Page 39 INTA0—When the microcontroller interrupt control unit is operating in cascade mode, this pin indicates to the system that the microcontroller needs an interrupt type to process the interrupt request on INT0. The peripheral issuing the interrupt request must provide the microcontroller with the corresponding interrupt type.
  • Page 40 When pulse width demodulation mode is enabled, INT4/PIO30 can be used as a PIO. LCS/ONCE0 Lower Memory Chip Select (output, synchronous, internal pullup) ONCE Mode Request 0 (input) LCS—This pin indicates to the system that a memory access is in progress to the lower memory block.
  • Page 41 If they are not programmed as PIOs and if MCS0 is programmed for the whole middle chip-select range, these signals operate normally. MCS3/RFSH/PIO25 Midrange Memory Chip Select 3 (output, synchronous, internal pullup) Automatic Refresh (output, synchronous) MCS3—This pin indicates to the system that a memory access is in progress to the fourth region of the midrange memory block.
  • Page 42 An NMI transition from Low to High is latched and synchronized internally, and it initiates the interrupt at the next instruction boundary. To guarantee that the interrupt is recognized, the NMI pin must be asserted for at least one CLKOUTA period. PCS1–PCS0 (PCS1/PIO17, PCS0/PIO16) Peripheral Chip Selects (output, synchronous)
  • Page 43 PCS3/RTS1/RTR1/PIO19 Peripheral Chip Select 3 (output, synchronous) Ready-to-Send 1 (output, asynchronous) Ready-to-Receive 1 (output, asynchronous) PCS3—This pin provides the Peripheral Chip Select 3 signal to the system when hardware flow control is not enabled for asynchronous serial port 1. The PCS3 signal indicates to the system that a memory access is in progress to the corresponding region of the peripheral memory block (either I/O or memory address space).
  • Page 44 Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers.

  • Page 45: Table 3-1 Numeric Pio Pin Designations

    Table 3-1 Numeric PIO Pin Designations PIO No Associated Pin Power-On Reset Status TMRIN1 Input with pullup TMROUT1 Input with pulldown PCS6/A2 Input with pullup PCS5/A1 Input with pullup DT/R Normal operation DEN/DS Normal operation SRDY Normal operation Normal operation Normal operation Normal operation TMROUT0...

  • Page 46: Table 3-2 Alphabetic Pio Pin Designations

    Table 3-2 Alphabetic PIO Pin Designations Associated Pin PIO No Power-On Reset Status Normal operation Normal operation Normal operation CTS0/ENRX0 Input with pullup DEN/DS Normal operation DRQ0/INT5 Input with pullup DRQ1/INT6 Input with pullup DT/R Normal operation INT2/INTA0/PWD Input with pullup INT4 Input with pullup MCS0...
  • Page 47 Read Strobe (output, synchronous, three-state) RD—This pin indicates to the system that the microcontroller is performing a memory or I/O read cycle. RD is guaranteed to not be asserted before the address and data bus is floated during the address- to-data transition.
  • Page 48 hardware flow control is enabled for the port (FC bit in the serial port 0 control register is set). The RTR0 signal is asserted when the associated serial port receive register does not contain valid, unread data. RXD0/PIO23 Receive Data 0 (input, asynchronous) This pin supplies asynchronous serial receive data from the system to asynchronous serial port 0.
  • Page 49 defaults to a PIO input with pullup, so the pin does not need to be driven High externally. SRDY/PIO6 Synchronous Ready (input, synchronous, level-sensitive) This pin indicates to the microcontroller that the addressed memory space or I/O device will complete a data transfer. The SRDY pin accepts an active High input synchronized to CLKOUTA.
  • Page 50 UCS/ONCE1 Upper Memory Chip Select (output, synchronous) ONCE Mode Request 1 (input, internal pullup) UCS—This pin indicates to the system that a memory access is in progress to the upper memory block. The base address and size of the upper memory block are programmable up to 512 Kbytes. UCS is held High during a bus hold condition.

  • Page 51: Pins That Are Used By Emulators

    WB—On the Am188ES microcontroller, this pin indicates a write to the bus. WB uses the same early timing as the nonmultiplexed address bus. WB is associated with AD7–AD0. This pin floats during reset. Write Strobe (output, synchronous) WR—This pin indicates to the system that the data on the bus is to be written to a memory or I/O device.

  • Page 52: Bus Operation

    BUS OPERATION The industry-standard 80C186 and 80C188 microcontrollers use a multiplexed address and data (AD) bus. The address is present on the AD bus only during the t clock phase. The Am186ES and Am188ES microcontrollers continue to provide the multiplexed AD bus and, in addition, provide a nonmultiplexed address (A) bus.

  • Page 53: Figure 3-1 Am186Es Microcontroller Address Bus-Normal Read And

    Figure 3-1 Am186ES Microcontroller Address Bus—Normal Read and Write Operation Address Data Phase Phase CLKOUTA A19–A0 Address AD15–AD0 Address Data (Read) AD15–AD0 Address Data (Write) LCS or UCS MCSx, PCSx Figure 3-2 Am186ES Microcontroller—Read and Write with Address Bus Disable In Effect Address Data Phase...

  • Page 54: Figure 3-3 Am188Es Microcontroller Address Bus-Normal Read

    Figure 3-3 Am188ES Microcontroller Address Bus—Normal Read and Write Operation Address Data Phase Phase CLKOUTA A19–A0 Address AD7–AD0 Address Data (Read) AO15–AO8 Address (Read or Write) AD7–AD0 Address Data (Write) LCS or UCS MCSx, PCSx Figure 3-4 Am188ES Microcontroller—Read and Write with Address Bus Disable In Effect Address Data Phase...

  • Page 55: Bus Interface Unit

    BUS INTERFACE UNIT The bus interface unit controls all accesses to external peripherals and memory devices. External accesses include those to memory devices, as well as those to memory-mapped and I/O-mapped peripherals and the peripheral control block. The Am186ES and Am188ES microcontrollers provide an enhanced bus interface unit with the following features: A nonmultiplexed address bus On the Am186ES microcontroller, a static bus sizing option for 8-bit and 16-bit memory...

  • Page 56: Byte Write Enables

    Table 3-3 Programming Am186ES Microcontroller Bus Width AUXCON Space Value Comments Field Width – – 16 bits not configurable LSIZ 16 bits default 8 bits IOSIZ 16 bits default 8 bits Other MSIZ 16 bits default 8 bits 3.3.3 Byte Write Enables The Am186ES microcontroller provides two signals that act as byte write enables—WHB (Write High Byte, AD15–AD8) and WLB (Write Low Byte, AD7–AD0).

  • Page 57: Clock And Power Management Unit

    High during a refresh cycle. The A19–A0 bus is not used during refresh cycles. The LMCS register must be configured to external Ready ignored (R2=1) with one wait state (R1– R0=01b), and the PSRAM mode enable bit (PSE) must be set to 1. See section 5.5.2 on page 5-6.

  • Page 58: Figure 3-5 Oscillator Configurations

    3.4.2.1 Selecting a Crystal When selecting a crystal, the load capacitance should always be specified (C ). This value can cause variance in the oscillation frequency from the desired specified value (resonance). The load capacitance and the loading of the feedback network have the following relationship: ⋅...

  • Page 59: External Source Clock

    3.4.3 External Source Clock Alternately, the internal oscillator can be driven from an external clock source. This source should be connected to the input of the inverting amplifier (X1) with the output (X2) not connected. 3.4.4 System Clocks Figure 3-6 shows the organization of the clocks. The original 80C186/188 microcontroller system clock has been renamed CLKOUTA.
  • Page 60 3-28 System Overview...

  • Page 61: Peripheral Control Block

    CHAPTER PERIPHERAL CONTROL BLOCK OVERVIEW The Am186ES and Am188ES microcontroller integrated peripherals are controlled by 16- bit read/write registers. The peripheral registers are contained within an internal 256-byte control block—the peripheral control block. Registers are physically located in the peripheral devices they control, but they are addressed as a single 256-byte block. Table 4-1 shows a map of the peripheral control block registers.

  • Page 62: Figure 4-5 System Configuration Register

    Table 4-1 Peripheral Control Block Register Map Register Name Offset Page Register Name Offset Page Processor Control Registers: Chapters 4 and 6 Timer Registers: Chapter 8 Peripheral control block relocation register Timer 2 mode/control register Reset configuration register Timer 2 max count compare A register Timer 2 count register Processor release level register Timer 1 mode/control register...

  • Page 63: Peripheral Control Block Relocation Register

    4.1.1 Peripheral Control Block Relocation Register (RELREG, Offset FEh) The peripheral control block is mapped into either memory or I/O space by programming the Peripheral Control Block Relocation (RELREG) register (see Figure 4-1). This register is a 16-bit register at offset FEh from the control block base address. The Peripheral Control Block Relocation register provides the upper 12 bits of the base address of the control block.

  • Page 64: Reset Configuration Register (Rescon, Offset F6H)

    4.1.2 Reset Configuration Register (RESCON, Offset F6h) The Reset Configuration (RESCON) register (see Figure 4-2) in the peripheral control block latches system-configuration information that is presented to the processor on the address/ data bus (AD15–AD0 for the 186 or AO15–AO8 and AD7–AD1 for the 188) during the rising edge of reset.

  • Page 65: Processor Release Level Register (Prl, Offset F4H)

    4.1.3 Processor Release Level Register (PRL, Offset F4h) The Processor Release Level register (Figure 4-3) is a read-only register that specifies the processor version. Figure 4-3 Processor Release Level Register Reserved Bits 15–8: Processor Release Level (PRL)—This byte returns the current release level of the processor, as well as the identification of the family member.

  • Page 66: Auxiliary Configuration Register (Auxcon, Offset F2H)

    4.1.4 Auxiliary Configuration Register (AUXCON, Offset F2h) The auxiliary configuration register is used to configure the asynchronous serial port flow- control signals and to configure the data bus width for memory and I/O accesses. The format of the auxiliary configuration register is shown in Figure 4-4. Figure 4-4 Auxiliary Configuration Register Reserved...

  • Page 67: System Configuration Register (Syscon, Offset F0H)

    4.1.5 System Configuration Register (SYSCON, Offset F0h) The format of the system configuration register is shown in Figure 4-5. Figure 4-5 System Configuration Register 0 0 0 0 0 PSEN MCSBIT DSDEN The value of the SYSCON register at reset is 0000h. Bit 15: Enable Power-Save Mode (PSEN)—When set to 1, enables power-save mode and divides the internal operating clock by the value in F2–F0.

  • Page 68: Initialization And Processor Reset

    CLKOUTB can be used as a full-speed clock source in power-save mode. Bit 10: CLKOUTB Drive Disable (CBD)—When set to 1, CBD three-states the clock output driver for CLKOUTB. When set to 0, CLKOUTB is driven as an output. This bit is 0 after processor reset.

  • Page 69: Table 4-3 Initial Register State After Reset

    Table 4-3 Initial Register State After Reset Value at Register Name Mnemonic Reset Comments Processor Status Flags FLAGS F002h Interrupts disabled Instruction Pointer 0000h Code Segment FFFFh Boot address is FFFF0h Data Segment 0000h DS = ES = SS = 0000h Extra Segment 0000h Stack Segment...
  • Page 70 Value at Register Name Mnemonic Reset Comments INT1 interrupt masked, edge-triggered, INT1 Control I1CON 000Fh priority 7 INT0 interrupt masked, edge-triggered, INT0 Control I0CON 000Fh priority 7 DMA1 interrupts masked, edge- DMA1 Interrupt Control/INT6 DMA1CON 000Fh triggered, priority 7 DMA0 interrupts masked, edge- DMA0 Interrupt Control/INT5 DMA0CON 000Fh triggered, priority 7...

  • Page 71: Chapter 5 Chip Select Unit

    CHAPTER CHIP SELECT UNIT OVERVIEW The Am186ES and Am188ES microcontrollers contain logic that provides programmable chip select generation for both memories and peripherals. In addition, the logic can be programmed to provide ready or wait-state generation and latched address bits A1 and A2. The chip select lines are active for all memory and I/O cycles in their programmed areas, whether they are generated by the CPU or by the integrated DMA unit.

  • Page 72: Chip Select Timing

    Except for the UCS chip select, which is active on reset as discussed in Section 5.5.1, chip selects are not activated until the associated registers have been accessed. (An access is any write operation and only write operations activate.) For this reason, the chip select registers should not be read by the processor initialization code until after they have been written with valid data.

  • Page 73: Chip Select Registers

    overlap must have the same configuration for ready (external ready required or not required) and the number of wait states to be inserted into the cycle by the processor. The peripheral control block (PCB) is accessed using internal signals. These internal signals function as chip selects configured with zero wait states and no external ready.

  • Page 74: Upper Memory Chip Select Register (Umcs, Offset A0H)

    5.5.1 Upper Memory Chip Select Register (UMCS, Offset A0h) The Am186ES and Am188ES microcontrollers provide the UCS chip select pin for the top of memory. On reset, the microcontroller begins fetching and executing instructions starting at memory location FFFF0h, so upper memory is usually used as instruction memory. To facilitate this usage, UCS defaults to active on reset with a default memory range of 64 Kbytes from F0000h to FFFFFh, with external ready required and three wait states automatically inserted.
  • Page 75 Bits 11–8: Reserved Bit 7: Disable Address (DA)—The DA bit enables or disables the AD15–AD0 bus during the address phase of a bus cycle when UCS is asserted. If DA is set to 1, AD15–AD0 is not driven during the address phase of a bus cycle when UCS is asserted. If DA is set to 0, AD15–AD0 is driven during the address phase of a bus cycle.

  • Page 76: Low Memory Chip Select Register (Lmcs, Offset A2H)

    5.5.2 Low Memory Chip Select Register (LMCS, Offset A2h) The Am186ES and Am188ES microcontrollers provide the LCS chip select pin for the bottom of memory. Since the interrupt vector table is located at 00000h at the bottom of memory, the LCS pin has been provided to facilitate this usage. The LCS pin is not active on reset, but any write access to the LMCS register activates this pin.
  • Page 77 Bits 11–8: Reserved—Set to 1. Bit 7: Disable Address (DA)—The DA bit enables or disables the AD15–AD0 bus during the address phase of a bus cycle when LCS is asserted. If DA is set to 1, AD15–AD0 is not driven during the address phase of a bus cycle when LCS is asserted. If DA is set to 0, AD15–AD0 is driven during the address phase of a bus cycle.

  • Page 78: Midrange Memory Chip Select Register (Mmcs, Offset A6H)

    5.5.3 Midrange Memory Chip Select Register (MMCS, Offset A6h) The Am186ES and Am188ES microcontrollers provide four chip select pins, MCS3–MCS0, for use within a user-locatable memory block. The base address of the memory block can be located anywhere within the 1-Mbyte memory address space, exclusive of the areas associated with the UCS and LCS chip selects (and, if they are mapped to memory, the address range of the Peripheral Chip Selects, PCS6–PCS5 and PCS3–PCS0).
  • Page 79 Bits 8–3: Reserved—Set to 1. Bit 2: Ready Mode (R2)—The R2 bit is used to configure the ready mode for the MCS chip selects. If R2 is set to 0, external ready is required. If R2 is set to 1, external ready is ignored.

  • Page 80: Pcs And Mcs Auxiliary Register (Mpcs, Offset A8H)

    5.5.4 PCS and MCS Auxiliary Register (MPCS, Offset A8h) The PCS and MCS Auxiliary (MPCS) register (see Figure 5-4) differs from the other chip select control registers in that it contains fields that pertain to more than one type of chip select.
  • Page 81 Bit 7: Pin Selector (EX)—This bit determines whether the PCS6–PCS5 pins are configured as chip selects or as alternate outputs for A2–A1. When this bit is set to 1, PCS6–PCS5 are configured as peripheral chip select pins. When EX is set to 0, PCS5 becomes address bit A1 and PCS6 becomes address bit A2.

  • Page 82: Peripheral Chip Select Register (Pacs, Offset A4H)

    5.5.5 Peripheral Chip Select Register (PACS, Offset A4h) Unlike the UCS and LCS chip selects, the PCS outputs assert with the same timing as the multiplexed AD address bus. Also, each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers.

  • Page 83: Table 5-5 Pcs Address Ranges

    Table 5-5 PCS Address Ranges Range PCS Line High PCS0 Base Address Base Address+255 PCS1 Base Address+256 Base Address+511 PCS2 Base Address+512 Base Address+767 PCS3 Base Address+768 Base Address+1023 Reserved N/A PCS5 Base Address+1280 Base Address+1535 PCS6 Base Address+1536 Base Address+1791 Bits 6–4: Reserved—Set to 1.
  • Page 84 5-14 Chip Select Unit...

  • Page 85: Chapter 6 Refresh Control Unit

    CHAPTER REFRESH CONTROL UNIT OVERVIEW The Refresh Control Unit (RCU) automatically generates refresh bus cycles. After a programmable period of time, the RCU generates a memory read request to the bus interface unit. The RCU is fixed to three wait states for the PSRAM auto refresh mode. The Refresh Control Unit operates off the processor internal clock.

  • Page 86: Clock Prescaler Register (Cdram, Offset E2H)

    6.1.2 Clock Prescaler Register (CDRAM, Offset E2h) Figure 6-2 Clock Prescaler Register 0 0 0 0 0 RC8–RC0 The CDRAM register is undefined on reset. Bits 15–9: Reserved—Read back as 0. Bits 8–0: Refresh Counter Reload Value (RC8–RC0)—Contains the value of the desired clock count interval between refresh cycles.

  • Page 87: Watchdog Timer Control Register (Wdtcon, Offset E6H)

    6.1.4 Watchdog Timer Control Register (WDTCON, Offset E6h) The Watchdog Timer Control register is a combined status and control register through which all watchdog timer functionality is implemented. The format of the watchdog timer control register is shown in Figure 6-4. The watchdog timer (WDT) is enabled out of reset and configured to system reset mode with a maximum timeout count.

  • Page 88: Table 6-1 Watchdog Timer Count Settings

    Bit 11: Test Mode (TEST)—This bit is reserved for an internal test mode. Setting this bit activates a special test mode that generates early WDT timeouts. This bit is 0 after processor reset. Bits 10–8: Reserved Bits 7–0: WDT Timeout Count (COUNT)—This field determines the duration of the watchdog timer timeout interval.

  • Page 89: Chapter 7 Interrupt Control Unit

    CHAPTER INTERRUPT CONTROL UNIT OVERVIEW The Am186ES and Am188ES microcontrollers can receive interrupt requests from a variety of sources, both internal and external. The internal interrupt controller arranges these requests by priority and presents them one at a time to the CPU. There are up to eight external interrupt sources on the Am186ES and Am188ES microcontrollers—seven maskable interrupt pins (INT6–INT0) and one nonmaskable interrupt (NMI) pin.
  • Page 90 Software exceptions, internal peripherals, and non-cascaded external interrupts supply the interrupt type through the internal interrupt controller. Cascaded external interrupts and slave-mode external interrupts get the interrupt type from the external interrupt controller by means of interrupt acknowledge cycles on the bus. 7.1.1.2 Interrupt Vector Table The interrupt vector table is a memory area of 1 Kbyte beginning at address 00000h that...
  • Page 91 7.1.1.6 Interrupt Priority The column titled Overall Priority in Table 7-1 shows the fundamental priority breakdown for the interrupts at power-on reset. The nonmaskable interrupts 00h through 07h are always prioritized ahead of the maskable interrupts. The maskable interrupts can be reprioritized by reconfiguring the PR2–PR0 bits in the interrupt control registers.

  • Page 92: Table 7-1 Am186Es And Am188Es Microcontroller Interrupt Types

    ESC Opcodes 1, 3 Timer 0 Interrupt 4, 5 Timer 1 Interrupt 4, 5 Timer 2 Interrupt 4, 5 Reserved for AMD Use DMA 0 Interrupt/INT5 DMA 1 Interrupt/INT6 INT0 Interrupt INT1 Interrupt INT2 Interrupt INT3 Interrupt INT4 Interrupt Asynchronous Serial Port 1 Interface...

  • Page 93: Interrupt Conditions And Sequence

    7.1.2 Interrupt Conditions and Sequence Interrupts are generally serviced as follows. 7.1.2.1 Nonmaskable Interrupts Nonmaskable interrupts—the trace interrupt, the NMI interrupt, and software interrupts (both user-defined (INT) and software exceptions)—are serviced regardless of the setting of the interrupt enable flag (IF) in the processor status flags. 7.1.2.2 Maskable Hardware Interrupts In order for maskable hardware interrupt requests to be serviced, the IF flag must be set...

  • Page 94: Interrupt Priority

    7.1.3 Interrupt Priority Table 7-1 shows the predefined types and overall priority structure for the Am186ES and Am188ES microcontrollers. Nonmaskable interrupts (interrupt types 0–7) are always higher priority than maskable interrupts. Maskable interrupts have a programmable priority that can override the default priorities relative to one another. The levels of interrupt priority are as follows: Interrupt priority for nonmaskable interrupts and software interrupts Interrupt priority for maskable hardware interrupts...

  • Page 95: Software Exceptions, Traps, And Nmi

    7.1.4 Software Exceptions, Traps, and NMI The following predefined interrupts cannot be masked by programming. 7.1.4.1 Divide Error Exception (Interrupt Type 00h) Generated when a DIV or IDIV instruction quotient cannot be expressed in the number of destination bits. 7.1.4.2 Trace Interrupt (Interrupt Type 01h) If the trace flag (TF) in the processor status flags register is set, the trace interrupt is generated after most instructions.

  • Page 96: Interrupt Acknowledge

    7.1.4.8 ESC Opcode Exception (Interrupt Type 07h) Generated if execution of ESC opcodes (D8h–DFh) is attempted. The microcontrollers do not check the escape opcode trap bit. The return address of this exception points to the ESC instruction that caused the exception. If a segment override prefix preceded the ESC instruction, the return address points to the segment override prefix.

  • Page 97: Interrupt Controller Reset Conditions

    7.1.6 Interrupt Controller Reset Conditions On reset, the interrupt controller performs the following nine actions: 1. All special fully nested mode (SFNM) bits are reset, implying fully nested mode. 2. All priority (PR) bits in the various control registers are set to 1. This places all sources at the lowest priority (level 7).

  • Page 98: Master Mode Operation

    MASTER MODE OPERATION This section describes master mode operation of the internal interrupt controller. See Section 7.4 on page 7-28 for a description of slave mode operation. Eight pins are provided for external interrupt sources. One of these pins is NMI, the nonmaskable interrupt.

  • Page 99: Cascade Mode

    7.2.2 Cascade Mode The Am186ES and Am188ES microcontrollers have seven interrupt pins, two of which (INT2 and INT3) have dual functions. In fully nested mode, the seven pins are used as direct interrupt inputs and the corresponding interrupt types are generated internally. In cascade mode, four of the seven pins can be configured into interrupt input and dedicated acknowledge signal pairs.

  • Page 100: Special Fully Nested Mode

    7.2.3 Special Fully Nested Mode Special fully nested mode is entered by setting the SFNM bit in the INT0 or INT1 control registers. (See Section 7.3.1 on page 7-14.) It enables complete nesting with external 82C59A masters or multiple interrupts from the same external interrupt pin when not in cascade mode.

  • Page 101: Master Mode Interrupt Controller Registers

    MASTER MODE INTERRUPT CONTROLLER REGISTERS The interrupt controller registers for master mode are shown in Table 7-2. All the registers can be read and written unless otherwise specified. Registers can be redefined in slave mode. See Section 7.4 on page 7-28 for detailed information regarding slave mode register usage.

  • Page 102: Int0 And Int1 Control Registers

    7.3.1 INT0 and INT1 Control Registers (I0CON, Offset 38h, I1CON, Offset 3Ah) (Master Mode) The INT0 interrupt is assigned to interrupt type 0Ch. The INT1 interrupt is assigned to interrupt type 0Dh. When cascade mode is enabled for INT0 by setting the C bit of I0CON to 1, the INT2 pin becomes INTA0, the interrupt acknowledge for INT0.

  • Page 103: Int2 And Int3 Control Registers

    7.3.2 INT2 and INT3 Control Registers (I2CON, Offset 3Ch, I3CON, Offset 3Eh) (Master Mode) The INT2 interrupt is assigned to interrupt type OEh. The INT3 interrupt is assigned to interrupt type 0Fh. The INT2 and INT3 pins can be configured as interrupt acknowledge pins INTA0 and INTA1 when cascade mode is implemented.

  • Page 104: Int4 Control Register (I4Con, Offset 40H)

    7.3.3 INT4 Control Register (I4CON, Offset 40h) (Master Mode) The Am186ES and Am188ES microcontrollers provide INT4, an additional external interrupt pin. This input behaves like INT3–INT0 on the 80C186 microcontroller with the exception that INT4 is only intended for use as a fully nested-mode interrupt source. INT4 is not available in cascade mode.

  • Page 105: Timer And Dma Interrupt Control Registers (Tcucon, Offset 32H, Dma0Con/Int5Con, Offset 34H, Dma1Con/Int6Con, Offset 36H)

    7.3.4 Timer and DMA Interrupt Control Registers (TCUCON, Offset 32h, DMA0CON/INT5CON, Offset 34h, DMA1CON/ INT6CON, Offset 36h) (Master Mode) The three timer interrupts are assigned to interrupt type 08h, 12h, and 13h. All three timer interrupts are configured through TCUCON, offset 32h. The DMA0 interrupt is assigned to interrupt type 0Ah.

  • Page 106: Serial Port 0/1 Interrupt Control Registers

    7.3.5 Serial Port 0/1 Interrupt Control Registers (SP0CON/SP1CON, Offset 44h/42h) (Master Mode) The serial port interrupt control registers control the operation of the serial ports’ interrupt source (SP1 and SP0, bits 10–9 in the interrupt request register). Serial port 0 is assigned to interrupt type 14h and serial port 1 is assigned to interrupt type 11h.

  • Page 107: Interrupt Status Register (Intsts, Offset 30H)

    7.3.6 Interrupt Status Register (INTSTS, Offset 30h) (Master Mode) The interrupt status register indicates the interrupt request status of the three timers. Figure 7-9 Interrupt Status Register Reserved TMR2 TMR0 DHLT TMR1 Bit 15: DMA Halt (DHLT)—When set to 1, halts any DMA activity. This bit is automatically set to 1 when nonmaskable interrupts occur and is reset when an IRET instruction is executed.

  • Page 108: Interrupt Request Register (Reqst, Offset 2Eh)

    7.3.7 Interrupt Request Register (REQST, Offset 2Eh) (Master Mode) The hardware interrupt sources have interrupt request bits inside the interrupt controller. A read from this register yields the status of these bits. The Interrupt Request register is a read-only register. The format of the Interrupt Request register is shown in Figure 7-10. For internal interrupts (SP0, SP1, D1/I6, D0/I5, and TMR), the corresponding bit is set to 1 when the device requests an interrupt.
  • Page 109 Bit 0: Timer Interrupt Request (TMR)—This bit indicates the state of the timer interrupts. This bit is the logical OR of the timer interrupt requests. When set to a 1, this bit indicates that the timer control unit has an interrupt pending. The interrupt status register indicates the specific timer that is requesting an interrupt.

  • Page 110: Interrupt In-Service Register (Inserv, Offset 2Ch)

    7.3.8 Interrupt In-Service Register (INSERV, Offset 2Ch) (Master Mode) The bits in the In-Service register are set by the interrupt controller when the interrupt is taken. Each bit in the register is cleared by writing the corresponding interrupt type to the End-of-Interrupt (EOI) register.

  • Page 111: Priority Mask Register (Primsk, Offset 2Ah)

    7.3.9 Priority Mask Register (PRIMSK, Offset 2Ah) (Master Mode) The Priority Mask register provides the value that determines the minimum priority level at which maskable interrupts can generate an interrupt. Figure 7-12 Priority Mask Register 0 0 0 0 0 0 PRM2 PRM1 PRM0...

  • Page 112: Interrupt Mask Register (Imask, Offset 28H)

    7.3.10 Interrupt Mask Register (IMASK, Offset 28h) (Master Mode) The Interrupt Mask register is a read/write register. Programming a bit in the Interrupt Mask register has the effect of programming the MSK bit in the associated interrupt control register. The format of the Interrupt Mask register is shown in Figure 7-13. When a bit is set to 1 in this register, the corresponding interrupt source is masked off.

  • Page 113: Poll Status Register (Pollst, Offset 26H)

    7.3.11 Poll Status Register (POLLST, Offset 26h) (Master Mode) The Poll Status register mirrors the current state of the Poll register. The Poll Status register can be read without affecting the current interrupt request. But when the Poll register is read, the current interrupt is acknowledged and the next interrupt takes its place in the Poll register.

  • Page 114: Poll Register (Poll, Offset 24H)

    7.3.12 Poll Register (POLL, Offset 24h) (Master Mode) When the Poll register is read, the current interrupt is acknowledged and the next interrupt takes its place in the Poll register. The Poll Status register mirrors the current state of the Poll register, but the Poll Status register can be read without affecting the current interrupt request.

  • Page 115: End-Of-Interrupt Register (Eoi, Offset 22H)

    7.3.13 End-of-Interrupt Register (EOI, Offset 22h) (Master Mode) The End-of-Interrupt (EOI) register is a write-only register. The in-service flags in the In- Service register (see Section 7.3.8 on page 7-22) are reset by writing to the EOI register. Before executing the IRET instruction that ends an interrupt service routine (ISR), the ISR should write to the EOI register to reset the IS bit for the interrupt.

  • Page 116: Slave Mode Operation

    SLAVE MODE OPERATION When slave mode is used, the internal microcontroller interrupt controller is used as a slave controller to an external master interrupt controller. The internal interrupts are monitored by the internal interrupt controller, while the external controller functions as the system master interrupt controller.

  • Page 117: Timer And Dma Interrupt Control Registers

    7.4.3 Timer and DMA Interrupt Control Registers (T0INTCON, Offset 32h, T1INTCON, Offset 38h, T2INTCON, Offset 3Ah, DMA0CON/INT5, Offset 34h, DMA1CON/INT6, Offset 36h) (Slave Mode) In slave mode, there are three separate registers for the three timers. In master mode, all three timers are masked and prioritized in one register TCUCON.

  • Page 118: Interrupt Status Register (Intsts, Offset 30H)

    7.4.4 Interrupt Status Register (INTSTS, Offset 30h) (Slave Mode) The Interrupt Status register controls DMA activity when nonmaskable interrupts occur and indicates the current interrupt status of the three timers. Figure 7-19 Interrupt Status Register Reserved DHLT TMR1 TMR2 TMR0 The INTSTS register is set to 0000h on reset.

  • Page 119: Interrupt Request Register (Reqst, Offset 2Eh)

    7.4.5 Interrupt Request Register (REQST, Offset 2Eh) (Slave Mode) The internal interrupt sources have interrupt request bits inside the interrupt controller. A read from this register yields the status of these bits. The Interrupt Request register is a read-only register. The format of the Interrupt Request register is shown in Figure 7-20. For internal interrupts (D1/I6, D0/I5, TMR2, TMR1, and TMR0), the corresponding bit is set to 1 when the device requests an interrupt.

  • Page 120: Interrupt In-Service Register (Inserv, Offset 2Ch)

    7.4.6 Interrupt In-Service Register (INSERV, Offset 2Ch) (Slave Mode) The format of the In-Service register is shown in Figure 7-21. The bits in the In-Service register are set by the interrupt controller when the interrupt is taken. The in-service bits are cleared by writing to the End-of-Interrupt (EOI) register.

  • Page 121: Priority Mask Register (Primsk, Offset 2Ah)

    7.4.7 Priority Mask Register (PRIMSK, Offset 2Ah) (Slave Mode) The format of the Priority Mask register is shown in Figure 7-22. The Priority Mask register provides the value that determines the minimum priority level at which maskable interrupts can generate an interrupt. Figure 7-22 Priority Mask Register Reserved...

  • Page 122: Interrupt Mask Register (Imask, Offset 28H)

    7.4.8 Interrupt Mask Register (IMASK, Offset 28h) (Slave Mode) The format of the Interrupt Mask register is shown in Figure 7-23. The Interrupt Mask register is a read/write register. Programming a bit in the Interrupt Mask register has the effect of programming the MSK bit in the associated control register.

  • Page 123: Specific End-Of-Interrupt Register (Eoi, Offset 22H)

    7.4.9 Specific End-of-Interrupt Register (EOI, Offset 22h) (Slave Mode) In slave mode, a write to the EOI register resets an in-service bit of a specific priority. The user supplies a three-bit priority-level value that points to an in-service bit to be reset. The command is executed by writing the correct value in the Specific EOI register at offset 22h.

  • Page 124: Interrupt Vector Register (Intvec, Offset 20H)

    7.4.10 Interrupt Vector Register (INTVEC, Offset 20h) (Slave Mode) Vector generation in slave mode is exactly like that of an 8259A or 82C59A slave. The interrupt controller generates an 8-bit interrupt type that the CPU shifts left two bits (multiplies by four) to generate an offset into the interrupt vector table. Figure 7-25 Interrupt Vector Register 0 0 0...

  • Page 125: Timer Control Unit

    CHAPTER TIMER CONTROL UNIT OVERVIEW There are three 16-bit programmable timers in the Am186ES and Am188ES microcontrollers. Timers 0 and 1 are highly versatile and are each connected to two external pins (each one has an input and an output). These two timers can be used to count or time external events, or they can be used to generate nonrepetitive or variable-duty-cycle waveforms.

  • Page 126: Programmable Registers

    PROGRAMMABLE REGISTERS The timers are controlled by eleven 16-bit registers (see Table 8-1) that are located in the peripheral control block. Table 8-1 Timer Control Unit Register Summary Register Offset from PCB Mnemonic Register Name T0CON Timer 0 Mode/Control T1CON Timer 1 Mode/Control T2CON Timer 2 Mode/Control...

  • Page 127: Timer 0 And Timer 1 Mode And Control Registers (T0Con, Offset 56H, T1Con, Offset 5Eh)

    8.3.2 Timer 0 and Timer 1 Mode and Control Registers (T0CON, Offset 56h, T1CON, Offset 5Eh) These registers control the functionality of timer 0 and timer 1. See Figure 8-2. Figure 8-2 Timer 0 and Timer 1 Mode and Control Registers 0 0 0 0 0 CONT The value of T0CON and T1CON at reset is 0000h.
  • Page 128 Bit 1: Alternate Compare Bit (ALT)—When set to 1, the timer counts to maxcount compare A, then resets the count register to 0. Then the timer counts to maxcount compare B, resets the count register to zero, and starts over with maxcount compare A. If ALT is clear, the timer counts to maxcount compare A and then resets the count register to zero and starts counting again against maxcount compare A.

  • Page 129: Timer 2 Mode And Control Register (T2Con, Offset 66H)

    8.3.3 Timer 2 Mode and Control Register (T2CON, Offset 66h) This register controls the functionality of timer 2. See Figure 8-3. Figure 8-3 Timer 2 Mode and Control Register 0 0 0 0 0 CONT The value of T2CON at reset is 0000h. Bit 15: Enable Bit (EN)—When EN is set to 1, the timer is enabled.

  • Page 130: Timer Count Registers (T0Cnt, Offset 50H, T1Cnt, Offset 58H, T2Cnt, Offset 60H)

    8.3.4 Timer Count Registers (T0CNT, Offset 50h, T1CNT, Offset 58h, T2CNT, Offset 60h) These registers can be incremented by one every four internal processor clocks. Timer 0 and timer 1 can also be configured to increment based on the TMRIN0 and TMRIN1 external signals, or they can be prescaled by timer 2.

  • Page 131: Timer Maxcount Compare Registers (T0Cmpa, Offset 52H, T0Cmpb, Offset 54H, T1Cmpa, Offset 5Ah, T1Cmpb, Offset 5Ch, T2Cmpa, Offset 62H)

    8.3.5 Timer Maxcount Compare Registers (T0CMPA, Offset 52h, T0CMPB, Offset 54h, T1CMPA, Offset 5Ah, T1CMPB, Offset 5Ch, T2CMPA, Offset 62h) These registers serve as comparators for their associated count registers. Timer 0 and timer 1 each have two maximum count compare registers. See Figure 8-5. Timer 0 and timer 1 can be configured to count and compare to register A and then count and compare to register B.
  • Page 132 Timer Control Unit...

  • Page 133: Dma Controller

    CHAPTER DMA CONTROLLER OVERVIEW Direct memory access (DMA) permits transfer of data between memory and peripherals without CPU involvement. The DMA unit in the Am186ES and Am188ES microcontrollers provides two high-speed DMA channels. Data transfers can occur between memory and I/O spaces (e.g., memory to I/O) or within the same space (e.g., memory-to-memory or I/ O-to-I/O).
  • Page 134 Figure 9-1 DMA Unit Block Diagram Adder Control 20-bit Adder/Subtractor Logic Timer Request DRQ1/Serial Port Request Selection DRQ0/Serial Port Logic Transfer Counter Ch. 1 Destination Address Ch. 1 Source Address Ch. 1 Control Transfer Counter Ch. 0 Logic Destination Address Ch. 0 Interrupt Source Address Ch.

  • Page 135: Programmable Dma Registers

    PROGRAMMABLE DMA REGISTERS The following sections describe the control registers that are used to configure and operate the two DMA channels. 9.3.1 DMA Control Registers (D0CON, Offset CAh, D1CON, Offset DAh) The DMA control registers (see Figure 9-2) determine the mode of operation for the DMA channels.

  • Page 136: Table 9-2 Synchronization Type

    Bit 13: Destination Increment (DINC)—When DINC is set to 1, the destination address is automatically incremented after each transfer. The address increments by 1 or 2 depending on the byte/word bit (B/W, bit 0). The address remains constant if the increment and decrement bits are set to the same value (00b or 11b).

  • Page 137: Serial Port/Dma Transfers

    Bit 1: Start/Stop DMA Channel (ST)—The DMA channel is started when the start bit is set to 1. This bit can be modified only when the CHG bit is set to 1 during the same register write. This bit is 0 after processor reset. Bit 0: Byte/Word Select (B/W)—On the Am186ES microcontroller, when B/W is set to 1, word transfers are selected.

  • Page 138: Dma Transfer Count Registers (D0Tc, Offset C8H, D1Tc, Offset D8H)

    9.3.3 DMA Transfer Count Registers (D0TC, Offset C8h, D1TC, Offset D8h) Each DMA channel maintains a 16-bit DMA Transfer Count register (DTC). This register is decremented after each DMA cycle, regardless of the state of the TC bit in the DMA control register.

  • Page 139: Dma Destination Address High Register (High Order Bits) (D0Dsth, Offset C6H, D1Dsth, Offset D6H)

    9.3.4 DMA Destination Address High Register (High Order Bits) (D0DSTH, Offset C6h, D1DSTH, Offset D6h) Each DMA channel maintains a 20-bit destination and a 20-bit source register. Each 20-bit address takes up two full 16-bit registers (the high register and the low register) in the peripheral control block.

  • Page 140: Dma Destination Address Low Register (Low Order Bits) (D0Dstl, Offset C4H, D1Dstl, Offset D4H)

    9.3.5 DMA Destination Address Low Register (Low Order Bits) (D0DSTL, Offset C4h, D1DSTL, Offset D4h) Figure 9-5 shows the DMA Destination Address Low register. The sixteen bits of this register are combined with the four bits of the DMA Destination Address High register (see Figure 9-4) to produce a 20-bit destination address.

  • Page 141: Dma Source Address High Register (High Order Bits) (D0Srch, Offset C2H, D1Srch, Offset D2H)

    9.3.6 DMA Source Address High Register (High Order Bits) (D0SRCH, Offset C2h, D1SRCH, Offset D2h) Each DMA channel maintains a 20-bit destination and a 20-bit source register. Each 20-bit address takes up two full 16-bit registers (the high register and the low register) in the peripheral control block.

  • Page 142: Dma Source Address Low Register (Low Order Bits) (D0Srcl, Offset C0H, D1Srcl, Offset D0H)

    9.3.7 DMA Source Address Low Register (Low Order Bits) (D0SRCL, Offset C0h, D1SRCL, Offset D0h) Figure 9-7 shows the DMA Source Address Low register. The sixteen bits of this register are combined with the four bits of the DMA Source Address High register (see Figure 9-6) to produce a 20-bit source address.

  • Page 143: Dma Requests

    DMA REQUESTS Data transfers can be either source or destination synchronized—either the source of the data or the destination of the data can request the data transfer. DMA transfers can also be unsynchronized (i.e., the transfer takes place continually until the correct number of transfers has occurred).

  • Page 144: Synchronization Timing

    9.4.1 Synchronization Timing DRQ1 or DRQ0 must be deasserted before the end of the DMA transfer to prevent another DMA cycle from occurring. The timing for the required deassertion depends on whether the transfer is source-synchronized or destination-synchronized. 9.4.1.1 Source Synchronization Timing Figure 9-8 shows a typical source-synchronized DMA transfer.

  • Page 145: Dma Acknowledge

    Figure 9-9 Destination Synchronized DMA Transfers Fetch Cycle Deposit Cycle CLKOUT (First case) (Second case) Notes: 1. This destination-synchronized transfer is not followed immediately by another DMA transfer. 2. This destination-synchronized transfer is immediately followed by another DMA transfer because DRQ is not deasserted soon enough.

  • Page 146: Dma Channels On Reset

    by the write. If multiple channel registers are modified, a LOCKed string transfer should be used to prevent a DMA transfer from occurring between updates to the channel registers. 9.4.5 DMA Channels on Reset On reset, the state of the DMA channels is as follows: The ST bit for each channel is reset.

  • Page 147: Asynchronous Serial Ports

    CHAPTER ASYNCHRONOUS SERIAL PORTS 10.1 OVERVIEW The Am186ES and Am188ES microcontrollers provide two independent asynchronous serial ports. These ports provide full-duplex, bidirectional data transfer using several industry-standard communications protocols. The serial ports may be used as sources or destinations of DMA transfers. The asynchronous serial ports support the following features: Full-duplex operation 7-bit, 8-bit, or 9-bit data transfers...

  • Page 148: Table 10-1 Serial Port External Pins

    Table 10-1 Serial Port External Pins Designation Pin Function RXD0, RXD1 Receives serial port data TXD0, TXD1 Transmits serial port data CTS0, CTS1/ Clear to send or enable receiver ENRX0, ENRX1 request RTS0, RTS1/ Ready to send or ready to receive RTR0, RTR1 Each port is provided with two data pins (RXD0/RXD1 and TXD0/TXD1) and two flow control signals (RTS0, RTS1/RTR0, RTR1).

  • Page 149: Programmable Registers

    10.1.1.3 CTS/RTR Protocol Note: The clear-to-send/ready-to-receive (CTS/RTR) protocol provides flow control when both ports are sending and receiving data, as shown in Figure 10-2. Figure 10-2 CTS/RTR Protocol CTS = Clear to send input to transmitter RTR = Ready to receive output from receiver The Am186ES and Am188ES microcontrollers’...

  • Page 150: Table 10-2 Asynchronous Serial Port Register Summary

    Table 10-2 Asynchronous Serial Port Register Summary Register Offset from PCB Mnemonic Register Name SP0CT Serial Port 0 Control SP0STS Serial Port 0 Status SP0BAUD Serial Port 0 Baud Rate Divisor SP0RD Serial Port 0 Receive SP0TD Serial Port 0 Transmit SP1CT Serial Port 1 Control SP1STS...

  • Page 151: Serial Port 0/1 Control Registers (Sp0Ct/Sp1Ct, Offset 80H/10H)

    10.2.1 Serial Port 0/1 Control Registers (SP0CT/SP1CT, Offset 80h/10h) The serial port control registers control both the transmit and receive sections of the serial port. The format of the serial port control registers is shown in Figure 10-3. Figure 10-3 Serial Port Control Register MODE RSIE...
  • Page 152 When a DMA channel is being used for serial port transmits or receives, the DMA request is generated internally. The corresponding external DMA request signals, DRQ0 or DRQ1, are not active for serial port DMA transfers. Bit 12: Receive Status Interrupt Enable (RSIE)—This bit enables the serial port to generate an interrupt request when an exception occurs during data reception.

  • Page 153: Table 10-4 Serial Port Mode Settings

    Bit 8: Transmitter Ready Interrupt Enable (TXIE)—When this bit is set, the serial port generates an interrupt request whenever the transmit holding register is empty (THRE bit in the status register is set), indicating that the transmitter is available to accept a new character for transmission.
  • Page 154 bit reset (Low) is ignored. The transmit portion of the port behaves identically with mode 3 operation. This mode can be used in conjunction with mode 3 to allow for multidrop communications over a common serial link. In this case, the serial port is configured as mode 2 initially. Each time data is received with the ninth bit set, the data is compared by software against a unique ID for this receiver.

  • Page 155: Serial Port 0/1 Status Registers (Sp0Sts/Sp1Sts, Offset 82H/12H)

    10.2.2 Serial Port 0/1 Status Registers (SP0STS/SP1STS, Offset 82h/12h) The Serial Port Status Registers provide information about the current status of the associated serial port. The THRE and TEMT fields provide the software with information about the state of the transmitter. The BRK1, BRK0, RB8, RDR, FER, OER, and PER bits provide information about the receiver.
  • Page 156 Bit 5: Framing Error Detected (FER)—When this bit is set, the serial port has detected a framing error. Framing errors are generated when the receiver samples the RXD line as Low when it expected the stop bit . Note: This bit should be reset by software. Bit 4: Overrun Error Detected (OER)—This bit is set when the processor detects an overrun error.

  • Page 157: Serial Port 0/1 Transmit Registers (Sp0Td/Sp1Td, Offset 84H/14H)

    10.2.3 Serial Port 0/1 Transmit Registers (SP0TD/SP1TD, Offset 84h/14h) The transmit registers (Figure 10-5) are written by software with the value to be transmitted over the serial interface. The transmitter is double-buffered; data to be transmitted is copied from the transmit register to the transmit shift register (which is not accessible to software) before transmitting.

  • Page 158: Serial Port 0/1 Receive Registers (Sp0Rd/Sp1Rd, Offset 86H/16H)

    10.2.4 Serial Port 0/1 Receive Registers (SP0RD/SP1RD, Offset 86h/16h) These registers (Figure 10-6) contain data received over the serial port. The receiver is double-buffered; the receive section can be receiving a subsequent frame of data in the receive shift register (which is not accessible to software) while the receive data register is being read.

  • Page 159: Serial Port 0/1 Baud Rate Divisor Registers (Sp0Baud/Sp1Baud, Offset 88H/18H)

    10.2.5 Serial Port 0/1 Baud Rate Divisor Registers (SP0BAUD/SP1BAUD, Offset 88h/18h) Each of the asynchronous serial ports has a baud rate divisor register, so the two ports can operate at different rates. These registers (Figure 10-7) specify a clock divisor for the generation of the serial clock that controls the associated serial port.
  • Page 160 Divisor Based on CPU Clock Rate Baud 20 MHz 25 MHz 33 MHz 40 MHz Rate 128000 153600 Special 15 MHz 21 MHz 24 MHz 30 MHz 187500 Note: A 1% error applies to all values in the above tables. Figure 10-7 Serial Port 0/1 Baud Rate Divisor Registers BAUDDIV...

  • Page 161: Programmable I/O Pins

    CHAPTER PROGRAMMABLE I/O PINS 11.1 OVERVIEW Thirty-two pins on the Am186ES and Am188ES microcontrollers are available as user- programmable I/O signals (PIOs). Each of these pins can be used as a PIO if the normal function of the pin is not needed. If a pin is enabled to function as a PIO signal, the normal function is disabled and does not affect the pin.

  • Page 162: Table 11-1 Pio Pin Assignments

    Table 11-1 PIO Pin Assignments PIO No Associated Pin Power-On Reset Status TMRIN1 Input with pullup TMROUT1 Input with pulldown PCS6/A2 Input with pullup PCS5/A1 Input with pullup DT/R Normal operation DEN/DS Normal operation Normal operation SRDY Normal operation Normal operation Normal operation TMROUT0 Input with pulldown...

  • Page 163: Pio Mode Registers

    11.2 PIO MODE REGISTERS Table 11-2 shows the possible settings for the PIO Mode and PIO Direction bits. The Am186ES and Am188ES microcontrollers default the 32 PIO pins to either 00b (normal operation) or 01b (PIO input with weak internal pullup or pulldown enabled). Pins that default to active High outputs at reset are pulled down.

  • Page 164: Pio Direction Registers

    11.3 PIO DIRECTION REGISTERS Each PIO is individually programmed as an input or output by a bit in one of the PIO Direction registers (see Figure 11-4 and Figure 11-5). Table 11-2 on page 11-3 shows the values that the PIO mode bits and the PIO direction bits can encode. The column titled Power-On Reset Status in Table 11-1 lists the reset default values for the PIOs.

  • Page 165: Pio Data Registers

    11.4 PIO DATA REGISTERS If a PIO pin is enabled as an output, the value in the corresponding bit in one of the PIO Data registers (see Figure 11-6 and Figure 11-7) is driven on the pin with no inversion (Low=0, High=1).
  • Page 166 11-6 Programmable I/O Pins...

  • Page 167: Register Summary

    APPENDIX REGISTER SUMMARY This appendix summarizes the peripheral control block registers. Table A-1 lists all the registers. Figure A-1 shows the layout of each of the internal registers. The column titled Comment in Table A-1 is used to identify the specific use of interrupt registers when there is a mix of master mode and slave mode usage.
  • Page 168 Hex Offset Mnemonic Comment Register Description LMCS Low memory chip select register UMCS Upper memory chip select register SP0BAUD Serial port 0 baud rate divisor register SP0RD Serial port 0 receive data register SP0TD Serial port 0 transmit data register SP0STS Serial port 0 status register SP0CT...
  • Page 169 Hex Offset Mnemonic Comment Register Description DMA0CON/ DMA 0 interrupt control register/INT5 Slave & master INT5CON TCUCON Timer interrupt control register Master mode T0INTCON Timer 0 interrupt control register Slave mode INTSTS Interrupt status register Slave & master REQST Interrupt request register Slave &...
  • Page 170 Figure A-1 Internal Register Summary Offset (Hexadecimal) R19–R8 Res S/M Res M/IO Peripheral Control Block Relocation Register (RELREG) Page 4-3 Reset Configuration Register (RESCON) Page 4-4 Reserved Processor Release Level Register (PRL) Page 4-5 Reserved ENRX1 LSIZ ENRX0 IOSIZ RTS1 MSIZ RTS0 Auxiliary Configuration Register (AUXCON)
  • Page 171 Figure A-1 Internal Register Summary (continued) Reserved COUNT RSTFLAG TEST WRST NMIFLAG Watchdog Timer Control Register (WDTCON) Page 6-3 T8–T0 Enable RCU Register (EDRAM) Page 6-2 RC8–RC0 Clock Prescaler Register (CDRAM) Page 6-2 M6–M0 RA19 RA13 Memory Partition Register (MDRAM) Page 6-1 INT SYN1–SYN0 TDRQ...
  • Page 172 Figure A-1 Internal Register Summary (continued) TC15–TC0 DMA 1 Transfer Count Register (D1TC) Page 9-6 Reserved DDA19–DDA16 DMA 1 Destination Address High Register (D1DSTH) Page 9-7 DDA15–DDA0 DMA 1 Destination Address Low Register (D1DSTL) Page 9-8 Reserved DSA19–DSA16 DMA 1 Source Address High Register (D1SRCH) Page 9-9 DSA15–DSA0 DMA 1 Source Address Low Register (D1SRCL)
  • Page 173 Figure A-1 Internal Register Summary (continued) TC15–TC0 DMA 0 Transfer Count Register (D0TC) Page 9-6 Reserved DDA19–DDA16 DMA 0 Destination Address High Register (D0DSTH) Page 9-7 DDA15–DDA0 DMA 0 Destination Address Low Register (D0DSTL) Page 9-8 Reserved DSA19–DSA16 DMA 0 Source Address High Register (D0SRCH) Page 9-9 DSA15–DSA0 DMA 0 Source Address Low Register (D0SRCL)
  • Page 174 Figure A-1 Internal Register Summary (continued) BA19–BA13 R1–R0 Midrange Memory Chip Select Register (MMCS) Page 5-8 BA19–BA11 R1–R0 Peripheral Chip Select Register (PACS) Page 5-12 UB2–UB0 R1–R0 Low Memory Chip Select Register (LMCS) Page 5-6 LB2–LB0 R1–R0 Upper Memory Chip Select Register (UMCS) Page 5-4 BAUDDIV Serial Port 0 Baud Rate Divisor Register (SP0BAUD)
  • Page 175 Figure A-1 Internal Register Summary (continued) TDATA Reserved Serial Port 0 Transmit Register (SP0TD) Page 10-11 Reserved BRK1 BRK0 THRE OER PER TEMT HS0 RES Serial Port 0 Status Register (SP0STS) Page 10-9 RSIE TXIE RXIE MODE TMODE RMODE Serial Port 0 Control Register (SP0CT) Page 10-5 PDATA31–PDATA16 PIO Data 1 Register (PDATA1)
  • Page 176 Figure A-1 Internal Register Summary (continued) PDATA15–PDATA0 PIO Data 0 Register (PDATA0) Page 11-5 PDIR15–PDIR0 PIO Direction 0 Register (PDIR0) Page 11-4 PMODE15–PMODE0 PIO Mode 0 Register (PIOMODE0) Page 11-3 CONT Timer 2 Mode/Control Register (T2CON) Page 8-5 TC15–TC0 Timer 2 Maxcount Compare A Register (T2CMPA) Page 8-7 TC15–TC0 Timer 2 Count Register (T2CNT)
  • Page 177 Figure A-1 Internal Register Summary (continued) Timer 1 Mode/Control Register (T1CON) CONT Page 8-3 TC15–TC0 Timer 1 Maxcount Compare B Register (T1CMPB) Page 8-7 TC15–TC0 Timer 1 Maxcount Compare A Register (T1CMPA) Page 8-7 TC15–TC0 Timer 1 Count Register (T1CNT) Page 8-6 Timer 0 Mode/Control Register (T0CON) CONT...
  • Page 178 Figure A-1 Internal Register Summary (continued) TC15–TC0 Timer 0 Maxcount Compare A Register (T0CMPA) Page 8-7 TC15–TC0 Timer 0 Count Register (T0CNT) Page 8-6 Reserved PR1 PR0 Serial Port 0 Interrupt Control Register (SP0CON) Master Mode Page 7-18 Reserved PR1 PR0 Serial Port 1 Interrupt Control Register (SP1CON) Master Mode Page 7-18...
  • Page 179 Figure A-1 Internal Register Summary (continued) Reserved PR2–PR0 INT2 Control Register (I2CON) Master Mode Page 7-15 Reserved PR2–PR0 SFNM INT1 Control Register (I1CON) Master Mode Page 7-14 Reserved PR2–PR0 Timer 2 Interrupt Control Register (T2INTCON) Slave Mode Page 7-29 Reserved PR2–PR0 SFNM INT0 Control Register (I0CON)
  • Page 180 Figure A-1 Internal Register Summary (continued) Reserved PR2–PR0 DMA 0 Interrupt Control Register (DMA0CON)/INT5CON Master Mode—Page 7-17 Slave Mode—Page 7-29 Reserved PR2–PR0 Timer Interrupt Control Register (TCUCON) Master Mode—Page 7-17 Timer 0 Interrupt Control Register (T0INTCON) Slave Mode—Page 7-29 TMR2–TMR0 Reserved DHLT Interrupt Status Register (INTSTS)
  • Page 181 Figure A-1 Internal Register Summary (continued) D1/I6 D1/I6 Reserved D0/I5 Res TMR Interrupt In-Service Register (INSERV) Master Mode Page 7-22 Reserved TMR2 TMR1 TMR0 In-Service Register (INSERV) Slave Mode Page 7-32 Reserved PRM2–PRM0 Priority Mask Register (PRIMSK) Master Mode—Page 7-23 Slave Mode—Page 7-33 D1/I6 D0/I5...
  • Page 182 Figure A-1 Internal Register Summary (continued) Reserved S4–S0 IREQ Poll Status Register (POLLST) Master Mode Page 7-25 Reserved S4–S0 IREQ Poll Register (POLL) Master Mode Page 7-26 Reserved S4–S0 NSPEC End-of-Interrupt Register (EOI) Master Mode Page 7-27 Reserved L2–L0 Specific End-of-Interrupt Register (EOI) Slave Mode Page 7-35 Reserved...
  • Page 183 Figure A-1 Internal Register Summary (continued) BAUDDIV Serial Port 1 Baud Rate Divisor Register (SP1BAUD) Page 10-14 RDATA Reserved Serial Port 1 Receive Register (SP1RD) Page 10-12 TDATA Reserved Serial Port 1 Transmit Register (SP1TD) Page 10-11 Reserved BRK1 BRK0 THRE OER PER TEMT...
  • Page 184 A-18 Register Summary...
  • Page 185 INDEX E (Enable RCU) 6-2 EN (Enable Bit) 8-3, 8-5 ALT bit (Alternate Compare Bit) EX (Pin Selector) 5-11 Timer 0 Mode/Control Register 8-4 EXT (External Clock Bit) 8-3 Timer 1 Mode/Control Register 8-4 F2-F0 (Clock Divisor Select) 4-8 Am186ES microcontroller FER (Framing Error Detected) 10-10 design philosophy xiii HS0 (Handshake Signal 0) 10-10...
  • Page 186 R19-R8 (Relocation Address Bits) 4-3 7-22 R1-R0 (Wait State Value) 5-5, 5-7, 5-9, 5-11 WD (Virtual Watchdog Timer Interrupt Mask) 7-24 R2 (Ready Mode) 5-5, 5-7, 5-9, 5-11 WD (Virtual Watchdog Timer Interrupt Request) 7- R7 (Address Disable) 5-5, 5-7 BRK1 bit (Long Break Detected) 10-9 RB8 (Received Bit 8) 10-9 RC (Reset Configuration) 4-4...
  • Page 187 IF (interrupt enable flag) 7-2 description 9-6 INH bit (Inhibit Bit) documentation Timer 0 Mode/Control Register 8-3 AMD E86 Family publications xiv Timer 1 Mode/Control Register 8-3 ordering documentation and literature v Timer 2 Mode/Control Register 8-5 DSA15-DSA0 field (DMA Source Address Low) 9-10...
  • Page 188 Interrupt control unit 7-1 IREQ bit (Interrupt Request) Interrupt controller registers Poll Register 7-26 master mode 7-13 Poll Status Register 7-25 slave mode 7-28 IRET interrupt return 7-5 Interrupt controller reset conditions 7-9 Interrupt enable flag (IF) 7-2 Interrupt mask bit 7-2 L2-L0 field (Interrupt Type) 7-35 Interrupt Mask Register LB2-LB0 field (Lower Boundary) 5-4...
  • Page 189 Timer Interrupt Control Registers 7-29 description Master mode 7-25 Polled interrupts 7-12 PR2-PR0 field (Priority Level) Nonmaskable interrupts 7-2, 7-7 DMA Interrupt Control Register 7-29 NSPEC bit (NonSpecific EOI) 7-27 Timer Interrupt Control Register 7-29 PR2-PR0 field (Priority) DMA Interrupt Control Registers 7-17 INT0 Control Register 7-14 OER bit (Overrun Error Detected) 10-10 INT1 Control Register 7-14...
  • Page 190 RDR bit (Receive Data Ready) 10-9 PCS and MCS Auxiliary (MPCS, Offset A8h) 5-10 registers Peripheral Chip Select (PACS, Offset A4h) 5-12 Clock Prescaler (CDRAM, Offset E2h) 6-2 Peripheral Control Block Relocation (RELREG, Offset FEh) 4-3 DMA 0 Control (D0CON, Offset CAh) 9-3 PIO Data 0 (PDATA0, Offset 74h) 11-5 DMA 0 Destination Address High (D0DSTH, Offset C6h) 9-7...
  • Page 191 Timer 2 Maxcount Compare A (T2CMPA, Special fully nested mode 7-12 Offset 62h) 8-7 Specific End-of-Interrupt Register Timer 2 Mode and Control (T2CON, Offset 66h) 8-5 description Timer Interrupt Control (TCUCON, Offset 32h) 7-17 Slave mode 7-35 Upper Memory Chip Select (UMCS, Offset A0h) 5-4 SPI bit (Serial Port Interrupt In-Service) 7-22 Reset SPI bit (Serial Port Interrupt Mask) 7-24...
  • Page 192 Timer 1 Maxcount Compare B Register description 8-7 Timer 1 Mode and Control Register description 8-3 Timer 2 Count Register description 8-6 Timer 2 Interrupt Control Register description Slave mode 7-29 Timer 2 Maxcount Compare B Register description 8-7 Timer 2 Mode and Control Register description 8-5 TImer Interrupt Control Register description...

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