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AMD Am186 CC User Manual

AMD Am186 CC User Manual

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Am186
CC/CH/CU Microcontrollers
User's Manual
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Summary of Contents for AMD Am186 CC

  • Page 1 ™ Am186 CC/CH/CU Microcontrollers User’s Manual Order #21914B...
  • Page 2 The information in this publication is believed to be accurate at the time of publication, but AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes at any time, without notice.
  • Page 3 Technical Support Answers to technical questions are available online, through e-mail, and by telephone. Go to AMD’s home page at www.amd.com and follow the Service link for the latest AMD technical support phone numbers, software, and Frequently Asked Questions. For technical support questions on all E86 and Comm86 products, send e-mail to epd.support@amd.com (in the US and Canada) or euro.tech@amd.com (in Europe and...
  • Page 4 Am186™CC/CH/CU Microcontrollers User’s Manual...

  • Page 5: Table Of Contents

    AMD Documentation ........
  • Page 6 Table of Contents Data Types..........2-8 Addressing Modes .
  • Page 7 Table of Contents 4.3.2.23 WHB and WR....... 4-5 4.3.2.24 WLB ........4-5 4.3.2.25 WR .
  • Page 8 Table of Contents Operation ..........7-6 7.5.1 Usage .
  • Page 9 Table of Contents 8.5.6.5 General-Purpose DMA Terminal Count ..8-14 8.5.6.6 General-Purpose DMA Channel Operations ..8-14 8.5.7 SmartDMA Channels ....... . 8-26 8.5.7.1 SmartDMA Channels Introduction .
  • Page 10 Table of Contents 11.5 Operation ..........11-3 11.5.1 Usage .
  • Page 11 Table of Contents CHAPTER 14 SYNCHRONOUS SERIAL PORT (SSI) 14-1 14.1 Overview ..........14-1 14.2 Block Diagram .
  • Page 12 Table of Contents CHAPTER 17 GENERAL CIRCUIT INTERFACE (GCI) 17-1 17.1 Overview ..........17-1 17.2 Block Diagram .
  • Page 13 Table of Contents 18.5.6 Using USB with DMA ....... 18-19 18.5.6.1 DMA Availability .
  • Page 14 Table of Contents LIST OF FIGURES Figure 1-1 Am186CC Communications Controller Block Diagram ..... . 1-5 Figure 1-2 Am186CH HDLC Microcontroller Block Diagram ......1-5 Figure 1-3 Am186CU USB Microcontroller Block Diagram .
  • Page 15 Table of Contents Figure 15-2 HDLC, TSA, and GCI Block Diagram ........15-3 Figure 15-3 HDLC Transmitter Block Diagram .
  • Page 16 Table of Contents LIST OF TABLES Table 0-1 Documentation Conventions......... . . xxii Table 1-1 Feature Comparison .
  • Page 17 Table of Contents Table 13-5 UARTs Interrupt Sources ......... . . 13-19 Table 14-1 SSI Multiplexed Signals .
  • Page 18 Table of Contents xviii Am186™CC/CH/CU Microcontrollers User’s Manual...

  • Page 19: Preface

    All of these microcontrollers offer the advantages of the x86 development environment’s widely available native development tools, applications, and system software. Additionally, the microcontrollers use the industry-standard 186 instruction set that is part of the AMD E86™ family, which continually offers instruction-set-compatible upgrades. Built into each of the microcontrollers is a wide range of communications features required in many communications applications.
  • Page 20 Introduction Chapter 7, “Interrupts,” describes the microcontrollers’ support for interrupts, both maskable and nonmaskable. It discusses interrupt sequence and priority as well as how to configure the maskable interrupt sources through the interrupt channels. It also describes the nonmaskable interrupts. Chapter 8, “DMA Controller,”...

  • Page 21: Related Documents

    In addition, many documents are available in PDF form on the AMD web site. To access the AMD home page, go to www.amd.com. Then follow the Embedded Processors link for information about E86 and Comm86 products.

  • Page 22: Additional Information

    Introduction Additional Information The following non-AMD documents and sources provide additional information that may be of interest to Am186CC and Am186CU microcontroller users: Universal Serial Bus Specification, Revision 1.0 , available from the USB web site at http://www.usb.org. Universal Serial Bus System Architecture , by Don Anderson, Mindshare, Inc., Addison Wesley Developers Press, 1997.

  • Page 23: Microcontroller-Specific Information

    Introduction Table 0-1 Documentation Conventions (Continued) Notation Meaning Microcontroller-Specific Information Icons 186CC Communications Controller Information specific to the Am 186CH HDLC Microcontroller Information specific to the Am 186CU USB Microcontroller Information specific to the Am MICROCONTROLLER-SPECIFIC INFORMATION This manual provides information that applies to all three of the Am186CC/CH/CU microcontrollers as well as information that is specific to each controller.
  • Page 24 Introduction xxiv Am186™CC/CH/CU Microcontrollers User’s Manual...

  • Page 25: Chapter 1 Architectural Overview

    These microcontrollers offer the advantages of the x86 development environment’s widely available native development tools, applications, and system software. Additionally, these microcontrollers use the industry-standard 186 instruction set that is part of the AMD E86 family, which continually offers instruction-set-compatible upgrades. Use of this instruction set ensures both backward and upward software compatibility.

  • Page 26: Am186Ch Hdlc Microcontroller

    Architectural Overview System peripherals – Interrupt controller (36 maskable interrupts) – Four general-purpose DMA channels – 48 programmable I/O signals – Three programmable 16-bit timers – Hardware watchdog timer Memory and Peripheral Interface – Integrated DRAM controller – Glueless interface to RAM/ROM/Flash memory (40-ns Flash memory required for zero-wait-state operation at 50 MHz) –...

  • Page 27: Am186Cu Usb Microcontroller

    Architectural Overview Memory and Peripheral Interface – Integrated DRAM controller – Glueless interface to RAM/ROM/Flash memory (40-ns Flash memory required for zero-wait-state operation at 50 MHz) – Fourteen chip selects (6 memory, 8 peripheral) – External bus mastering support – Multiplexed and nonmultiplexed address/data bus –...

  • Page 28: Feature Comparison

    Architectural Overview 1.2.3 Feature Comparison Table 1-1 summarizes and compares the features of each of the microcontrollers. Table 1-1 Feature Comparison Feature HDLC Channels – Time Slot Assigners (TSAs) – Raw DCE Interface – PCM Highway Interface – GCI (IOM-2) Interface –...

  • Page 29: Figure 1-1 Am186Cc Communications Controller Block Diagram

    Architectural Overview Figure 1-1 Am186CC Communications Controller Block Diagram Serial Communications Peripherals Interrupt Chip High-Speed Synchronous Am186 PIOs Watchdog Controller Selects UART UART with Serial (48) (17 Ext. Timer (14) Interface (SSI) Autobaud Sources) Physical Interface Glueless General- Smart DRAM Timers HDLC Raw DCE...

  • Page 30: Am186 Embedded Cpu

    Architectural Overview ARCHITECTURAL OVERVIEW The architectural goal of the Am186CC/CH/CU microcontrollers is to provide comprehensive communications features on a processor running the widely-known x86 instruction set. These microcontrollers combine communications peripherals with the Am186 embedded CPU, resulting in highly integrated microcontrollers that provide system- cost and performance advantages for a wide range of communications applications.

  • Page 31: Hdlc Channels And Tsas

    Architectural Overview In addition, the USB peripheral controller supports the following: An unlimited number of device descriptors. A total of six endpoints: one control endpoint; one interrupt endpoint; and four data endpoints that can be configured as control, interrupt, bulk, or isochronous. The interrupt, bulk, and isochronous endpoints can be configured for the IN or OUT direction.

  • Page 32: General Circuit Interface

    GCI. The GCI interface provides a glueless connection between the Am186CC microcontroller and GCI/IOM-2 based ISDN transceiver devices, such as the AMD Am79C30 or Am79C32. The GCI interface provides a 4-pin connection to the transceiver device. The Am186CC...

  • Page 33: Asynchronous Serial Ports

    The SSI port also offers a programmable clock divisor (dividing the clock from 2 to 256 in power of 2 increments), a bidirectional transmit/receive shift register, and direct connection to AMD Subscriber Line Audio-processing Circuit (SLAC™) devices.

  • Page 34: General-Purpose Dma Channels

    Architectural Overview The Am186CH HDLC microcontroller has 14 internal maskable interrupt sources. The Am186CU USB microcontroller has 13 internal maskable interrupt sources. In addition to interrupts managed by the interrupt controller, each microcontroller supports eight nonmaskable interrupts—an external or internal nonmaskable interrupt (NMI), a trace interrupt, and software interrupts and exceptions.

  • Page 35: Hardware Watchdog Timer

    Architectural Overview input pins. When driven from a timer input pin, the timer is counting the “event” of an input transition. The microcontroller also provides a pulse width demodulation (PWD) option so that a toggling input signal’s Low state and High state durations can be measured. 1.4.3.5 Hardware Watchdog Timer (Chapter 11) Each of the Am186CC/CH/CU microcontrollers provides a full-featured watchdog timer,...

  • Page 36: Chip Selects

    Architectural Overview capability allows designs requiring larger amounts of memory to save system cost over SRAM designs by taking advantage of low DRAM costs. The DRAM interface uses various chip select pins to implement the RAS/CAS interface required by DRAMs. The microcontroller’s DRAM controller drives the RAS/CAS interface appropriately during both normal memory accesses and refresh.
  • Page 37 Architectural Overview APPLICATIONS The Am186CC/CH/CU microcontrollers, with their integrated communications features, provide highly integrated, cost-effective solutions for a wide range of telecommunications and networking applications. ISDN Modems and Terminal Adapters: Next-generation ISDN equipment requires USB (or High-speed UART capability), in addition to three channels of HDLC. Low-End Routers: ISDN to Ethernet-based personal routers, often used for connections in Small Office/Home Office (SOHO) environments, require three channels of HDLC, as well as the high performance of a 16-bit controller.

  • Page 38: Figure 1-4 Isdn Terminal Adapter

    Architectural Overview Figure 1-4 ISDN Terminal Adapter Figure 1-5 ISDN-to-Ethernet Low-End Router 1-14 Am186™CC/CH/CU Microcontrollers User’s Manual...

  • Page 39: Figure 1-6 32-Channel Linecard

    Architectural Overview Figure 1-6 32-Channel Linecard Am186™CC/CH/CU Microcontrollers User’s Manual 1-15...
  • Page 40 Architectural Overview 1-16 Am186™CC/CH/CU Microcontrollers User’s Manual...

  • Page 41: Processor Registers

    CHAPTER CONFIGURATION BASICS OVERVIEW All members of the Am186 family, including the Am186CC/CH/CU microcontrollers, build on the same core set of internal processor registers, instructions, and addressing modes. All members are compatible with the original industry-standard 186 parts. This chapter provides basic information about configuring the microcontrollers, including discussions of the registers, memory organization, address generation, I/O space, peripheral control block, instruction set, segments, data types, and addressing modes.

  • Page 42: Processor Status Flags Register

    Configuration Basics These registers are grouped into the following categories: General-Purpose registers: Eight 16-bit general-purpose registers support arithmetic and logical operands. Four of these (AX, BX, CX, and DX) also operate as pairs of separate 8-bit registers (AH, AL, BH, BL, CH, CL, DH, and DL). The Destination Index (DI) and Source Index (SI) general-purpose registers support data movement and string instructions.

  • Page 43: Figure 2-2 Processor Status Flags Register

    Configuration Basics After the processor executes an instruction, the value of the flags can be set to 1, cleared or reset to 0, unchanged, or undefined. The term undefined means that the flag value prior to the execution of the instruction is not preserved, and that after the instruction is executed, the value of the flag cannot be predicted.

  • Page 44: Peripheral Registers

    Configuration Basics 2.2.3 Peripheral Registers While the 186-legacy registers can be accessed directly through the 186 instructions, the peripheral registers must be accessed by using instruction operands that access memory or I/O space. The address of each 16-bit read/write peripheral register is in the internal 1-Kbyte peripheral control block (PCB).

  • Page 45: Table 2-3 Peripheral Register Summary

    Configuration Basics Table 2-3 Peripheral Register Summary Offset Range Functional Block User’s Manual Chapter High-level Data Link Control (HDLC) Chapter 15 CC CH 000h–0F0h 100h–13Ch General-Purpose DMA Chapter 8 140h–198h SmartDMA Universal Serial Bus (USB) Chapter 18 1E0h–25Eh CC CU High-Speed Asynchronous Serial Port 260h–27Ch (High-Speed UART)

  • Page 46: Figure 2-3 Physical Address Generation

    Configuration Basics For example, if the segment register is loaded with 12A4h and the offset is 0022h, the resultant address is 12A62h, as illustrated in Figure 2-3. To find the result: 1. The segment register contains 12A4h. 2. Shift the segment register left 4 places to produce 12A40h. 3.
  • Page 47 Configuration Basics Figure 2-4 Memory and I/O Space FFFFFh Memory 1 Mbyte Space FFFFh 64 Kbyte Space 0000h 00000h Notes: 1. 00000h–003FFh are reserved for the interrupt vector table. 2. 00F8h–00FFh are reserved. INSTRUCTION SET The instruction set for the Am186CC/CH/CU microcontrollers is identical to the 80C186/188 instruction set.

  • Page 48: Data Types

    Configuration Basics Table 2-4 Segment Register Selection Rules Memory Reference Segment Register Needed Used Implicit Segment Selection Rule Local Data Data (DS) All data references Instructions Code (CS) Instructions (including immediate data) Stack Stack (SS) All stack pushes and pops Any memory references that use the BP register External Data (Global) Extra (ES)

  • Page 49: Addressing Modes

    Configuration Basics Figure 2-5 Supported Data Types Signed Binary Byte . . . Coded Sign Bit Magnitude Decimal Digit N Digit 1 Digit 0 (BCD) Unsigned Byte . . . Magnitude ASCII ASCII ASCII ASCII Signed Character Character Character 15 14 Word Sign Bit Packed...

  • Page 50: Table 2-5 Memory Addressing Mode Examples

    Configuration Basics Combinations of the above three address elements define the following six memory addressing modes (see Table 2-5 for examples). Direct Mode: The instruction contains the operand offset as an 8-bit or 16-bit displacement element. Register Indirect Mode: The operand offset is in one of the following registers: SI, DI, BX, or BP.

  • Page 51: System Overview

    CHAPTER SYSTEM OVERVIEW OVERVIEW This chapter contains descriptions of the Am186CC/CH/CU microcontrollers’ system configuration registers, initialization and processor reset, signals, bus interface, and clock control. SYSTEM DESIGN Table 3-1 shows the multiplexed signals and the trade-offs when selecting various functions. Table 3-2 on page 3-3 shows the multiplexed signal information ordered by PIO signal.
  • Page 52 System Overview Table 3-1 Multiplexed Signal Trade-Offs (Continued) Desired Function Unavailable Functions Inter- Inter- Inter- Inter- Inter- Signal Signal Signal Signal Signal face face face face face DCE_RXD_D PCM_RXD_D RXD_U PIO26 High- DCE_TXD_D PCM_TXD_D TXD_U PIO20 Low- Speed Channel Channel DCE_RCLK_D PCM_CLK_D RTR_U...

  • Page 53: Table 3-2 Multiplexed Signal Trade-Offs Ordered By Pio

    System Overview Table 3-1 Multiplexed Signal Trade-Offs (Continued) Desired Function Unavailable Functions Inter- Inter- Inter- Inter- Inter- Signal Signal Signal Signal Signal face face face face face Miscellaneous — — — — PIO30 Interfac Interfac — — — — PIO30 USBSOF USBSCI UCLK...

  • Page 54: System Configuration

    System Overview Table 3-2 Multiplexed Signal Trade-Offs Ordered by PIO (Continued) Desired Function Unavailable Functions Signal Signal Signal Signal PIO30 — PIO31 PCS7 — — PIO32 PCS6 — — PIO33 — — PIO34 — — PIO35 SRDY — — PIO36 —...

  • Page 55: Initialization And Reset

    System Overview The System Configuration (SYSCON) register is typically written once to establish the proper modes of operation based on the system in which the part is operating. This register performs the following functions: Enables the data strobe timings on the DEN pin. When the DSDEN bit (bit 13) is set to 1, data strobe bus mode is enabled, and the DS timing for reads and writes is identical to the normal read cycle DEN timing.

  • Page 56: Table 3-4 Cpu And Internal Peripheral States Immediately Following Power-On Reset

    System Overview During an external reset, RESOUT remains active (High) for two clocks after RES is deasserted. The microcontroller exits reset and begins the first valid bus cycle approximately 4.5 clocks after RES is deasserted. With an internal reset, the watchdog timer reset duration, and therefore the duration of the RESOUT signal, is 2 processor clocks.

  • Page 57: Table 3-5 Reset Configuration Pins (Pinstraps)

    System Overview Table 3-5 Reset Configuration Pins (Pinstraps) Multiplexed Signal Name Description Signal(s) Address Enable: If {ADEN} is held High or left floating during power-on reset, the address portion of the AD bus (AD15–AD0) is enabled or disabled during LCS, UCS, or other memory bus cycles based on how the software configures the DA bit in the UMCS or LMCS registers.

  • Page 58: Signal Descriptions

    System Overview SIGNAL DESCRIPTIONS Table 3-7 contains a description of the Am186CC/CH/CU microcontroller signals. Table 3-6 describes the terms used in Table 3-7. The signals are organized alphabetically within the following functional groups: Bus interface/general-purpose DMA request (page 3-10) Clocks/reset/watchdog timer (page 3-14) Reserved (page 3-16) Power and ground (page 3-16) Debug support (page 3-17)

  • Page 59: Table 3-6 Signal Descriptions Table Definitions

    System Overview Table 3-6 Signal Descriptions Table Definitions Term Definition General Terms Indicates the pin alternate function; a pin defaults to the signal named without the brackets. Indicates the reset configuration pin (pinstrap). Refers to the physical wire. An external or power-on reset is caused by asserting RES. An internal reset is initiated by the watchdog timer.

  • Page 60: Table 3-7 Signal Descriptions

    System Overview Table 3-7 Signal Descriptions Multiplexed Signal Name Type Description Signal(s) BUS INTERFACE/GENERAL-PURPOSE DMA REQUEST Address Bus supplies nonmultiplexed memory or I/O addresses to the system one half of a CLKOUT period earlier than the multiplexed address and data bus (AD15–AD0). During bus-hold or reset conditions, the address bus is three-stated with pulldowns.
  • Page 61 System Overview Table 3-7 Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) Bus High Enable: During a memory access, BHE and the least- significant address bit (AD0) indicate to the system which bytes of the data bus (upper, lower, or both) participate in a bus cycle. The BHE and AD0 pins are encoded as follows: Data Byte Encoding Type of Bus Cycle...
  • Page 62 System Overview Table 3-7 Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) Data Strobe provides a signal where the write cycle timing is identical to the read cycle timing. When used with other control signals, [DS] provides an interface for 68K-type peripherals without the need for additional system interface logic.
  • Page 63 System Overview Table 3-7 Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) Bus-Hold Request indicates to the microcontroller that an external bus master needs control of the local bus. The microcontroller HOLD latency time—the time between HOLD request and HOLD acknowledge—is a function of the activity occurring in the processor when the HOLD request is received.
  • Page 64 System Overview Table 3-7 Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) Synchronous Ready indicates to the microcontroller that the addressed memory space or I/O device will complete a data transfer. The SRDY pin accepts an active High input synchronized to CLKOUT.
  • Page 65 System Overview Table 3-7 Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) Reset requires the microcontroller to perform a reset. When RES is asserted, the microcontroller immediately terminates its present activity, clears its internal logic, and on the deassertion of RES, transfers CPU control to the reset address FFFF0h.
  • Page 66 System Overview Table 3-7 Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) Table 3-5 on page 3-7 PINSTRAPS (See RESERVED — RSVD_75 On the Am186CH HDLC microcontroller, the RSVD_75 pin — RSVD_76 should be tied externally to V — RSVD_80 On the Am186CH HDLC microcontroller, pins RSVD_75, —...
  • Page 67 System Overview Table 3-7 Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) DEBUG SUPPORT Queue Status 1–0 values provide information to the system concerning the interaction of the CPU and the instruction queue. The pins have the following meanings: Queue Status Pins QS1 QS0 Queue Operation None...
  • Page 68 System Overview Table 3-7 Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) [PIO13] PCS0 Peripheral Chip Selects 0–7 indicate to the system that an {USBSEL1} access is in progress to the corresponding region of the PCS1 [PIO14] peripheral address block (either I/O or memory address space). {USBSEL2} The base address of the peripheral address block is PCS2...
  • Page 69 System Overview Table 3-7 Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) DRAM Column Address Strobes 0–1: When either the upper or lower chip select regions are configured for DRAM, these pins provide [CAS0] MCS2 the column address strobe signals to the DRAM. The CAS signals can be used to perform byte writes in a manner similar [CAS1] MCS1...
  • Page 70 System Overview Table 3-7 Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) Nonmaskable Interrupt indicates to the microcontroller that an interrupt request has occurred. The NMI signal is the highest priority hardware interrupt and cannot be masked. The microcontroller always transfers program execution to the location specified by the nonmaskable interrupt vector in the microcontroller’s interrupt vector table when NMI is asserted.
  • Page 71 System Overview Table 3-7 Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) PROGRAMMABLE I/O (PIOS) Shared Programmable I/O pins can be programmed with the following attributes: PIO function (enabled/disabled), direction (input/output), and weak pullup or pulldown. After a reset, the PIO pins default to various configurations. Most of the PIO pins are configured as PIO inputs with pullup after reset.
  • Page 72 System Overview Table 3-7 Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) Timer Inputs 0–1 supply a clock or control signal to the internal microcontroller timers. After internally synchronizing a Low-to- High transition on [TMRIN1]–[TMRIN0], the microcontroller increments the timer. [TMRIN1]–[TMRIN0] must be tied High if [TMRIN0] PIO27 not being used.
  • Page 73 System Overview Table 3-7 Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) Clear-To-Send High-Speed UART provides the Clear-to-Send signal from the high-speed asynchronous serial port when hardware flow control is enabled for the port. The [CTS_HU] signal gates the transmission of data from the serial port transmit [DCE_CTS_D] shift register.
  • Page 74 System Overview Table 3-7 Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) DCE Clear-To-Send Channel A indicates to the channel A DCE [DCE_CTS_A] [PCM_TSC_A] interface that an external serial interface is ready to receive data. [DCE_CTS_A] and [DCE_RTR_A] provide the handshaking for PIO17 CC CH the channel A DCE interface.
  • Page 75 System Overview Table 3-7 Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) DCE Ready-to-Receive Channel C indicates to an external serial interface that the internal channel C DCE is ready to accept PIO45 [DCE_RTR_C] data. [DCE_CTS_C] and [DCE_RTR_C] provide the handshaking for the channel C DCE interface.
  • Page 76 System Overview Table 3-7 Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) CC CH HDLC Channel B (PCM) [PCM_RXD_B] [DCE_RXD_B] PCM Receive Data Channel B is the serial data input pin for the channel B PCM Highway interface. PIO36 CC CH [PCM_TXD_B] [DCE_TXD_B]...
  • Page 77 System Overview Table 3-7 Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) [CTS_U] (UART) PCM Frame Synchronization Clock provides the Frame [DCE_TCLK_D] Synchronization Clock input (usually 8 kHz) for the channel D [PCM_FSC_D] PCM Highway interface. PIO24 [CTS_HU] (High- PCM Time Slot Control D enables an external buffer device Speed UART) when channel D PCM Highway data is present on the...

  • Page 78: Bus Interface

    System Overview Table 3-7 Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) USB External Transceiver Differential Plus is an output that RSVD_101 UTXDPLS CC CU drives the external transceiver differential driver plus input. USB External Transceiver Transmit Output Enable is an output that enables the external transceiver.

  • Page 79: Block Diagrams

    System Overview 3.6.2 Block Diagrams Figure 3-1 shows an Am186CC/CH/CU microcontroller system with DRAM; Figure 3-2, with SRAM. Figure 3-1 Typical Microcontroller Memory System With DRAM MA8–MA0 Flash Memory (x8 or x16) A19–A0 Address 4-Mbit DRAM Am186CC/CH/CU AD15–AD0 Data Microcontroller Data CAS0 CAS0...

  • Page 80: Operation

    System Overview 3.6.3 Operation 3.6.3.1 Address and Data Buses The 80C186 and 80C188 microcontrollers use a multiplexed address and data (AD) bus. The address is present on the AD bus only during the t clock phase. The Am186CC/CH/CU microcontrollers provide the multiplexed AD bus and, in addition, provide a nonmultiplexed address (A) bus.

  • Page 81: Byte Write Enables

    System Overview The width of the data access should not be modified while the processor is fetching instructions from the associated address space or while the peripheral control block is overlaid on the affected address space. Table 3-8 Programming Am186CC/CH/CU Microcontrollers Bus Width Space Register Value...

  • Page 82: Dram Controller

    System Overview 3.6.3.6 DRAM Controller The microcontroller has a fully integrated DRAM controller that provides a glueliss interface to 25-ns–70-ns EDO DRAM. The microcontroller provides zero-wait state operation at up to 50 MHz with 40-ns DRAM. The DRAM controller includes the following features: Multiplexed addresses for DRAM row and column accesses 8-bit and 16-bit boot mode for UCS accesses Two RAS signals that support two banks of DRAM...

  • Page 83: Figure 3-3 Am186Cc/Ch/Cu Microcontroller Clocks

    System Overview The Am186CC and Am186CH microcontrollers also include the transmitter/receiver clocks for each High-level Data Link Control (HDLC) channel. In the Am186CC microcontroller, each HDLC channel receives its clock inputs directly from the external communication clock pins (TCLK _X and RCLK_X) in all modes except in GCI mode.

  • Page 84: Pll Bypass Mode

    System Overview 3.7.2 PLL Bypass Mode The Am186CC/CH/CU microcontrollers provide a PLL Bypass mode that allows the X1 input frequency to be anything from 0 to 24 MHz. Select PLL Bypass by asserting CLKSEL1 and CLKSEL2. When the microcontroller is in PLL Bypass mode, the CLKOUT frequency equals the X1 input frequency.
  • Page 85 System Overview On the Am186CC microcontroller, both an external and an internal reset selects full HDLC with flow control for external interface D and sets HDLC Channel C for raw DCE or PCM Highway mode. On an external reset, the following also occurs: Pinstraps are sampled (see Table 3-5 on page 3-7).
  • Page 86 System Overview 3-36 Am186™CC/CH/CU Microcontrollers User’s Manual...

  • Page 87: Chapter 4 Emulator Support

    CHAPTER EMULATOR SUPPORT OVERVIEW This chapter describes the various features available in the Am186CC/CH/CU microcontrollers to facilitate the design and operation of an In-Circuit Emulator (ICE). Most of the discussion centers around the operation of pins. Because different debug tool manufacturers take different approaches to emulator implementation, restrictions imposed by the use of one type of emulator may not apply to another.

  • Page 88: Operation

    Emulator Support designer to clip an emulator pod over the target CPU, then use ONCE mode to disable the target CPU and provide a connection to each of the PQFP processor pins. Be aware of any horizontal and vertical areas required by the emulators’ physical attachment method, and plan the board layout accordingly.

  • Page 89: Ale

    Emulator Support 186 processors also use BHE with A0 to denote refresh cycles to 16-bit DRAM (both inactive). The Am186CC/CH/CU microcontrollers do not support 8-bit wide DRAM designs, so using this mechanism to determine refresh cycles is reliable under all allowed DRAM designs.

  • Page 90: Mcs3-Mcs0

    Emulator Support 4.3.2.11 MCS3–MCS0 The system uses MCS1 and MCS2 as DRAM CAS strobes. MCS0 and MCS3 can be used as extra memory chip selects. Emulators can use these to determine when accesses occur to these memory spaces, and can intercept it for overlay memory purposes. 4.3.2.12 {ONCE} ONCE is not a dedicated pin but rather a pinstrap option that allows an external emulator...

  • Page 91: S2-S0

    Emulator Support 4.3.2.18 S2–S0 The S2–S0 bus indicates the type of memory cycle in progress. 4.3.2.19 The S6 signal is active from t –t on the microcontroller and signals a refresh or DMA access. 4.3.2.20 SRDY See “ARDY and SRDY” on page 4-3. 4.3.2.21 The system typically uses UCS as a FLASH or ROM chip select.
  • Page 92 Emulator Support Am186™CC/CH/CU Microcontrollers User’s Manual...

  • Page 93: Chapter 5 Chip Selects

    CHAPTER CHIP SELECTS OVERVIEW Signals that allow the CPU to select specific memory or peripheral devices are called chip selects . The microcontroller provides six chip select outputs for use with memory devices (UCS, LCS, and MCS3–MCS0) and eight chip selects for use with peripherals (PCS7–PCS0) in either memory or I/O space.

  • Page 94: Block Diagram

    Chip Selects BLOCK DIAGRAM Figure 5-1 shows the block diagram for the chip selects. Figure 5-1 Chip Selects and DRAM Block Diagram (CDRAM) PCB_AD Refresh Value Control to 186 Refresh Write Data Refresh Enable Control Read Data Current Value CS/DRAM (EDRAM) Registers DRAM Address...

  • Page 95: Registers

    Chip Selects Table 5-1 Chip Selects Multiplexed Signals Multiplexed Default Signal Function Signal(s) Signal RAS0 Lower memory chip select MCS0 PIO4 PIO4 MCS1 CAS1 MCS1 Midrange memory chip selects MCS2 CAS0 MCS2 RAS1 MCS3 PIO5 PIO5 PCS0 PIO13 PCS0 PCS1 PIO14 PCS1 PCS2...

  • Page 96: Operation

    Chip Selects OPERATION 5.5.1 Usage Note: Before using the chip selects, ensure multiplexed pins are configured to reflect the use of the chip selects and not other functionality (see Table 5-1 on page 5-3). Except for the UCS chip select, which is active on reset, chip selects are not activated until the associated register is written (not when it is read).

  • Page 97: Selecting Memory And I/O Space

    Chip Selects To use the Midrange Memory Chip Select (MCS), configure the following options in the MMCS and MPCS registers: – Base address (BA[19–13] bit field in MMCS) – MCS0-Only mode (MCS0_ONLY bit in MMCS) – External Ready mode (R2 bit in MMCS) –...

  • Page 98: Pcs7-Pcs0

    Chip Selects 5.5.2.4 PCS7–PCS0 The Am186CC/CH/CU microcontrollers each provide eight chip selects for eight contiguous, user-locatable, 256-byte address ranges within memory or I/O space. The base address can reside anywhere in the 1-Mbyte memory address space as long as it is a multiple of 2 Kbytes (0 is a valid multiple), and the memory space is not already mapped to by UCS, LCS, or MCS.

  • Page 99: Selecting Dram Using The Chip Selects

    Chip Selects Figure 5-3 Chip Selectable I/O Space FFFFh 8 Contiguous 256-Byte Base + 2047 bytes Address 64-Kbyte Regions I/O Space Base 0000h PCS7–PCS0 Selectable 5.5.3 Selecting DRAM Using the Chip Selects UCS and LCS can be configured for DRAM support with the UDEN bit in the UMCS register and the LDEN bit in the LMCS register, respectively.

  • Page 100: Overlapping Chip Selects

    Chip Selects PCS7–PCS0 can overlap any UCS or LCS space which has been configured for DRAM. (Overlap of the PCS signals with UCS or LCS in non-DRAM mode is not recommended.) Overlapping PCS with DRAM is fully supported as long as the PCS chip selects are programmed for a greater or equal number of wait states than that of the DRAM.

  • Page 101: Configuring Address And Data Buses

    Chip Selects 5.5.5 Configuring Address and Data Buses 5.5.5.1 UCS and LCS When UCS or LCS are asserted, the DA bit in the UMCS or LMCS register selects whether the AD15–AD0 bus is driven during the address phase of a bus cycle. The DA bit is still valid when UCS or LCS supports DRAM (either UDEN or LDEN is 1).

  • Page 102: Programming Ready Signals And Wait States

    Chip Selects 5.5.6 Programming Ready Signals and Wait States The Am186CC/CH/CU microcontrollers can sense a ready signal for each of the peripheral or memory chip select lines. The ready signal can be either the ARDY or SRDY signal. Each chip select control register (UMCS, LMCS, PACS, MMCS, and MPCS) contains a single-bit field, R2, that determines whether the external ready signal is required or ignored.

  • Page 103: Comparison To Other Devices

    Chip Selects 5.5.10 Comparison to Other Devices General enhancements over the original 80C186 include bus mastering (three-state) support for all chip selects, and activation only when the associated register is written, not when it is read. In addition, each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in the 80C186.
  • Page 104 Chip Selects The value of the MMCS register is set to 7FDBh and the MPCS register is set to 8183h, which defaults MCS3–MCS0 each to 2 Kbytes with a total MCS block size of 8 Kbytes at a base address of 3Fh, with external ready, and three wait states. However, the MCS chip selects are not enabled until software writes to both the MMCS and MPCS registers.

  • Page 105: Chapter 6 Dram Controller

    CHAPTER DRAM CONTROLLER OVERVIEW Dynamic Random Access Memory (DRAM) offers memory at moderate speed and low cost. DRAM memory cells consist of one transistor and one capacitor. DRAM also uses a multiplexed address bus in a row/column format, which results in a lower pin count and smaller device package.

  • Page 106: Block Diagram

    DRAM Controller BLOCK DIAGRAM Figure 6-1 shows the block diagram for the DRAM controller. Figure 6-1 Chip Selects and DRAM Block Diagram (Same as Figure 5-1) (CDRAM) PCB_AD Refresh Value Control to 186 Refresh Write Data Refresh Enable Control Read Data Current Value CS/DRAM (EDRAM)

  • Page 107: Registers

    DRAM Controller REGISTERS Table 6-2 lists the 16-bit peripheral registers that determine the operation of the DRAM controller. You must also program the LDEN bit of the LMCS register and the UDEN bit of the UMCS register for DRAM operation. Appendix A summarizes the bits in all the registers. For a complete description of all the peripheral registers, see the Am186™CC/CH/CU Microcontrollers Register Set Manual , order #21916.

  • Page 108: Dram Interface

    DRAM Controller Table 6-3 DRAM Supported by the Am186CC/CH/CU Microcontrollers CPU Clock Refresh DRAM Speed Wait States Speed Cycles 50 ns 7 clocks 25 MHz 60 ns 7 clocks 70 ns 7 clocks 50 ns 7 clocks 40 MHz 60 ns 7 clocks 70 ns 7 clocks...

  • Page 109: Option To Overlap Dram With Pcs

    DRAM Controller The user can re-enable UCS by clearing the UDEN bit in the UMCS register. Doing so disables refreshing the upper bank of DRAM. If the data in the upper bank of DRAM does not have to be retained, no special action is required. If the data in the upper bank of DRAM must be retained, two options are available.

  • Page 110: Dram Refresh Intervals

    DRAM Controller 6.5.5.2 DRAM Refresh Intervals During a refresh cycle, the AD bus drives the address to FFFFh, which prevents the PCS and MCS signals from asserting inadvertently. PCS and MCS decode should never contain the address FFFFFh. The UCS signal does not assert during a refresh cycle. If two banks of DRAM are being used in a system (i.e., RAS0 and RAS1), then both banks are refreshed at the same time.

  • Page 111: Comparison To Other Devices

    DRAM Controller 6.5.8 Comparison to Other Devices The DRAM controller is similar to the Am186ED DRAM controller, with these primary enhancements: 50 MHz, extended refresh interval times, and faster DRAMs. The Am186CC/CH/CU microcontrollers support 25-ns to 70-ns EDO DRAM only. It does not support Fast Page mode DRAM.
  • Page 112 DRAM Controller Am186™CC/CH/CU Microcontrollers User’s Manual...

  • Page 113: Chapter 7 Interrupts

    CHAPTER INTERRUPTS OVERVIEW An interrupt is a request to the CPU for service. CPUs receive interrupt requests from a variety of sources, both internal and external. When the CPU receives a request, it stops executing the current task, and if the new task is of higher priority, begins executing that routine.

  • Page 114: Block Diagram

    Interrupts The following Am186CH HDLC microcontroller peripherals can generate internal interrupts: Three on-board timers (two of the timers can operate as pulse width modulators) Two UARTs Two HDLC channels Two pairs of transmit/receive SmartDMA channels Four general-purpose DMA channels The following Am186CU USB microcontroller peripherals can generate internal interrupts: Three on-board timers (two of the timers can operate as pulse width modulators) Two UARTs Two pairs of transmit/receive SmartDMA channels...

  • Page 115: System Design

    Interrupts Figure 7-1 Interrupts Block Diagram External NMI Internal NMI Watchdog Timer Interrupt Sources Timers (3) INT8/PWD (1) Execution Unit Interrupt Controller INT7–INT0 (8) INT request Execution Unit/ PIO5, 15, 27, 29, 30, 33, 34, 35 (8) Bus Grant Bus Interface General-Purpose DMAs (4) Control Bus Request...

  • Page 116: Table 7-1 Interrupt Multiplexed Signals

    Interrupts Table 7-1 Interrupt Multiplexed Signals Multiplexed Default Signal Function Signal(s) Signal INT0 — INT0 INT1 — INT1 INT2 — INT2 INT3 — INT3 INT4 — INT4 INT5 — INT5 INT6 PIO19 PIO19 INT7 , PIO7 PIO7 INT8 , PIO6 PIO6 Maskable interrupt requests RAS1, MCS3...

  • Page 117: Registers

    Interrupts Table 7-2 Interrupt Controller Register Summary Register Offset Register Name Description Mnemonic 300h CH0CON Interrupt Channel 0 Control 302h CH1CON Interrupt Channel 1 Control 304h CH2CON Interrupt Channel 2 Control 306h CH3CON Interrupt Channel 3 Control 308h CH4CON Interrupt Channel 4 Control 30Ah CH5CON Interrupt Channel 5 Control...

  • Page 118: Operation

    Interrupts Table 7-2 Interrupt Controller Register Summary (Continued) Register Offset Register Name Description Mnemonic Indicates if an INT signal that is enabled for 332h SHREQ Interrupt Shared Request shared interrupts is currently requesting an interrupt on the shared channel, Channel 14. Determines if an INT signal is masked 334h SHMASK...

  • Page 119: Using Maskable Interrupts

    Interrupts or clearing of the SRC bit does not affect the vector generated, so INT1 and the USB share the same interrupt vector. Because only one can be generating interrupts at a time, this is unambiguous. All channels have a single programmable priority that is set in the CHxCON register.

  • Page 120: Using Nonmaskable Interrupts

    Interrupts the IMASK register. It is safe to write the MSK bits in the CHxCON registers while interrupts are enabled. 8. Program the SHMASK register to enable the INT and PIO interrupts that share Channel 14. The SHREQ interrupt request is generated if any shared interrupt is asserted that is not masked off in the SHMASK register.

  • Page 121: Interrupt Sequence

    Interrupts Software Interrupt: An interrupt initiated by the INT or INTO software instruction, or by a software exception. A software interrupt does not affect the IF flag. Software Exception: A software interrupt that occurs when an instruction causes a particular condition in the processor. A software exception does not affect the IF flag. Trace Interrupt: The trace interrupt is the highest priority interrupt.

  • Page 122: Servicing The Interrupt

    Interrupts 7.5.3.2 Servicing the Interrupt Nonmaskable interrupts—the trace interrupt, the NMI/watchdog timer interrupt, and software interrupts (both user-defined (INT) and software exceptions)—are serviced regardless of the setting of the IF flag in the FLAGS register. For more information about nonmaskable interrupts, see “Nonmaskable Interrupts” on page 7-18. For maskable hardware interrupt requests to be serviced, the IF flag must be set by the STI instruction, and the mask bit associated with each interrupt must be reset.

  • Page 123: Interrupt Priority

    Interrupts 7.5.4 Interrupt Priority Table 7-3 on page 7-12 shows the predefined types and overall priority structure for the Am186CC/CH/CU microcontrollers. The Overall Priority column shows the priority for the interrupts at power-on reset and at watchdog timer reset. Interrupt sources that constitute one request source share the same overall priority level with respect to other interrupt sources but are prioritized among themselves.

  • Page 124: Table 7-3 Interrupt Types

    Interrupts Table 7-3 Interrupt Types Related Instruction or Interrupt/ Vector Table Overall Interrupt Source EOI Type Address Priority Channel Nonmaskable Interrupts Divide Error Exception DIV, IDIV Trace Interrupt NMI / Watchdog Breakpoint Interrupt INT3 INTO Detected Overflow Exception INTO Array Bounds Exception BOUND Unused Opcode Exception Undefined Opcodes...

  • Page 125: Maskable Interrupts

    Interrupts 3. The type and overall priority for the INT1–INT7 pins in this table assume that these pins are being serviced by a dedicated channel; that is, they are not being serviced by channel 14. When the INT1–INT7 pins are being ser- viced by Channel 14, they share type 1Eh, overall priority 15, as indicated by the last row in Table 7-3.

  • Page 126: Interrupts In Polled Mode

    Interrupts 7.5.5.2 Interrupts In Polled Mode Software can handle interrupt requests in polled mode. In polled mode, configure the interrupt sources exactly as in normal interrupt mode, but do not set the IF bit in the FLAGS register. This disables automatic hardware servicing of interrupt requests. In this case, software must periodically read the POLL or POLLST register to determine if a valid interrupt request is pending.

  • Page 127: Maskable Interrupt Block Diagram

    Interrupts The interrupt controller uses the peripheral registers listed in Table 7-2 on page 7-5 to support generating a maskable interrupt. In addition, the FLAGS processor register contains a flag to enable the interrupts and one to set the trace interrupt. For more information about the interrupt registers, see “Registers Used”...

  • Page 128: Table 7-4 Interrupt Channel Map

    Interrupts Table 7-4 Interrupt Channel Map Interrupt Channel Interrupt Source Timer 0 Timer 1 Timer 2 High-Speed UART UART HDLC_A CC CH HDLC_B CC CH HDLC_C HDLC_D SDMA0 CC CH SDMA1 CC CH SDMA2 CC CU SDMA3 CC CU GP DMA0 GP DMA1 GP DMA2 GP DMA3...

  • Page 129: Table 7-5 Interrupt Channel Sources

    Interrupts Notes: 1. Channels 0 to 3 and 8 to 13 can have only one interrupt source active at a time (e.g., Channel 2 can only service the INT1 signal or the USB at any one time). Channels 4 to 7 (shaded) can service up to two sources at once (e.g., Channel 4 can service the HDLC_A as well as SDMA0 interrupt requests).

  • Page 130: Pios As Interrupts

    Interrupts 7.5.5.6 PIOs as Interrupts Eight PIOs (PIO5, PIO15, PIO27, PIO29, PIO30, PIO33, PIO34, and PIO35) are programmable as external interrupt sources on shared Channel 14. These PIOs are level- triggered. PIO15, PIO29, PIO30, PIO33, PIO34, and PIO35 default to their alternate function at external or internal reset.

  • Page 131: Software Interrupts

    Interrupts 7.5.6.1 Software Interrupts Up to 256 possible interrupts can be initiated by the INT or INTO instructions. INT 21h causes an interrupt to the vector located at 00084h in the interrupt vector table. INT FFh causes an interrupt to the vector located at 003FCh in the interrupt vector table. 7.5.6.2 Divide Error Exception (Interrupt Type 00h) When a DIV or IDIV instruction quotient cannot be expressed in the number of destination...

  • Page 132: Array Bounds Exception (Interrupt Type 05H)

    The interrupt controller supports the Fully Nested Master mode and Polled mode operation available in all AMD Am186 devices. The interrupt controller does not support Slave mode, Cascade mode, or Special Fully Nested mode. Support for the NMI and software interrupts are similar to Master mode in AMD’s Am186ES microcontroller.
  • Page 133 Interrupts The End-of-Interrupt (EOI) register is cleared, so no in-service bits are cleared. The Poll (POLL) and Poll Status (POLLST) registers are cleared, so Polling mode is disabled. The Interrupt Mask (IMASK) register and Shared Mask (SHMASK) registers are set to FFFFh, so all interrupts are masked.
  • Page 134 Interrupts 7-22 Am186™CC/CH/CU Microcontrollers User’s Manual...

  • Page 135: Chapter 8 Dma Controller

    CHAPTER DMA CONTROLLER OVERVIEW Direct memory access (DMA) permits the transfer of data between memory and peripherals without CPU involvement. With DMA transfers, the DMA controller becomes the bus master. The arbitration for the bus is internal to the processor and is not visible externally. When the DMA no longer has transfers pending (no internal or external DRQs are asserted) or a higher priority event occurs, the DMA controller removes its request for the bus thus freeing the bus for other types of cycles.
  • Page 136 DMA Controller pairs support the USB endpoints A, B, C, or D. On-chip peripherals that support general- purpose DMA are Timer 2, the two asynchronous serial ports (the UART and the High- Speed UART), and the USB peripheral controller. External peripherals support DMA transfers through the external DMA request signals.

  • Page 137: Block Diagram

    DMA Controller BLOCK DIAGRAM Figure 8-1 shows the block diagram for the general-purpose DMA and SmartDMA controllers. Figure 8-1 DMA Block Diagram DMAREG PCB Interface Address Decode 20-Bit Block ADD/SUB DMA3–0 CONTROL (2) DMA3–0 TRANSFER COUNT GP DMA DMA3–0 DEST ADDR (2) State Machine DMA3–0 SOURCE ADDR (2) SDMA3–0 CONTROL...

  • Page 138: System Design

    DMA Controller SYSTEM DESIGN Table 8-1 lists the DMA signals that are multiplexed with other microcontroller functions. Pinstraps are sampled only at external reset and do not affect the pin’s other functions, so they are not shown in this table. Other multiplexed signals, when enabled, either disable or alter any other functions that use the same pin.
  • Page 139 DMA Controller Table 8-2 DMA Controller Register Summary (Continued) Register Offset Register Name Description Mnemonic Four bits of this register [19–16], combined General-Purpose DMA0 Destination with the 16 bits of the low register, produce a 10Ah GD0DSTH Address High 20-bit destination address for general-purpose DMA Channel 0.
  • Page 140 DMA Controller Table 8-2 DMA Controller Register Summary (Continued) Register Offset Register Name Description Mnemonic SmartDMA Channel Pair 0 and 1 Registers CC CH 140h SD0CON SmartDMA0 Control Sets up SmartDMA Channel 0. Indicates the number of available buffer descriptors per transmit ring in SmartDMA Channel 0.

  • Page 141: Operation

    DMA Controller Table 8-2 DMA Controller Register Summary (Continued) Register Offset Register Name Description Mnemonic SmartDMA Channel Pair 2 and 3 Registers CC CU 170h SD2CON SmartDMA2 Control SmartDMA2 Transmit Ring Count / 172h SD2TRCAL Address Low SmartDMA2 Transmit Ring Address 174h SD2TRAH High...

  • Page 142: Table 8-3 Am186Cc Communications Controller Dma Channel Use

    DMA Controller Table 8-3 Am186CC Communications Controller DMA Channel Use DMA Channel Associated Peripheral Memory-to-memory transfers (note I/O space can be used in addition to memory space), Timer 2, external peripherals (via the DRQ General-Purpose DMA Channels 0–3 signals), internal UART or High-Speed UART, or any USB data endpoint (A–D) configured in either direction SmartDMA Pair 0 Receive Channel...

  • Page 143: When To Use Dma

    DMA Controller Table 8-5 Am186CU USB Microcontroller DMA Channel Use DMA Channel Associated Peripheral Memory-to-memory transfers (note I/O space can be used in addition to memory space), Timer 2, external peripherals (via the DRQ General-Purpose DMA Channels 0–3 signals), internal UART or High-Speed UART, or any USB data endpoint (A–D) configured in either direction USB data endpoint B if configured as a USB IN...

  • Page 144: Dma Request Synchronization

    DMA Controller the CPU to respond quickly to the NMI request. Software can also inhibit DMA transfers by setting the DHLT bit in the DMAHLT register. Priorities for the general-purpose DMA channels are set through the GDxCON0 registers; SmartDMA channel priorities are set with the SDxCON registers. 8.5.3 DMA Request Synchronization Synchronized data transfers are either source or destination synchronized—either the...

  • Page 145: General-Purpose Dma Channels

    DMA Controller or Circular Buffers” on page 8-20. This method helps guarantee data integrity by ensuring that data is transferred to main memory whether or not the interrupt task can execute. The DMA channel can be set to interrupt immediately on receipt of data by setting the Interrupt (INT) and Terminal Count (TC) bits in the GDxCON0 register.

  • Page 146: General-Purpose Dma Usage

    DMA Controller 8.5.6.1 General-Purpose DMA Usage Note: Before using the general-purpose DMA channels, ensure multiplexed signals are configured to reflect the use of DMA and not other functionality (see Table 8-1 on page 8-4). To use any of the four general-purpose DMA channels, software must perform the following steps.

  • Page 147: General-Purpose Dma Transfer Suspension

    DMA Controller 4. If the GDxTC register is non-zero, it decrements. 5. If the GDxTC register became zero and either the Terminal Count (TC) bit is set or the transfer type is unsynchronized, the Start/Stop (ST) bit is reset, and further DMA requests on that channel are ignored.

  • Page 148: General-Purpose Dma Terminal Count

    DMA Controller cycles. Word transfers to 8-bit address spaces are supported only when the source decrement or increment is 2 bytes. The Am186CC/CH/CU microcontrollers have the added feature of being able to transfer by DMA to and from the UART and High-Speed UART. The Am186CC and Am186CU microcontrollers can also transfer by DMA to and from USB peripherals.
  • Page 149 DMA Controller The DMA synchronization for the channel (“Setting Synchronization” on page 8-17) Whether DMA transfers use buffer queues or circular buffers (see “Using Buffer Queues or Circular Buffers” on page 8-20) 8.5.6.6.1 Generating Interrupts The general-purpose DMA channels can generate an interrupt request when the terminal count value in the GDxTC register reaches 0.

  • Page 150: Figure 8-3 Dma Request Sources

    DMA Controller Figure 8-3 DMA Request Sources DRQ Source Select External DRQ signal Memory or I/O Unsynchronized Transfer Timer 2 (latched) UART Receiver UART Transmitter High-Speed UART Receiver High-Speed UART Transmitter USB Endpoint A USB Endpoint B USB Endpoint C USB Endpoint D DMA Request from Timer 2 The GDxCON0 register can configure a DMA channel to accept the output of Timer 2 as...

  • Page 151: Table 8-7 General-Purpose Dma Request Source And Synchronization

    DMA Controller DMA Request from USB Because USB can use either general-purpose DMA or SmartDMA channels, this is discussed separately in “DMA and USB” on page 8-43. 8.5.6.6.5 Setting Synchronization The DSEL bit field in the GDxCON0 register sets the DMA request source for that channel (see “Selecting DMA Request Sources”...

  • Page 152: Figure 8-4 Source-Synchronized General-Purpose Dma Transfers

    DMA Controller a general-purpose DMA channel. In source synchronization, the device providing the data asserts the DMA request. Figure 8-4 shows a typical source-synchronized DMA transfer. When an external device is asserting DRQ, the request must be deasserted at least four clock cycles before the end of the transfer (at T1 of the deposit phase) to prevent another transfer from taking place.

  • Page 153: Figure 8-5 Destination-Synchronized General-Purpose Dma Transfers

    DMA Controller between destination-synchronized transfers. Table 8-8 shows the maximum DMA transfer rates based on the different synchronization strategies. Figure 8-5 Destination-Synchronized General-Purpose DMA Transfers Fetch Cycle Deposit Cycle CLKOUT (First case) (Second case) Notes: 1. This destination-synchronized transfer is not followed immediately by another DMA transfer, because DRQ is deasserted during the four idle states.
  • Page 154 DMA Controller A destination-synchronized transfer differs from a source-synchronized transfer in that the four cycle delay allows the destination device to deassert its DRQ signal four clocks before another request is latched. Without this delay, the destination device would not have time to deassert its DRQ signal.
  • Page 155 DMA Controller Example of Using Buffer Queues and Circular Buffers with the UARTs Note: This section discusses implementation tradeoffs for using the general-purpose DMA channels. To have a concrete system to discuss, the integrated UART and High-Speed UART are used as examples, but much of this information is applicable to using the general- purpose DMA channels with other peripherals as well.

  • Page 156: Table 8-9 Example Register Settings For Uarts And Circular Buffers

    DMA Controller Software must ensure that this buffer is aligned on a multiple of its size. This is easily done for statically allocated buffers with a good linker/locator; for dynamically allocated buffers, the software must waste the size of one buffer. This waste can usually be reduced or eliminated by allocating and deallocating additional buffers;...
  • Page 157 DMA Controller Table 8-9 Example Register Settings for UARTs and Circular Buffers (Continued) General-Purpose DMA Value for Value for Bit(s) in Register Register Transmit DMA Receive DMA GDxSRCH DSA[19–16] Buffer address DIV 64K 0 (Source Address High) GDxDSTL Buffer address DDA[15–0] (H)SPTXD (Destination Address Low)
  • Page 158 DMA Controller pointer from it, and dividing the result by the buffer size. The remainder of this division is the number of bytes available for reading. The difficulty again revolves around multitasking and flow control, with the added problem of error handling. Receive XON/XOFF Flow Control XON/XOFF flow control with DMA is problematic because, in general, the received flow control characters should not be stored in the buffer, and also because the characters...
  • Page 159 DMA Controller Receive Multitasking In a single-tasking system, received characters are held in the circular buffer until higher- level code is ready for them. In a multitasking system, it may be desirable for receipt of characters to cause an interrupt to signal that a task switch should take place. When DMA is used with one of the UARTs on the Am186CC/CH/CU microcontrollers, the hardware is typically programmed to cause interrupts under these two conditions: After a programmed number of characters have been received.

  • Page 160: Smartdma Channels

    SmartDMA Channels The Am186CC/CH/CU microcontrollers each contain SmartDMA channels, compatible with the DMA in the AMD Am79C90 C-LANCE (Local Area Network Controller for Ethernet). This LANCE-compatible buffer descriptor ring interface provides a method for transmission and reception of data across multiple memory buffers. The ring descriptor interface also provides a method for reporting status on multiple received and transmitted packets while ensuring that status information is always correctly linked with the associated data.

  • Page 161: Smartdma Channel Request Source And Synchronization

    DMA Controller performs this operation without software intervention, the latency is significantly lower than if an interrupt task performed the same operation. Software must still read and write the buffer descriptors, but the latency requirements are greatly relaxed because multiple descriptors are queued at one time. The software can take, on average, the time it takes to transmit or receive a buffer to update each descriptor, and software can increase allowable latency even more by updating several descriptors at the same time.

  • Page 162: Table 8-11 Am186Ch Smartdma Channel Request Source And Synchronization

    DMA Controller Table 8-11 Am186CH SmartDMA Channel Request Source and Synchronization SmartDMA Direction Source Destination Synchronization Channel Transmit Memory buffer HDLC A transmit FIFO Destination Receive HDLC A receive FIFO Memory buffer Source Transmit Memory buffer HDLC B transmit FIFO Destination Receive HDLC B receive FIFO...

  • Page 163: Figure 8-6 Smartdma Channel Descriptor Ring Example

    DMA Controller The owner semaphore (OWN) bit is a single-bit field in each buffer descriptor. This bit is set by software when the buffer is valid—either it contains valid data for transmission or it is available to be overwritten by the receiver. The SmartDMA controller never sets the OWN bit.

  • Page 164: Figure 8-7 Smartdma Channel Memory Management

    DMA Controller Figure 8-7 SmartDMA Channel Memory Management Transmit Data Buffer Queue Transmit Descriptor Ring Transmit Data Transmit Buffer 1 Address Buffer Transmit Buffer 1 Status/Config Transmit Buffer 1 Byte Count Transmit Transmit Buffer 1(Unused) SmartDMA Channel Transmit Ring Address Data Transmit Buffer 2 Address Registers (SDxTRCAL and SDxTRAH)

  • Page 165: Smartdma Channel Usage

    DMA Controller 8.5.7.3.2 Receive Descriptor Ring If Figure 8-6 is a receive descriptor ring, then the OWN bit in the current buffer descriptor was 1 when the receive channel began to receive packet x. The packet was not completely received before reaching the terminal count for buffer 1, so the channel cleared the owner semaphore for descriptor 1, releasing it for processing by software, and advanced to 2 for continued reception of the packet.
  • Page 166 DMA Controller Microcontrollers Register Set Manual , order #21916. Even when the ring size is set to 1, that entry is still interpreted as a descriptor, not as the memory buffer itself. 5. Point to the first buffer descriptor by clearing the SDxCBD register to 0. Program the Interrupt Conditions The interrupt conditions are typically configured only once.
  • Page 167 DMA Controller d. Set to 1 the OWN bit in Word 1 to indicate the descriptor entry is owned by the SmartDMA channel. e. To force a poll of the OWN bit of the current buffer descriptor, set to 1 the POLL bit in the SDxCON register.
  • Page 168 DMA Controller Register Set Manual , order #21916. Even when the ring size is set to 1, that entry is still interpreted as a descriptor, not as the memory buffer itself. 5. Point to the first buffer descriptor by clearing the SDxCBD register to 0. Program the Interrupt Conditions The interrupt conditions are typically configured only once.

  • Page 169: Smartdma Channel Cycle

    DMA Controller In the Am186CU USB microcontroller, the DSEL bit in the SDxCON register must be set to 1. Software clears the status bits in SDxSTAT after receiving an interrupt. Software can use the SDxCBD register to monitor the transmit and receive buffers. Software can also use the SDxCRAD register to determine the address in memory where the DMA receive process was interrupted.
  • Page 170 DMA Controller If the OWN bit is 0, the software owns the current descriptor. In this case, the SmartDMA transmit channel periodically polls the descriptor until the OWN bit becomes 1. The transmit channel does not advance past a descriptor for which the OWN bit is 0. For information about forcing a poll, see “SmartDMA Channel Descriptor Polling”...

  • Page 171: Figure 8-8 Smartdma Transmit Channel Flow Diagram

    DMA Controller Figure 8-8 SmartDMA Transmit Channel Flow Diagram Owner semaphore bit set Owner semaphore bit not set and not start-of-packet OWN=1 OWN=0 STP=0 Search for available buffer Initialize channel Search for OWN=1 start-of-packet Clear owner OWN=1 Owner semaphore bit set semaphore bit STP=1 and advance to...

  • Page 172: Figure 8-9 Smartdma Receive Channel Flow Diagram

    DMA Controller 5. If the terminal count reaches zero before the end-of-packet signal from the device is asserted, the receiver closes the current buffer and enters Get-Next-Buffer mode. In this mode, the receiver reads the next descriptor in the descriptor ring and determines if the OWN bit is set.

  • Page 173: Table 8-13 Smartdma Transmit Channel Descriptor Format

    DMA Controller Table 8-13 SmartDMA Transmit Channel Descriptor Format Bit Number Bit Name Description Transmit Buffer Address (Word 0) The LADR (Low Order) field contains the 16 low-order address bits of the data buffer 15–0 pointed to by this descriptor. The LADR field is written by the software and not changed LADR by the SmartDMA channel.

  • Page 174: Table 8-14 Smartdma Receive Channel Descriptor Format

    DMA Controller Table 8-14 SmartDMA Receive Channel Descriptor Format Bit Number Bit Name Description Receive Buffer Address (Word 0) The LADR (Low Order) field contains the 16 low order address bits of the data buffer 15–0 pointed to by this descriptor. The LADR field is written by the software and not LADR changed by the SmartDMA channel.

  • Page 175: Smartdma Channel Descriptor Polling

    DMA Controller Table 8-14 SmartDMA Receive Channel Descriptor Format (Continued) Bit Number Bit Name Description The HADR (High Order) field contains the eight high-order address bits of the data buffer pointed to by this descriptor. The highest four bits of the address must be set 7–0 to 0000b.

  • Page 176: Smartdma Channel Interrupts

    DMA Controller 8.5.7.8 SmartDMA Channel Interrupts SmartDMA channels can generate interrupts based on three conditions. The interrupt remains pending until software clears the associated status bit(s). The following list shows the different interrupt types, and gives some useful information about the characteristics of the interrupt. TEPI and REPI (Transmit/Receive End of Packet) interrupts are asserted when the last byte of a packet is transmitted or received.

  • Page 177: Dma And Usb

    DMA Controller The following facilities aid in SmartDMA channel circular buffer management: When receiving transparent HDLC data, no buffer status is transferred to the SmartDMA channel. The received data is simply a continuous stream of samples, and the SmartDMA controller keeps cycling through buffers without ever storing an EOP. The TXSO and RXSO bits in the SDxCON registers can be set to keep the DMA controller from returning buffer descriptors to the software.

  • Page 178: Initialization

    DMA Controller INITIALIZATION On both an internal and external reset, the following occurs: All the general-purpose DMA and SmartDMA channel registers are cleared to 0. Any DMA transfer in progress is aborted. Multiplexed signal DRQ0 defaults to its PIO functionality. 8-44 Am186™CC/CH/CU Microcontrollers User’s Manual...

  • Page 179: Chapter 9 Programmable I/O Signals 9.1 Overview

    CHAPTER PROGRAMMABLE I/O SIGNALS OVERVIEW The Am186CC/CH/CU microcontrollers provide 48 user-programmable input/output signals (PIOs). Many of these signals share a pin with at least one alternate function. If an application does not need the alternate function, the associated PIO can be programmed through the PIO registers.

  • Page 180: Figure 9-1 Pio Operation Block Diagram

    Programmable I/O Signals Figure 9-1 PIO Operation Block Diagram Read Dir Write Direction Register Mode Alternate Read Mode Function Write Data Out Mode Mode Register Write Read Set Read Clear Data Write Output Data or V 100K Write Data Clear Read Data Input PIO Data...

  • Page 181: Table 9-1 Pio Multiplexed Signals

    Programmable I/O Signals Table 9-1 PIO Multiplexed Signals Signal Multiplexed Signal(s) Default Signal Register[Bit] PIO0 TMRIN1 PIO0: input with pullup PIOMODE0[0] PIO1 TMROUT1 PIO1: input with pulldown PIOMODE0[1] PIO2 PCS5 PIO2: input with pullup PIOMODE0[2] PIO3 PCS4 PIO3: input with pullup PIOMODE0[3] PIO4 MCS0...
  • Page 182 Programmable I/O Signals Table 9-1 PIO Multiplexed Signals (Continued) Signal Multiplexed Signal(s) Default Signal Register[Bit] PIO29 DT/R DT/R: three-state output with pullup PIOMODE1[13] PIO30 DEN / DS DEN: three-state output with pullup PIOMODE1[14] PIO31 PCS7 PIO31: input with pullup PIOMODE1[15] PIO32 PCS6 PIO32: input with pullup...

  • Page 183: Usage

    Programmable I/O Signals REGISTERS The 16 registers listed in Table 9-2 program the PIO signals. Appendix A summarizes the bits in all the registers. For a complete description of all the peripheral registers, see the Am186™CC/CH/CU Microcontrollers Register Set Manual , order #21916. Table 9-2 PIO Register Summary Register...

  • Page 184: Driving Data On The Pio

    Programmable I/O Signals Table 9-3 PIO Mode and PIO Direction Register Bit Settings Mode Mode Direction Pin Function Register Register Alternate operation with pullup/pulldown (PIO Alternate Operation functionality disabled) PIO input with pullup/pulldown PIO output with pullup/pulldown PIO input without pullup/pulldown Notes: 1.

  • Page 185: Hardware-Related Considerations

    Programmable I/O Signals 9.5.6 Hardware-Related Considerations Choose your PIOs wisely. The following PIO signals are multiplexed with alternate signals that may be used by emulators: PIO8, PIO15, PIO33, PIO34, and PIO35. Consider any emulator requirements for the alternate signals before using these pins as PIOs. For more information, see Chapter 4, “Emulator Support.”...
  • Page 186 Programmable I/O Signals Am186™CC/CH/CU Microcontrollers User’s Manual...

  • Page 187: Figure 10-1 Programmable Timers Block Diagram

    CHAPTER PROGRAMMABLE TIMERS 10.1 OVERVIEW There are three 16-bit programmable timers in the Am186CC/CH/CU microcontrollers. Timers 0 and 1 are identical and may be used to generate periodic external signals or waveforms or to count or time external events. Each of these two timers has an input and an output pin.

  • Page 188: Table 10-1 Programmable Timer Multiplexed Signals

    Programmable Timers 10.3 SYSTEM DESIGN Table 10-1 lists the programmable timer signals that are multiplexed with other microcontroller functions. Pinstraps are sampled only at external reset and do not affect the pin’s other functions, so they are not shown in this table. When TMRIN0 or TMRIN1 is programmed as a PIO, the corresponding signal is held high (asserted) internally, except in PWD mode where TMRIN0 is replaced with INT8 and TMRIN1 is replaced with the inverse of INT8.

  • Page 189: Operation

    Programmable Timers 10.5 OPERATION 10.5.1 Usage Note: If Timer 0 or Timer 1 is being used without the associated TMRIN pin, the pin must be held high or programmed as a PIO, otherwise the timer will not increment. Before using the programmable timers, ensure multiplexed pins are configured to reflect the use of the timers and not other functionality (see Table 10-1).

  • Page 190: Table 10-3 Timer 0 And Timer 1 Behavior

    Programmable Timers Three bits in the control register and the external TMRIN pin control the way Timer 0 and Timer 1 count: When the EXT (external clock) bit is set, the TMRIN signal provides the clock for the associated timer. In this mode, the timer count increments once for each low to high transition on the TMRIN pin.

  • Page 191: Requesting Interrupts

    Programmable Timers When ALT is set and the timer is using TxCMPA (initial value after reset), the timer behaves as follows: The RIU (Register-In-Use) bit is zero (this is a read-only bit). Holds the TMROUTx signal High (inverse of RIU). Each time the timer increments, it compares the value in TxCNT to the value in TxCMPA.

  • Page 192: Figure 10-2 Pulse Width Demodulation Example

    High phase of the output waveform. The TxCMPB value determines the duration of the Low phase of the output waveform. For more information, see the timer examples available on the AMD website at ftp.amd.com. 10.5.7 Pulse Width Demodulation For many applications, such as bar-code reading, it is necessary to measure the width of a signal in both its High and Low phases.

  • Page 193: Handling Short Signal Durations

    Programmable Timers As shown in Figure 10-1 on page 10-1, entering pulse width demodulation mode by setting the PWD bit in the SYSCON register does not have any direct effect on the timer block other than to reroute the TMRIN0 and TMRIN1 signals. The timers retain their full functionality and programmability.

  • Page 194: Software-Related Considerations

    Programmable Timers 10.5.8 Software-Related Considerations Timer 2 can generate a DMA request. For more information, see Chapter 8, “DMA Controller.” Timer 0 and Timer 1 each have two 16-bit count compare registers. These registers can be used together to expand the time resolution for the timers. For more information, see the Timer Mode and Control registers in the Am186™CC/CH/CU Microcontrollers Register Set Manual , order #21916.

  • Page 195: Figure 11-1 Watchdog Timer Block Diagram

    CHAPTER WATCHDOG TIMER 11.1 OVERVIEW The Am186CC/CH/CU microcontrollers provide a full-featured watchdog timer that can generate nonmaskable interrupts (NMIs), internal resets, and system resets when the time- out value is reached. The time-out value is programmable and ranges from 2 to 2 processor clocks.

  • Page 196: Table 11-1 Watchdog Timer Multiplexed Signals

    Watchdog Timer 11.3 SYSTEM DESIGN Table 11-1 lists the watchdog timer signals that are multiplexed with other microcontroller functions. Pinstraps are sampled only at external reset and do not affect the pin’s other functions, so they are not shown in this table. Other multiplexed signals, when enabled, either disable or alter any other functions that use the same pin.

  • Page 197: Figure 11-2 Access To The Wdtcon Register

    Watchdog Timer 11.4 REGISTERS The register shown in Table 11-2, WDTCON, programs the watchdog timer. Figure 11-2 illustrates the rules for accessing the WDTCON register. Appendix A summarizes the bits in all the registers. For a complete description of all the peripheral registers, see the Am186™CC/CH/CU Microcontrollers Register Set Manual , order #21916.

  • Page 198: Overview

    Debug monitor software (such as AMD’s E86MON™ software) can disable the watchdog timer, allowing the user to interact with the monitor without having to refresh the watchdog timer.

  • Page 199: Software-Related Considerations

    Watchdog Timer 11.5.4 Software-Related Considerations Even if the watchdog-timer default configuration is appropriate for the application, software should always perform an enabling write to the watchdog timer. This write causes most of the fields of the WDTCON register to become read-only, preventing run- away code from disabling or otherwise modifying the watchdog timer behavior.
  • Page 200 Watchdog Timer 11-6 Am186™CC/CH/CU Microcontrollers User’s Manual...

  • Page 201: Chapter 12 Serial Communications Overview

    CHAPTER SERIAL COMMUNICATIONS OVERVIEW 12.1 OVERVIEW The Am186CC/CH/CU microcontrollers support both asynchronous and synchronous serial communications. These features are described in the chapters indicated in the bullets below. The remainder of this chapter shows some of the trade-offs of using the various serial communications features available on the microcontroller and provides a brief overview of serial communications.

  • Page 202: Table 12-1 Multiplexed Signal Trade-Offs For Serial Interfaces

    Serial Communications Overview 12.2 SYSTEM DESIGN 12.2.1 Multiplexed Signals The serial interfaces in the Am186CC/CH/CU microcontrollers are multiplexed as shown in Table 12-1. Because of the multiplexing, there are some design trade-offs, as shown in the table. The figures that follow the table show how the microcontroller’s serial communications features could be used in typical applications.

  • Page 203: Controller

    Serial Communications Overview Table 12-1 Multiplexed Signal Trade-Offs for Serial Interfaces (Continued) Function Used Functions Lost Inter- Inter- Inter- Inter- Inter- Name Name Name Name Name face face face face face PCM_RXD_D DCE_RXD_D RXD_U — PIO26 PCM_TXD_D DCE_TXD_D TXD_U — PIO20 Low- High-...

  • Page 204: Figure 12-1 Hdlc Control Application

    Serial Communications Overview Figure 12-1 HDLC Control Application UARTs HDLC Channels High- UART Speed Channel D Channel C Channel B Channel A UART External Interface Debug or Raw DCE Raw DCE Raw DCE Raw DCE console External External External External UART interface interface...

  • Page 205: Figure 12-3 Isdn Application

    Serial Communications Overview Figure 12-3 ISDN Application UARTs HDLC Channels High- UART Speed Channel D Channel C Channel B Channel A UART TSA Channels Channel D Channel C Channel B Channel A External Interface Optional USB SSI to Connection External interface D is External interfaces External connection to...

  • Page 206: Serial Communications Introduction

    Serial Communications Overview 12.3 SERIAL COMMUNICATIONS INTRODUCTION In serial communications, one data bit at a time is transmitted through a single wire or communication channel. Because a processor data bus uses parallel communications (more than one data bit is transmitted at the same time through more than one wire), the communications channel must convert data to serial at the transmitter and then back to parallel at the receiver.

  • Page 207: Figure 12-5 Cts/Rtr Protocol

    Serial Communications Overview Figure 12-5 CTS/RTR Protocol Port 1 Port 2 Transmitter Receiver Receiver Transmitter CTS = Input signal to the transmitter; clear to send input RTR = Output signal from the receiver; ready to receive output 12.3.3 FIFOs Another way to reduce data overflow is to use a hardware FIFO (First In First Out data buffer).

  • Page 208: Simplex, Half-Duplex, And Full-Duplex Systems

    Serial Communications Overview 12.3.5 Simplex, Half-Duplex, and Full-Duplex Systems In serial communications, a simplex system can transmit data in only one direction; a half- duplex system can send data in either direction, but not both at the same time; a full-duplex system can send data in both directions simultaneously.

  • Page 209: Chapter 13 Asynchronous Serial Ports (Uarts)

    CHAPTER ASYNCHRONOUS SERIAL PORTS (UARTS) 13.1 OVERVIEW The Am186CC/CH/CU microcontrollers each provide two independent asynchronous serial ports: a Universal Asynchronous Receiver/Transmitter (UART) and a High-Speed UART. The UARTs support the following features: Up to 115.2 Kbaud rate (UART) or up to 460 Kbaud rate (High-Speed UART) Automatic baudrate detection with enhancements to compensate for distortion of start bit (High-Speed UART only) 32-byte receive and 16-byte transmit FIFOs with threshold at half full (High-Speed UART...

  • Page 210: Figure 13-1 Uarts Block Diagram

    Asynchronous Serial Ports (UARTs) – Receive overflow error detected – Parity error detected – Transmitter empty – Receive line idle The High-Speed UART interface has been designed so that code written to run on the UART runs on the High-Speed UART with no modification other than adjusting the register offsets.

  • Page 211: Table 13-1 Uarts Multiplexed Signals

    Asynchronous Serial Ports (UARTs) 13.3 SYSTEM DESIGN Table 13-1 lists the UART signals that are multiplexed with other microcontroller functions. Pinstraps are sampled only at external reset and do not affect the pin’s other functions, so they are not shown in this table. Other multiplexed signals, when enabled, either disable or alter any other functions that use the same pin.

  • Page 212: Operation

    Asynchronous Serial Ports (UARTs) Table 13-2 UARTs Register Summary Register Offset Register Name Description Mnemonic High-Speed UART 260h HSPCON0 High-Speed Serial Port Control 0 Configures and enables serial port. 262h HSPCON1 High-Speed Serial Port Control 1 Configures serial port. Provides information about the current status 264h HSPSTAT High-Speed Serial Port Status...

  • Page 213: Transmit

    Asynchronous Serial Ports (UARTs) register name indicates that both the UART and the High-Speed UART registers are being described. 13.5.1.1 Transmit This section describes the procedure for programming a transmit. To program a receive, see page 13-6. To use autobaud mode, see page 13-7. Transfers can be done in Polled, Interrupt, or DMA modes.

  • Page 214: Receive

    Asynchronous Serial Ports (UARTs) When extended writes and address bits are enabled , 9-bit data should be written to the (H)SPTXD register. The first word should include the AB bit value (set the transmit AB (AB) bit in the (H)SPTXD register to 1 followed by the address bits in the TDATA field). Then the following words should contain AB = 0 and the data for the designated address point.

  • Page 215: Autobaud Mode (High-Speed Uart Only)

    Asynchronous Serial Ports (UARTs) 13.5.1.2.3 Receiving Data When the receiver is initialized, to receive data: 1. Read the (H)SPSTAT register: a. Verify that the RDR bit is set to 1 to ensure the RDATA field contains valid data. b. Read the other status bits to check the status on the last byte received and clear any status bits that were set.

  • Page 216: Figure 13-2 Uarts Frame

    Asynchronous Serial Ports (UARTs) 13.5.2 Data In asynchronous serial port communication, data is transmitted in frames . Each frame begins with a start bit (Low) and ends with one or two stop bits (High). After the start bit is transmitted, the data bits are transmitted serially, least significant bit first. Data can be 7 or 8 bits, plus an optional address bit.

  • Page 217: Address Bits

    Asynchronous Serial Ports (UARTs) The OER bit in the (H)SPSTAT status register is set to 1 when the receiver has a data overrun error. When extended reads are enabled, the OER bit in the (H)SPRXD receive data register is set to 1, and then a 1 is written to the OER bit in the status register. When FIFOs are enabled, the OER bit in the receive data register is passed through the FIFO with the last character of overrun data (i.e., the first data character after the overrun loss).

  • Page 218: Receive Status And Data

    Asynchronous Serial Ports (UARTs) 13.5.2.2.2 Receiving with Address Bit Set In a receive, when ABEN is set in the HSPCON0 register, the most significant bit of received data can be read in the AB bit in the (H)SPSTAT register. The received AB bit can optionally generate an interrupt (if the AB bit is set in the HSPIMSK register and the RSIE bit is set in the HSPCON0 register).

  • Page 219: Fifos (High-Speed Uart Only)

    Asynchronous Serial Ports (UARTs) frame. At the end of the receipt of a sequence of frames, software can examine the value of the (H)SPSTAT register to determine if any significant status bits have been set. If the accumulated status does not reflect action required by software, the status bytes can be ignored, otherwise software can traverse the buffer searching for the status of interest and its associated data byte.

  • Page 220: Receive Fifo

    Asynchronous Serial Ports (UARTs) When both the FIFO and a transmit have been enabled (with the TFEN and TMODE bits), hardware immediately checks the Transmit FIFO Threshold Reached (TTHRSH) bit in the status register. The transmit FIFO threshold value is set to half-empty (FIFO contains eight bytes of data) and is not programmable.

  • Page 221: Cts/Rtr Hardware Flow Control

    Asynchronous Serial Ports (UARTs) data register. The new status is ORed with the previous status, possibly accumulating status over multiple frames. For this reason, the status register must be read before the receive data register to ensure that the status being read is for the current frame. Set status bits must be cleared by software.

  • Page 222: Figure 13-4 Rtr_U Signal Behavior

    Asynchronous Serial Ports (UARTs) Figure 13-4 illustrates the behavior of the RTR_U signal. Figure 13-5 illustrates the behavior of the RTR_U signal with the FIFO. Note that the RTR_U signal is deasserted as soon as the serial port begins receiving a character and is reasserted when the data is read from the receive data register.

  • Page 223: Figure 13-6 Uarts Clock

    Asynchronous Serial Ports (UARTs) Figure 13-6 UARTs Clock CPU Clock Oversample Stage 1 Divide Baud clock baud clock UCLK divisor oversampling (HS)UART Clock Select Autobaud clock (High-Speed UART only) 13.5.5.1 Programming the Baud Rate The formula for determining the baud divisor register value is: BAUDDIV = (clock frequency / (16 •...

  • Page 224: Receiver Bit Sampling

    Asynchronous Serial Ports (UARTs) 13.5.5.2 Receiver Bit Sampling Whenever the receiver is enabled and is not in-frame (i.e., no data frame is currently being received), it remains in a Search-for-start-bit mode. In this mode, the receiver looks for a High to Low transition of the RXD input. This sampling is done based on the divided Baud Clock.

  • Page 225: Figure 13-7 Worst Case % Error Per Bit Vs. Baud Divisor Without Autobaud Enhancement

    Asynchronous Serial Ports (UARTs) Figure 13-7 Worst Case % Error Per Bit vs. Baud Divisor Without Autobaud Enhancement Worst Case % Error Error Range BAUD DIV Worst case % error per bit = 1 – BAUD DIV + .5 4.3% .29% 9 10 Baud Divisor...

  • Page 226: Figure 13-9 Autobaud Enhancement

    Asynchronous Serial Ports (UARTs) or equal to threshold 1 and greater than threshold 0 selects the divisor 1 value, and so on. A value greater than threshold 3 uses the calculated divisor value. If the registers are not programmed (are in reset state), the High-Speed UART uses the autobaud calculated baud divisor value.

  • Page 227: Interrupt Sources

    Asynchronous Serial Ports (UARTs) HSPABx registers, which is not programmed in the ABDIV field for one of the HSPABx registers, is unattainable for that system. In example B, the HSPAB0 register is not being used. The value of the ABDIV field for HSPAB3 is greater than the ABTHRSH field for that register.

  • Page 228: Figure 13-10 Break Character Example

    Asynchronous Serial Ports (UARTs) 13.5.7 Break Detection and Generation The UARTs support detection of break characters. A break is defined as a constant Low signal on the receive data line for one frame time or greater. This is reported as a zero character with the framing error (FER) and break (BRK) status bits set in the (H)SPSTAT register.

  • Page 229: Interface To General-Purpose Dma Channels

    Asynchronous Serial Ports (UARTs) 13.5.8 Receive Special-Character Matching (High-Speed UART Only) The High-Speed UART provides a method of generating interrupts on special characters. Up to six special characters can be matched. Special-character matching is enabled by the MEN bit in the HSPCON1 register. The special characters are written by software into three 16-bit character match registers (HSPM0, HSPM1, and HSPM2).
  • Page 230 Asynchronous Serial Ports (UARTs) data in memory so that the association of status and data is not lost. This behavior is not affected by enabling or disabling the receive FIFO on the High-Speed UART. Unlike the other status interrupts that move through the receive FIFO with their associated data, the OERIM bit provides immediate notification of an overrun error condition.

  • Page 231: Comparison To Other Devices

    Asynchronous Serial Ports (UARTs) 13.5.12 Comparison to Other Devices The UARTs are similar to those of the other Am186 family microcontrollers and are most closely related to those of the Am186ES and Am186ED microcontrollers. However, the functionality provided by the serial port modes of those devices have been replaced by individual enables that allow for more flexibility on the UARTs and the configuration of the DMA interface has been modified.
  • Page 232 Asynchronous Serial Ports (UARTs) 13-24 Am186™CC/CH/CU Microcontrollers User’s Manual...

  • Page 233: Chapter 14 Synchronous Serial Port (Ssi)

    CHAPTER SYNCHRONOUS SERIAL PORT (SSI) 14.1 OVERVIEW The Am186CC/CH/CU microcontrollers each include one synchronous serial port, which uses the SSI to provide a half-duplex, bidirectional communications interface between the microcontroller and other system components (i.e., integrated circuits). This interface is typically used by the microcontroller to monitor the status of other system devices or to configure these devices under software control.

  • Page 234: Figure 14-1 Ssi Block Diagram

    Synchronous Serial Port (SSI) Figure 14-1 SSI Block Diagram Block Select Register Control Internal Register Offset Block Read Read Data Read Data Enable Register Read Data Selects 16 x 5 Internal Transmit Data Bidirectional Write Data SDATA 5 Registers/ Shift Register Decode SDATA Receive Data...

  • Page 235: Figure 14-2 Synchronous Serial Interface System Application Example

    Synchronous Serial Port (SSI) Figure 14-2 Synchronous Serial Interface System Application Example Synchronous Serial Interface Peripheral (Multiplexed Data In/Out Pin) SDEN ENABLE SCLK SDATA DATA Am186CC/CH/CU Microcontroller ENABLE DATA_IN DATA_OUT Synchronous Serial Interface Peripheral (Dedicated Data In/Out Pins) 14.4 REGISTERS The registers listed in Table 14-2 program the SSI.

  • Page 236: Operation

    Synchronous Serial Port (SSI) 14.5 OPERATION 14.5.1 Usage Note: Before using the SSI port, ensure multiplexed pins are configured to reflect the use of SSI and not other functionality (see Table 14-1 on page 14-2). 1. Set the ENHCTL bit in the SSSTAT register to 1 so that all bits in the SSCON register are operational (unless Am186EM-backwards compatibility is required).

  • Page 237: Sdata

    Synchronous Serial Port (SSI) the falling edge of the SCLK signal and is received (latched into the microcontroller) on the rising edge of the SCLK signal. In the Inverted Clock mode, data is transmitted on the SDATA pin on the rising edge of the SCLK signal and is received (latched into the microcontroller) on the falling edge of the SCLK signal.

  • Page 238: Ssi Transactions

    Synchronous Serial Port (SSI) signal. Setting DE0 asserts the SDEN signal. Asserting SDEN enables the external device to which this signal is connected for communication on the SSI. Writing the transmit register or reading the receive register initiates a data transfer on the SSI. Software can configure the SDEN signal to be active High or Low with the DENP bit in the SSCON register.

  • Page 239: Figure 14-3 Ssi Multiple Transmit With Sden As External Device Enable

    Synchronous Serial Port (SSI) Figure 14-3 SSI Multiple Transmit with SDEN as External Device Enable PB=0 PB=0 PB=0 PB=0 PB=0 PB=1 PB=1 PB=1 DR/DT=0 DR/DT=1 DR/DT=1 DR/DT=0 DR/DT=0 DR/DT=1 DR/DT=0 DR/DT=0 SDEN SCLK LSB (Normal shift order) MSB SDATA PB=1 PB=1 PB=1 Write...

  • Page 240: Figure 14-5 Ssi Single-Transmit, Multiple-Receive With Sden As External Device Enable

    Synchronous Serial Port (SSI) Figure 14-5 SSI Single-Transmit, Multiple-Receive with SDEN as External Device Enable PB=0 PB=0 PB=0 PB=0 PB=1 PB=0 PB=1 PB=1 DR/DT=0 DR/DT=1 DR/DT=1 DR/DT=1 DR/DT=0 DR/DT=0 DR/DT=0 DR/DT=0 SDEN SCLK MSB(Reverse shift order)LSB SDATA PB=1 PB=1 PB=1 Clear Write Read...

  • Page 241: Initialization

    Synchronous Serial Port (SSI) Only one dedicated SSI enable pin is available. PIOs can be used for additional device enables if they are required. Software written for the Am186EM SSI that writes to the SSI status register does not work on the Am186CC/CH/CU microcontrollers. Only the /2 and /4 clock modes are available unless software sets the ENHCTL bit in the SSSTAT register.
  • Page 242 Synchronous Serial Port (SSI) 14-10 Am186™CC/CH/CU Microcontrollers User’s Manual...

  • Page 243: Figure 15-1 Hdlc Frame

    CHAPTER HIGH-LEVEL DATA LINK CONTROL (HDLC) Note: Only the Am186CC and Am186CH microcontrollers support HDLC. 15.1 OVERVIEW In the Open Systems Interconnection (OSI) model, layer two is the data link layer. This layer provides control between physical nodes: link initialization, flow control, and error control. One protocol that performs this function is High-level Data Link Control (HDLC).

  • Page 244: Block Diagram

    High-Level Data Link Control (HDLC) The microcontroller uses FIFOs in both directions (16-byte transmit and 32-byte receive) to isolate the data requests from the system bus. The controller supports SmartDMA and programmed I/O for filling or emptying the FIFOs. Each HDLC channel can connect to an external serial interface directly (nonmultiplexed mode) or can pass through a time slot assigner (multiplexed mode).
  • Page 245 HDLC Control/Status Internal RTR Receiver Time Clock Receive CLK (A, B, C, D) receive data Control receive clock Transmit CLK (A, B, C, D) transmit clock 32 x 8 FIFO transmit data Receive DATA (A, B, C, D) Data Mux Transmit DATA (A, B, C, D) Interface Control...

  • Page 246: System Design

    High-Level Data Link Control (HDLC) 15.3 SYSTEM DESIGN Table 15-1 lists the HDLC/TSA/GCI signals that are multiplexed with other microcontroller functions. Pinstraps are sampled only at external reset and do not affect the pin’s other functions, so they are not shown in this table. Other multiplexed signals, when enabled, either disable or alter any other functions that use the same pin.

  • Page 247: Registers

    High-Level Data Link Control (HDLC) Table 15-1 HDLC/TSA/GCI Multiplexed Signals (Continued) Multiplexed Signals Default External Interface Function Signal PIOs UART DCE and PCM data input/ DCE_RXD_D PCM_RXD_D — RXD_U PIO26 PIO26 UART data receive DCE and PCM data output/ DCE_TXD_D PCM_TXD_D —...

  • Page 248: Table 15-2 Hdlc Register Summary

    High-Level Data Link Control (HDLC) Table 15-2 HDLC Register Summary Register Register Name Description Offset Mnemonic Sets operating modes for both the transmitter HxCON HDLC Channel Control and receiver. HxTCON0 HDLC Channel Transmit Control 0 Sets operating modes for transmitter. HxTCON1 HDLC Channel Transmit Control 1 HxRCON0...

  • Page 249: Operation

    High-Level Data Link Control (HDLC) Table 15-2 HDLC Register Summary (Continued) Register Register Name Description Offset Mnemonic HDLC Channel Mismatch Address Copy of HxMACNT register that does not HxMACNTP Counter Peek change when read. Contains the value to compare to the address HxA0 HDLC Channel Address 0 in the received frames.

  • Page 250: Interface

    High-Level Data Link Control (HDLC) 3. Set the necessary transmit enables (HxTXON0 register) and receive enables (HxRCON0 register) for each HDLC channel. 4. Do an HDLC reset. A reset flushes the FIFOs and clears all R/0 status bits, but does not clear the R/W0 interrupt status registers.

  • Page 251: General Hdlc Options

    High-Level Data Link Control (HDLC) The receive status indicates the following information: If there was an overflow of the receive FIFO If a non-integer number of bytes were received If a CRC error was detected Which address was matched If the frame was too short or too long If the receiver was turned off during the frame If the frame ended with an abort (one zero followed by seven to 14 consecutive 1s).

  • Page 252: Hdlc Transmitter

    High-Level Data Link Control (HDLC) Remote Loopback Mode: To enable Remote Loopback mode, set the LOOPR bit in the HxCON register to 1. Remote Loopback disables the transmitter and echoes the data received at the serial input out to the serial output. The receiver operates normally in this mode.
  • Page 253 High-Level Data Link Control (HDLC) The HDLC transmitters have the following features: Transmit FIFO: The transmit FIFO consists of a 16-byte FIFO buffer, end-of-frame logic, and DMA-request logic. When using programmed I/O to fill the transmit FIFO, a bit must be set after the last byte in a frame is written to the FIFO.
  • Page 254 High-Level Data Link Control (HDLC) Abort Generation: The HDLC transmitter sends an abort sequence (one 0 followed by seven to 14 1s) whenever the FORABR bit of the HxTCON0 register is set to 1. The transmitter continues sending an abort sequence as long as this bit is set; however, if the send abort bit is set and cleared on two successive writes to the HDLC Command/ Control register, at least one abort character is sent.
  • Page 255 High-Level Data Link Control (HDLC) transmitter status in the FABRST, CTSLST, TUFLO, TGOODF, and TSTOP bits of the HxISTAT0 register. Automatic CTS: When automatic CTS is enabled, the transmitter does not start transmission until CTS is asserted. If the transmitter is transmitting (in-frame) and CTS is deasserted, a lost CTS has occurred.

  • Page 256: Hdlc Receiver

    High-Level Data Link Control (HDLC) Figure 15-6 shows another typical transmit with auto-enable CTS enabled. At the end of the closing flag, CTS is driven inactive. CTS is actually driven inactive at the same time as the last bit of the byte before the flag, but it is not recognized until the next bit; therefore, a lost CTS does not occur.

  • Page 257: Figure 15-7 Hdlc Receiver Block Diagram

    High-Level Data Link Control (HDLC) Note: The HDLC receiver requires frames two bytes or longer. The HDLC transmitter requires at least one byte of data surrounded by flags: the start flag, one byte of data, and the end flag. A 2-byte CRC with no data also constitutes a valid transmission. Figure 15-7 HDLC Receiver Block Diagram CRC Checker (16- or 32-bit)
  • Page 258 High-Level Data Link Control (HDLC) Short-Frame Counter: The HxSFCNT and HxSFCNTP registers indicate the total number of short frames received. The HxSFCNT register clears when read; HxSFCNTP does not. This count also includes all very short frames. If the counter rolls over, it generates a maskable interrupt.
  • Page 259 High-Level Data Link Control (HDLC) is independent of the threshold selected. The receiver can optionally generate a data- ready interrupt as well. Receive End-of-Frame: For programmed I/O, the REOF bit of the HxISTAT0 register indicates when any status bytes (that is, an end-of-frame) are present in the FIFO. This indication is independent of the threshold selected.

  • Page 260: Hdlc And Smartdma

    High-Level Data Link Control (HDLC) multiplexed bus is allocated to a single TSA/HDLC channel. To enable Transparent mode, set the TRANSM bit of the HxCON register to 1. Figure 15-8 shows the assertion and deassertion of RTR with back-to-back flags. A real frame would contain additional data between the two flags.

  • Page 261: Hdlc Receiver

    High-Level Data Link Control (HDLC) 4. Finally, set the SmartDMA TXST and POLL bits to restart the DMA and poll the current descriptor. If step 3 was executed to back the DMA to the start of the packet, or if the DMA was already at the start of the packet (e.g., if CTS was lost during transmission of the first buffer in the packet), then the packet is resent.

  • Page 262: Interrupts

    High-Level Data Link Control (HDLC) 15.5.7 Interrupts All interrupts are individually maskable. Set the status bits in the HxISTAT0 and HxISTAT1 registers. Mask interrupts in the HxIMSK0 and HxIMSK1 registers. 15.5.7.1 Transmit Interrupts The microcontroller provides the following transmit interrupts: Transmit threshold reached Data byte available Abort sent...

  • Page 263: Software-Related Considerations

    High-Level Data Link Control (HDLC) The receiver sets the One Receive Data Byte Available (RDATA1) bit in the HDLC Channel Interrupt Status 0 (HxISTAT) register when the current byte available is data; the RDATA1 bit does not reflect the entire FIFO contents. If the next byte is status and the following byte is data, the receiver does not set RDATA1.
  • Page 264 High-Level Data Link Control (HDLC) 15-22 Am186™CC/CH/CU Microcontrollers User’s Manual...

  • Page 265: Chapter 16 Hdlc External Serial Interface Configuration (Tsas)

    CHAPTER HDLC EXTERNAL SERIAL INTERFACE CONFIGURATION (TSAS) Note: Only the Am186CC and Am186CH microcontrollers support the TSAs. 16.1 OVERVIEW Time Slot Assigners (TSAs) and muxing logic between the HDLC channels and the external communications interfaces of the chip provide flexible data path control on the Am186CC and Am186CH microcontrollers.
  • Page 266 HDLC External Serial Interface Configuration (TSAs) In the Am186CC microcontroller, Time Slot selection also supports isolation of GCI B and D channels on separate HDLC channels. Each TSA channel can support a burst data rate to or from the HDLC of up to 768 Kbit/s in GCI mode. The TSA controllers also generate control signals for programmable frame sync pulse polarity and individual channel time slot control output, which is asserted for the duration of the programmed time slot(s).

  • Page 267: Block Diagrams

    HDLC External Serial Interface Configuration (TSAs) 16.2 BLOCK DIAGRAMS Figure 16-1 and Figure 16-2 show simplified block diagrams for the TSA muxing. Figure 16-3 shows a block diagram for a single HDLC channel, including connections with the TSA and GCI. Figure 16-1 Block Diagram For TSA Multiplexing (Am186CC Communications Controller) RTR, CTS...
  • Page 268 HDLC Control/Status Internal RTR Receiver Time Clock Receive CLK (A, B, C, D) receive data Control receive clock Transmit CLK (A, B, C, D) transmit clock 32 x 8 FIFO transmit data Receive DATA (A, B, C, D) Data Mux Transmit DATA (A, B, C, D) Interface Control...

  • Page 269: System Design

    HDLC External Serial Interface Configuration (TSAs) 16.3 SYSTEM DESIGN lists the signals that are multiplexed with other microcontroller functions. Pinstraps are sampled only at external reset and do not affect the pin’s other functions, so they are not shown in this table. Other multiplexed signals, when enabled, either disable or alter any other functions that use the same pin.
  • Page 270 HDLC External Serial Interface Configuration (TSAs) Table 16-1 HDLC/TSA/GCI Multiplexed Signals (Same as Table 15-1) (Continued) Multiplexed Signals Default External Interface Function Signal PIOs UART DCE_RXD_B PCM_RXD_B — — PIO36 DCE and PCM data input pin PIO36 DCE_TXD_B PCM_TXD_B — —...

  • Page 271: Registers

    HDLC External Serial Interface Configuration (TSAs) 16.4 REGISTERS Table 16-2 lists the three unique registers that program each individual TSA. The x shown in the register name is A, B, C, or D, depending on the channel selected. The offset shown is for Channel A;...

  • Page 272: Programmable Time Slots

    HDLC External Serial Interface Configuration (TSAs) 4. To establish byte alignment in transparent mode, additional configuration is necessary as follows: a. Enable transmit FIFO (TFIFOEN bit), force abort (FORABR bit), and transmit enable (HTEN bit) of the HxTCON0 register for each specific HDLC channel. b.
  • Page 273 HDLC External Serial Interface Configuration (TSAs) Figure 16-5 on page 16-10 demonstrates the muxing logic for an ISDN basic-rate GCI interface. The muxes at each stage level have been removed for clarity. In their place is the end data path established after proper mux initialization. This figure illustrates the following: 1.

  • Page 274: Figure 16-5 Isdn Basic-Rate Gci Application (Am186Cc Communications Controller)

    HDLC External Serial Interface Configuration (TSAs) Figure 16-5 ISDN Basic-Rate GCI Application (Am186CC Communications Controller) Time C/I1, D,C/I0, Mon0 MR,MX IC2 Mon1 MR,MX Stage 1 (10xxxxxx) Stage 2 D (2 bits: 10) Stage 3 Stage 3 Stage 2 Stage 1 D-channel traffic External Interface A...

  • Page 275: External Interfaces

    HDLC External Serial Interface Configuration (TSAs) 16.5.4 External Interfaces As mentioned previously, the Am186CC and Am186CH microcontrollers’ external data streams can take the following forms: raw DCE and PCM Highway. When connecting directly to an individual HDLC, raw DCE format is available. When HDLC data passes through a TSA, the PCM Highway interface is available.
  • Page 276 – AT&T T75xx family – TI/Intel 291x family Targets the following external ISDN transceivers (ISDN requires three channels): – AMD Am79C30A/32A S/T – Lucent T7237 U Note: The Am186CC microcontroller does not provide the PCM codec master clocks for GCI applications.

  • Page 277: Figure 16-6 Programmable Frame Sync

    HDLC External Serial Interface Configuration (TSAs) Figure 16-6 Programmable Frame Sync Frame Sync Programmed for Channel B1 GCI B1 Channel GCI B2 Channel Frame Sync Programmed for Channel B2 GCI B1 Channel GCI B2 Channel Figure 16-7 Converted GCI Clock and Frame Sync Solid Line Illustrates Frame Sync’s Minimum Setup and Hold Times (with respect to DCL) Don’t care for codec...

  • Page 278: Software-Related Considerations

    (mark idle) previous to the actual data stream is corrupted, which could falsely indicate the start of actual data. This only applies when using Transparent mode. 16.5.6 Comparison to Other Devices The Am186CC and Am186CH microcontrollers are similar to the AMD Am79C30 in clock slave mode. 16.6 INITIALIZATION...

  • Page 279: Chapter 17 General Circuit Interface (Gci)

    PCM Highway and GCI interfaces to the other three HDLC channels. See Chapter 15, “High-Level Data Link Control (HDLC)” and Chapter 16, “HDLC External Serial Interface Configuration (TSAs)” for more information. Full documentation on GCI/IOM-2 is available in the AMD IOM-2 Interface Reference Guide , order #12576. 17.2 BLOCK DIAGRAM Figure 17-1 shows the block diagram for a single HDLC channel, including connections with the TSA and GCI.
  • Page 280 HDLC Control/Status Internal RTR Receiver Time Clock Receive CLK (A, B, C, D) receive data Control receive clock Transmit CLK (A, B, C, D) transmit clock 32 x 8 FIFO transmit data Receive DATA (A, B, C, D) Data Mux Transmit DATA (A, B, C, D) Interface Control...

  • Page 281: System Design

    General Circuit Interface (GCI) 17.3 SYSTEM DESIGN Table 17-1 lists the HDLC/TSA/GCI signals that are multiplexed with other Am186CC microcontroller functions. Pinstraps are sampled only at external reset and do not affect the pin’s other functions, so they are not shown in this table. Other multiplexed signals, when enabled, either disable or alter any other functions that use the same pin.
  • Page 282 General Circuit Interface (GCI) Table 17-1 HDLC/TSA/GCI Multiplexed Signals (Same as Table 15-1) (Continued) Multiplexed Signals Default External Interface Function Signal PIOs UART DCE_RXD_B PCM_RXD_B — — PIO36 DCE and PCM data input pin PIO36 DCE_TXD_B PCM_TXD_B — — PIO37 DCE and PCM data output pin PIO37 DCE receive clock/PCM DCE_RCLK_B PCM_CLK_B...

  • Page 283: Registers

    General Circuit Interface (GCI) 17.4 REGISTERS The registers listed in Table 17-2 program the GCI. Appendix A summarizes the bits in all the registers. For a complete description of all the peripheral registers, see the Am186™CC/CH/CU Microcontrollers Register Set Manual , order #21916. Table 17-2 GCI Register Summary Register...

  • Page 284: Transmitting Data

    General Circuit Interface (GCI) 17.5.1.1 Transmitting Data 1. Configure the HDLC channels and time slot assigners to transmit the data. For details, see Chapter 15, “High-Level Data Link Control (HDLC),” and Chapter 16, “HDLC External Serial Interface Configuration (TSAs).” 2. Configure and activate the GCI channels: a.

  • Page 285: Receiving Data

    General Circuit Interface (GCI) MEOMRQ bit being set, the GCI controller deactivates the outgoing MX bits in response to incoming MR bits going inactive, and leaves them inactive. 17.5.1.2 Receiving Data 1. Configure the HDLC channels and time slot assigners to receive the data. For details, see Chapter 15, “High-Level Data Link Control (HDLC),”...

  • Page 286: Gci Structure: Channels And Frames

    “GCI-to-PCM Converted Pin Interface” on page 17-14). This second interface allows an external PCM codec to multiplex directly onto a GCI terminal frame B channel. For more information, see the AMD IOM-2 Interface Reference Guide , order #12576. Figure 17-3...

  • Page 287: Gci Bus

    The activation/deactivation procedure is a combination of software handshakes through the C/I channel, and hardware indications through the clock and data lines. The AMD IOM-2 Interface Reference Guide , order #12576, describes both the hardware and the software protocols in detail.

  • Page 288: Figure 17-4 Bus Activation/Deactivation

    General Circuit Interface (GCI) Figure 17-4 Bus Activation/Deactivation Idle Activation Downstream (clocks off) (DU = Z) Software sets (DD = Z) Activation bit; Deactivation DU output forced Low DU output forced to Z DD output forced to Z (DU = 0) Activation Upstream (clocks off) Clock (DCL) received...

  • Page 289: Gci Bus Reversal

    General Circuit Interface (GCI) reception as soon as DCL appears; no intervention from the controller is required. However, the microcontroller must respond to the interrupt and perform the normal C/I channel software handshakes before activation completes. 17.5.4.2 GCI Bus Reversal In Terminal mode, a device may be required to transmit both upstream and downstream, based on which GCI channel is being transmitted at any one time.

  • Page 290: Figure 17-5 Downstream Versus Upstream

    General Circuit Interface (GCI) Figure 17-5 Downstream Versus Upstream GCI codec downstream, Example 1: Am 186CC microcontroller Example 2: downstream, 186CC microcontroller upstream transceiver upstream Codec Am186CC Am186CC Transceiver GCI_DU_A GCI_DU_A Controller Controller GCI_FSC_A Downstream Upstream Downstream Upstream GCI_DD_A GCI_DD_A Device Device Device...

  • Page 291: Gci Interface Signals

    General Circuit Interface (GCI) Figure 17-7 GCI With Bus Reversal Disabled Transceiver B1,B2,D,MON0,C/I0,IC1,IC2, MON1,C/I1,E(in),S/G(in), BAC(out), TBA2-0(out) Am186CC Downstream Downstream Notes: E, S/G, BAC, and TBA2–TBA0 are bits on the TIC bus. 17.5.5 GCI Interface Signals 17.5.5.1 Four-Pin Interface The GCI terminal mode interface consists of a four-pin subset of the seven-pin GCI industry standard serial bus.

  • Page 292: Gci-To-Pcm Converted Pin Interface

    (the MCHSEL bit in the GPCON register designates which monitor channel is selected). For a detailed description of the monitor channel handshake procedure, see the AMD IOM-2 Interface Reference Guide , order #12576.

  • Page 293: C/I Channel Operation

    C/I channel can be thought of as a set of static status lines that only change when the status changes. For a list of C/I codes (for GCI Subframe 0 only), and further C/I channel operation, refer to the AMD IOM-2 Interface Reference Guide , order #12576. Am186™CC/CH/CU Microcontrollers User’s Manual...

  • Page 294: Tic Bus Support

    General Circuit Interface (GCI) 17.5.7.5 TIC Bus Support The meaning of each bit within the TIC bus is dependent on whether the Am186CC microcontroller is transmitting or receiving on the TIC bus. Table 17-5 lists and describes the TIC bus bits. Table 17-5 TIC Bus Bits Bit Name...
  • Page 295 General Circuit Interface (GCI) An Am186CC microcontroller access request can either be generated by software (microprocessor access to C/I Channel 0) or by the HDLC controller itself (transmission of an HDLC frame—signified internally by a signal, originating from the GCI TIC bus controller, whose function is similar to an external RTS assertion).
  • Page 296 General Circuit Interface (GCI) In the case where the S/G bit is 1, only the D-channel data is prevented from being switched through the GCI bus (i.e., the C/I0 channel could request access to this already established TIC bus and transmit its information). The TIC bus request remains unaffected (for example, if the microcontroller has earned the right to the GCI TIC bus it does not give up this bus and keeps BAC and the TIC address active while waiting for GO).

  • Page 297: Ic Channel Operation

    General Circuit Interface (GCI) bus by setting all remaining TIC bus address bits to 1. (This assures that the lowest address has priority. If the remaining bits are not immediately set to 1, addresses such as 101 and 011 would have equal priority.) If a bit is overwritten and an address mismatch occurs, the TIC bus controller returns to step 2.

  • Page 298: Software-Related Considerations

    Channel A Configuration (TSACON) register. This is necessary regardless of whether TSA Channel A is being used. 17.5.10 Comparison to Other Devices The Am186CC microcontroller’s GCI interface is similar to the AMD Am79C30 in clock slave mode. 17.6 INITIALIZATION On external and internal reset, the following occurs: The TSAs default to non-GCI mode.

  • Page 299: Chapter 18 Universal Serial Bus (Usb)

    CHAPTER UNIVERSAL SERIAL BUS (USB) Note: Only the Am186CC and Am186CU microcontrollers support USB. 18.1 OVERVIEW The Universal Serial Bus (USB) is an industry-standard bus architecture for computer peripheral attachment. The USB provides a single interface for easy, plug-and-play, hot- plug attachment of peripherals such as a keyboard, mouse, speakers, printers, scanners, and communication devices.

  • Page 300: Block Diagram

    Universal Serial Bus (USB) The Am186CC microcontroller also supports isochronous transfers from one of the integrated HDLC channels. The USB peripheral controller also includes robust error detection and management features so the device software can manage transfers in any number of ways as required by the application.

  • Page 301: Usb Transceiver Interface

    Universal Serial Bus (USB) Table 18-1 USB Multiplexed Signals Multiplexed Default Signal Function Signal(s) Signal Internal USB Transceiver I/O Pins USBD+ Internal USB transceiver differential input/output UDPLS USBD+ USBD– Internal USB transceiver differential input/output UDMNS USBD– External USB Transceiver I/O Pins UDMNS Status input from external transceiver USBD–...

  • Page 302: Figure 18-2 Usb With Internal Transceiver

    Universal Serial Bus (USB) 1.5 K-Ω pull up on USBD+ when V is removed. The following system design issues should be resolved to provide a robust self-powered USB device application: On Connect: Monitor V to identify a powered USB host/hub. Enable the 1.5 K-Ω...

  • Page 303: Usb Clock Source

    Universal Serial Bus (USB) Figure 18-3 USB With External Transceiver PIO_USB_DETECT PIO_USB_VCC Am186CC/CU Microcontroller USB Type “B” 1.5 K-Ω USBD– UTXDMNS[RSVRD_102] USBD+ UTXDPLS[RSVRD_101] UXVOE[RSVRD_103] UXVRCV[RSVRD_104] UDMNS[USBD–] UDPLS[USBD+] Note: The USB specification requires a driver impedance between 29 Ω and 44 Ω on the USBD+ and USBD–...

  • Page 304: Isochronous Synchronization Signals

    Universal Serial Bus (USB) primary system clock must be a minimum of 24 MHz when using the USB peripheral controller . To select the dedicated USB clock source, assert either the USBSEL2 or USBSEL1 pinstrap during reset (power-on or assertion of RES). These pinstraps select either 4x or 2x PLL operation, allowing the use of a 12-MHz or 24-MHz crystal, respectively, as the USB clock input on pins USBX1 and USBX2.

  • Page 305: Registers

    Universal Serial Bus (USB) Each USB data endpoint can only be connected to a single specific SmartDMA channel, but can be connected to any general-purpose DMA channel. Because SmartDMA channels are directional (either transmit or receive), a general-purpose DMA channel must be used if more than 2 IN data endpoints or more than 2 OUT data endpoints are desired.
  • Page 306 Universal Serial Bus (USB) Table 18-3 USB Register Summary (Continued) Register Offset Register Name Description Mnemonic USB Control Endpoint Registers Contains control and status bits for the Control 200h CNTCTL Control Endpoint Control/Status endpoint (endpoint 0). Shows the size of the packet present in the 202h CNTSIZ Control Endpoint Receive Packet Size...
  • Page 307 Universal Serial Bus (USB) Table 18-3 USB Register Summary (Continued) Register Offset Register Name Description Mnemonic Used to set the endpoint’s FIFO size and 22Ch AEPDEF2 A Endpoint Definition 2 maximum packet size. Used to set auto-rate enable, status interrupt 22Eh AEPDEF3 A Endpoint Definition 3...

  • Page 308: Operation

    Universal Serial Bus (USB) 18.5 OPERATION The Am186CC and Am186CU microcontrollers act as USB peripheral devices. The USB is a half-duplex, master/slave, polled bus. In other words, the microcontroller only transmits on the USB in response to a request from the USB host, usually a personal computer. There can be only one transmitter on the USB at a time.

  • Page 309: Programming The Control Endpoint

    Universal Serial Bus (USB) 18.5.1.2 Programming the Control Endpoint The host uses the USB peripheral controller’s dedicated control endpoint for detection and control of the device. The endpoint contains an 8-byte FIFO for storage of commands, command data (for host command writes), and responses (for host command reads). The maximum packet size of the control endpoint is always eight bytes, the physical size of the FIFO.

  • Page 310: Programming Data Endpoints

    Universal Serial Bus (USB) The host polls the interrupt endpoint once every 1 to 255 ms. Device software requests a poll rate when it sets up the endpoint’s descriptor data structure, which the host obtains by issuing a GET_DESCRIPTOR command during device configuration. Note that the interrupt endpoint can only be used in non-DMA mode.
  • Page 311 Universal Serial Bus (USB) The following registers configure a data endpoint in response to commands received from the USB host. For details on any of these registers, see the Am186™CC/CH/CU Microcontrollers Register Set Manual , order #21916. Endpoint Definition 1 (xEPDEF1): –...
  • Page 312 Universal Serial Bus (USB) Endpoint Control/Status (xEPCTL): This register controls various aspects of the data endpoint. Because the data endpoint is flexible in terms of the endpoint type, direction, and mode, besides other programmable features, use of this register is discussed in the following specific application scenarios. 18.5.1.4.1 Endpoint A Configured as Bulk OUT, Non-DMA Mode 1.
  • Page 313 Universal Serial Bus (USB) 5. Device software can clear the NOT_FLUSH bit in the AEPCTL register if it needs to update stale data in the FIFO before the data is transmitted. This causes the USB hardware to return control to software by setting the ACT_REQ bit. However, the ACT_REQ bit is set only if there is no active data transfer from this endpoint to the host.

  • Page 314: Data Transmission And Data Types

    Universal Serial Bus (USB) stop the hardware, requiring device software to take appropriate action and then clear the ACT_REQ bit to let the hardware continue. – Perform any additional programming of the definition registers that is required for the specific application. 2.

  • Page 315: Usb Reset

    Universal Serial Bus (USB) 18.5.2.2 USB Reset Hardware sets the USB_RST bit in the UISTAT2 register when a USB reset signal is detected on the USB bus. The USB_RST bit can be enabled as an interrupt source by setting the corresponding bit in the UIMASK2 register.

  • Page 316: Handling Usb Data

    Universal Serial Bus (USB) For the USB control endpoint, the system software is responsible for decoding and servicing several of the USB standard commands and all device class or vendor specific commands. Hardware is provided that allows the system software to detect incoming commands, and respond appropriately.

  • Page 317: Interrupt-Driven I/O

    Universal Serial Bus (USB) For a transmit endpoint (IN direction), the ACT_REQ bit is set if the FIFO is ready to be filled with data. If this bit is set, software can fill the FIFO when it has data for that endpoint to transmit, then it must clear the ACT_REQ bit to release the FIFO.

  • Page 318: Dma/Fifo Interaction

    Universal Serial Bus (USB) automatically between the endpoint’s FIFO and memory (or I/O), possibly using even less overhead than general-purpose DMA. Software interaction is still required to handle FIFO and USB packet errors. Table 18-4 USB Endpoints Used with DMA USB Endpoint DMA Channel USB data Endpoint (A–D) configured in either direction...

  • Page 319: Setting Up Dma For Usb

    Universal Serial Bus (USB) endpoint is configured to use a Smart DMA channel, information in the FIFO descriptor indicates if a byte is the last byte or a null byte. 18.5.6.3 Setting Up DMA for USB The USB peripheral controller gives the programmer a large degree of freedom in using DMA with USB endpoints.

  • Page 320: Error Recovery On Bulk And Interrupt Endpoints

    Universal Serial Bus (USB) 18.5.6.5 Error Recovery on Bulk and Interrupt Endpoints When an endpoint is configured as a bulk or interrupt endpoint, data delivered over the endpoint is guaranteed to be correct, but is not guaranteed to be delivered within any certain time interval.

  • Page 321: Isochronous Transfer Synchronization

    Universal Serial Bus (USB) 18.5.6.6 Error Recovery on Isochronous Endpoints Isochronous data, by definition, is very time-sensitive. Neither PCM highway nor USB have any mechanism or concept of retransmission of isochronous data. Nevertheless, there are error-recovery issues with isochronous data. For the intended audio applications, these primarily revolve around making sure that FIFO pointers do not overlap or drift too far apart.

  • Page 322: Isochronous Transfer Features

    Universal Serial Bus (USB) Isochronous synchronization involves converting the data stream from its sample rate (for example, the 44.1-KHz rate of an audio CD player) into packets delivered at the fixed USB start-of-frame (SOF) rate of 1 KHz (1000 frames per second). The USB specification defines three types of isochronous synchronization: Asynchronous: The data sample clock and the USB frame rate are independent of each other.
  • Page 323 Universal Serial Bus (USB) The SOF is also reflected on the controller’s USBSOF output signal, which is used in the first method (lock the sample clock) of synchronous isochronous synchronization, as described in “Isochronous Transfer Synchronization” on page 18-23. If a missing SOF is detected, the USB peripheral controller automatically generates an internal SOF, which is reflected by the SOF_GEN bit and the USBSOF signal.

  • Page 324: Command Handling

    Universal Serial Bus (USB) The specified number of bytes is transferred on each sample clock as long as data is present in the endpoint’s FIFO, or is sequentially written to the FIFO as needed during the transaction. Start of Frame and Frame Number Monitoring: The USB peripheral controller monitors the USB SOF packet and latches the frame number value into the Time Stamp (TSTMP) register upon successfully receiving the SOF packet from the USB host.

  • Page 325: Controller Hardware

    Universal Serial Bus (USB) Table 18-5 USB Commands Handled by Device Software Parameters and Data Command Results Data Passed Direction The device software, upon detecting this command, should return all of the data associated Device, Configuration, with the particular descriptor that was requested. GET_DESCRIPTOR or String Descriptor Because this controller allows the endpoint...

  • Page 326: Command Protocol

    Universal Serial Bus (USB) Table 18-6 USB Commands Handled by USB Peripheral Controller Hardware Parameters and Data Command Results Data Passed Direction Device stores the address assigned to it by the SET_ADDRESS Device’s USB address USB host. The device’s remote wake up feature is enabled (or) Device Remote Wake-up, A particular endpoint is forced to be stalled.

  • Page 327: Data Transfer Using The Control Endpoint

    Universal Serial Bus (USB) software clears the ACT_REQ bit when it has filled the FIFO with information to go to the host, and hardware sets the ACT_REQ bit after the information has safely made it to the host. The host can send a new command at any time, so the NEW_COMMAND bit provides a somewhat less “polite”...

  • Page 328: Data Transfer With The Interrupt Endpoint

    Universal Serial Bus (USB) 18.5.11.1 USB Command Processing and the Interrupt Endpoint When a SET_CONFIGURATION or SET_INTERFACE command is received, software must reprogram the Interrupt Endpoint Definition registers (if necessary) to reflect the new configuration and alternate interface setting. Also, the descriptor relating to the interrupt endpoint (which is returned to a host GET_DESCRIPTOR request) must contain the correct maximum packet size (8 or 16 bytes) and Interval value (1-ms to 255-ms interrupt rate).

  • Page 329: Interrupt Endpoint Definition

    Universal Serial Bus (USB) Table 18-7 Control Endpoint Definition Parameter Value USB Parameters Number Configuration Interface Alternate Setting Type Control Maximum Packet Size Eight bytes System Parameters Data Handling Polled I/O or interrupt driven FIFO Depth Eight bytes 18.5.12.2 Interrupt Endpoint Definition The Am186CC and Am186CU microcontrollers each provide one dedicated interrupt endpoint.

  • Page 330: Data Endpoint Definition

    Universal Serial Bus (USB) 18.5.12.3 Data Endpoint Definition The Am186CC and Am186CU microcontrollers each provide four general-purpose data endpoints. These endpoints transfer large amounts of data between the USB host and device using either the USB bulk, isochronous, or interrupt transfer protocols. Note that if the data endpoint is programmed for interrupt transfer, the DMA mode is not applicable.

  • Page 331: Software-Related Considerations

    Universal Serial Bus (USB) 18.5.13 Software-Related Considerations A data endpoint must be configured with the xEPDEFx register before enabling it with the EP_EN bit in the xEPCTL register. When the MODE bit field in the xEPDEF3 register is set to 101b (SmartDMA channel, status stored in the buffer descriptor), a bulk OUT transfer that results in a retransmission of data by the host due to handshake packet errors produces the following buffer descriptor field values: STP = 1, ENP = 1, and CRC = 1.
  • Page 332 Universal Serial Bus (USB) 18-34 Am186™CC/CH/CU Microcontrollers User’s Manual...
  • Page 333 APPENDIX REGISTER SUMMARY Table A-1 on page A-2 provides a summary of all the Am186CC/CH/CU microcontrollers’ peripheral control block (PCB) registers, listed in offset order. The table includes the following information for each register: Abbreviated name Register description page number Relative offset from the PCB base (set in RELOC) Default location in I/O space (equal to the default PCB base of FC00h plus the register’s relative offset)

  • Page 334: Table A-1 Am186Cc/Ch/Cu Microcontrollers Register Summary

    Table A-1 Am186CC/CH/CU Microcontrollers Register Summary DEFAULT DEFAULT NAME OFFSET LOCATION VALUE CC CH HDLC Channel A Registers HACON FC00h 0000h HRESET NRZI TRANSM LOOPR LOOPL CRCTYPE HATCON0 FC02h 0000h TTHRSH TFIFOEN FORABR HTEN IMSTART CRCDIS LBREAD LBNOW HATCON1 FC04h 0000h FLAGIDL MLTDRP...
  • Page 335 Table A-1 Am186CC/CH/CU Microcontrollers Register Summary (Continued) DEFAULT DEFAULT NAME OFFSET LOCATION VALUE CC CH HDLC Channel B Registers HBCON FC40h 0000h HRESET NRZI TRANSM LOOPR LOOPL CRCTYPE HBTCON0 FC42h 0000h TTHRSH TFIFOEN FORABR HTEN IMSTART CRCDIS LBREAD LBNOW HBTCON1 FC44h 0000h FLAGIDL...
  • Page 336 Table A-1 Am186CC/CH/CU Microcontrollers Register Summary (Continued) DEFAULT DEFAULT NAME OFFSET LOCATION VALUE HDLC Channel C Registers HCCON FC80h 0000h HRESET NRZI TRANSM LOOPR LOOPL CRCTYPE HCTCON0 FC82h 0000h TTHRSH TFIFOEN FORABR HTEN IMSTART CRCDIS LBREAD LBNOW HCTCON1 FC84h 0000h FLAGIDL MLTDRP AUTOCTS...
  • Page 337 Table A-1 Am186CC/CH/CU Microcontrollers Register Summary (Continued) DEFAULT DEFAULT NAME OFFSET LOCATION VALUE HDLC Channel D Registers HDCON FCC0h 0000h HRESET NRZI TRANSM LOOPR LOOPL CRCTYPE HDTCON0 FCC2h 0000h TTHRSH TFIFOEN FORABR HTEN IMSTART CRCDIS LBREAD LBNOW HDTCON1 FCC4h 0000h FLAGIDL MLTDRP AUTOCTS...
  • Page 338 Table A-1 Am186CC/CH/CU Microcontrollers Register Summary (Continued) DEFAULT DEFAULT NAME OFFSET LOCATION VALUE General-Purpose DMA Channel 0 Registers GD0CON0 100h FD00h 0000h DSEL ! GD0CON1 102h FD02h 0000h SM/IO SINC DM/IO DINC GD0SRCL 104h FD04h 0000h DSA[15–0] GD0SRCH 106h FD06h 0000h DSA[19–16] GD0DSTL...
  • Page 339 Table A-1 Am186CC/CH/CU Microcontrollers Register Summary (Continued) DEFAULT DEFAULT NAME OFFSET LOCATION VALUE GD3TC 13Ch FD3Ch 0000h CC CH SmartDMA Channel Pair 0 Registers SD0CON 140h FD40h 0000h TEPI TBUI TTCI REPI RBUI RTCI TXSO RXSO POLL TXST RXST SD0TRCAL 142h FD42h 0000h...
  • Page 340 Table A-1 Am186CC/CH/CU Microcontrollers Register Summary (Continued) DEFAULT DEFAULT NAME OFFSET LOCATION VALUE SD2CRAD 180h FD80h 0000h CRAD CC CU SmartDMA Channel Pair 3 Registers SD3CON 188h FD88h 0000h TEPI TBUI TTCI REPI RBUI RTCI TXSO RXSO POLL DSEL ! TXST RXST SD3TRCAL 18Ah...
  • Page 341 Table A-1 Am186CC/CH/CU Microcontrollers Register Summary (Continued) DEFAULT DEFAULT NAME OFFSET LOCATION VALUE CC CU USB Interrupt Endpoint Registers EP_NOT_ NOT_ ACT_ IEPCTL 210h FE10h 0000h EP_EN STALLED FLUSH IEPDAT 216h FE16h 00xxh IEPDEF1 21Ah FE1Ah 1003h EP_NUM EP_CFG EP_INT EP_ASET EP_DIR EP_TYPE...
  • Page 342 Table A-1 Am186CC/CH/CU Microcontrollers Register Summary (Continued) DEFAULT DEFAULT NAME OFFSET LOCATION VALUE CC CU USB Data C Endpoint Registers FULL SHORT OTHER CEPCTL 240h FE40h 0000h STAT LAST STALLED FLUSH ZERO START STOP BYTE CEPSIZ 242h FE42h 0000h CEPBUFS 244h FE44h 0000h...
  • Page 343 Table A-1 Am186CC/CH/CU Microcontrollers Register Summary (Continued) DEFAULT DEFAULT NAME OFFSET LOCATION VALUE High-Speed Asynchronous Serial Port (High-Speed UART) Registers HSPCON0 260h FE60h 0000h RSIE TXIE RXIE TMODE RMODE ABEN STP2 HSPCON1 262h FE62h 0000h TFEN RFEN TFLUSH RFLUSH ABAUD MAB2 MAB1 MAB0...
  • Page 344 Table A-1 Am186CC/CH/CU Microcontrollers Register Summary (Continued) DEFAULT DEFAULT NAME OFFSET LOCATION VALUE General Circuit Interface (GCI) Registers GPCON 2A0h FEA0h 0000h PCMFSC MCARV MARQ MCHEN MCHSEL MEOMRQ ICSEL GCIACT BRDIS 0002h GISTAT 2A2h FEA2h DCLST CHGCI1 CHGCI0 MRAD MTARD MEOMRD MXBA MRDA...
  • Page 345 Table A-1 Am186CC/CH/CU Microcontrollers Register Summary (Continued) DEFAULT DEFAULT NAME OFFSET LOCATION VALUE Time Slot Assigner (TSA) Channel D Registers TSDCON 2D8h FED8h 0000h MODE ! FSCP DRVLVL ESADJ TSDSTART 2DAh FEDAh 0000h BPSTART TSDSTOP 2DCh FEDCh 0000h BPSTOP Synchronous Serial Interface (SSI) Registers SSSTAT 2F0h FEF0h...
  • Page 346 Table A-1 Am186CC/CH/CU Microcontrollers Register Summary (Continued) DEFAULT DEFAULT NAME OFFSET LOCATION VALUE INSERV 32Ah FF2Ah 0000h CH14 CH13 CH12 CH11 CH10 REQST 32Ch FF2Ch 0000h CH14 CH13 CH12 CH11 CH10 INTSTS 32Eh FF2Eh 0000h DMA3 DMA2 DMA1 DMA0 TIM2 TIM1 TIM0 DMAHLT...
  • Page 347 Table A-1 Am186CC/CH/CU Microcontrollers Register Summary (Continued) DEFAULT DEFAULT NAME OFFSET LOCATION VALUE Programmable I/O (PIO) Registers PMODE PMODE PMODE PMODE PMODE PMODE PMODE PMODE PMODE PMODE PMODE PMODE PMODE PMODE PMODE PMODE PIOMODE0 3C0h FFC0h 0000h PIODIR0 3C2h FFC2h 1EFFh PDIR15 PDIR14...
  • Page 348 Register Summary A-16 Am186™CC/CH/CU Microcontrollers User’s Manual...
  • Page 349 GLOSSARY break During serial communications, a constant Low signal on A bus the receive data line for one frame time or greater. In the Nonmultiplexed address bus. Am186CC/CH/CU microcontrollers, this is reported as a zero character with the framing error (FER) and break (BRK) status bits set in the (H)SPSTAT register.
  • Page 350 Glossary back to the beginning of the buffer and continues writing data transparency or reading data. Sometimes called a ring buffer. Com- A data stream that happens to contain a data sequence pare to buffer queue. that is the same as a flag, mark, or abort sequence is disguised during transmission so it is not misconstrued as an actual flag, mark, or abort.
  • Page 351 Glossary DRAM external reset Dynamic random access memory. A type of computer The reset of the Am186CC/CH/CU microcontrollers ini- memory that employs a system of transistors and tiated by asserting the RES signal. Also called a power- on reset. Compare to internal reset and system reset. capacitors to retain data.
  • Page 352 Glossary General circuit interface, also called IOM-2. One of the In-circuit emulator. A device for testing and program- external interfaces supported by the Am186CC commu- ming an integrated circuit outside of any actual system nications controller HDLC channels. GCI is an interface in which the device will be used.
  • Page 353 Glossary interrupt transfer One of four USB transfer types. Interrupt transfers have LANCE the following characteristics: small data, nonperiodic, Local area network controller for ethernet. low frequency, and bounded latency. They are device- initiated communications typically used to notify the LAP-B host of device service needs.
  • Page 354 Glossary mation (source, destination address, length), the data to be transmitted, and error detection and correction bits. NACK A packet may be made up of one or more frames. Negative acknowledgment. packet buffer nibble The logical buffer used by a USB device for sending or Half a byte (four bits).
  • Page 355 Glossary more information about setting the FLAGS register, see Refers to a physical wire on a chip which is available the Am186™CC/CH/CU Microcontrollers Register Set externally. Compare to signal. Manual , order #21916. If the programmable priority lev- els are equal, the overall priority number is used. pinstrap A pinstrap is used to enable or disable features based on the state of the pin during an external reset.
  • Page 356 SmartDMA™ channel the next piece of information is available from the trans- An AMD proprietary technique for increasing the perfor- mitter. In DMA operations, a synchronized transfer mance of DMA transfers. SmartDMA channels provide...
  • Page 357 Glossary trace interrupt The trace interrupt is the highest priority interrupt. It is a UART software interrupt in that it is initiated by software, but Universal asynchronous receiver/transmitter. A device unlike other software interrupts, it does clears the IF that provides full-duplex, bidirectional data transfer in flag.
  • Page 358 Glossary very short frame During an HDLC transfer, a frame containing less than two bytes (zero or one) between the start and stop flags. wait state A pause in a microprocessor’s clock cycles that allows for differences in speed between one component and others in a computer (such as input/output devices or RAM).
  • Page 359 INDEX Numerics ALE signal description, 3-10 32-channel linecard application, 1-15 emulator support, 4-3 Am186CC microcontroller, block diagram, 1-5 Am186CC/CH/CC microcontroller block diagrams, 1-4 A bus, definition, Glossary-1 clocks, 3-33 DMA channel use, 8-8, 8-9 A19–A0 signals embedded CPU overview, 1-6 description, 3-10 signal description table, 3-10 emulator support, 4-2...
  • Page 360 Index BSIZE8 signal description, 3-11 basic-rate GCI, 16-10 emulator support, 4-3 baud rate buffer detection adding, 8-32, 8-34 description, 13-16 descriptor ring, creating, 8-31, 8-33 enhancement, 13-18 descriptor ring, definition, Glossary-1 error, 13-17 queues, using, 8-20 procedure, 13-7 replacing, 8-35 range, 13-17 buffer queue, definition, Glossary-1 programming, 13-15...

  • Page 361: Figure 2-1 Register Set

    Index operation, 5-4 configuration overlapping, 5-8 of maskable interrupts, 7-7 overlapping PCS with DRAM, 6-5 register, 3-4 overview, 1-12 summary, 2-4 PCS, 5-9 connect, USB, 18-3 PCS7–PCS0 signals, 5-6 control endpoint ranges and DRAM configuration, 3-10, 3-19 definition, 18-30, 18-31, Glossary-2 ready signal programming, 5-10 interrupts, 18-29 registers, 5-3...
  • Page 362 Index types, 2-8, 2-9 DEPDEF1 register, 18-9 UART DEPDEF2 register, 18-9 data overflow, 13-8 DEPDEF3 register, 18-9 description, 13-8 DEPSIZ register, 18-9 receiving, 13-7, 13-10 descriptor format, 8-38 descriptor ring control endpoint, 18-29 creating, 8-31, 8-33 interrupt endpoint, 18-30 definition, Glossary-2 transmission types, 18-16 transmit, 8-30, 8-31 data bus...
  • Page 363 Index initialization, 8-44 overlapping PCS, 6-5 interface to UART, 13-21 overview, 1-11, 3-32 latency, definition, Glossary-2 refresh, 6-5 maximum transfer rates, 8-19 refresh interval, 6-6 mode, definition, Glossary-2 refreshing, 6-1 mode, UART, 13-12 register summary, 6-3 multiplexed signals, 8-4 signal descriptions, 3-19 operation, 8-7 signal functions, 5-7 overview, 1-10...
  • Page 364 Index S6 signal, 4-5 FIFO signals used by emulators, 3-17 definition, Glossary-3 SRDY signal, 4-3, 4-5 DMA, 18-20 system design, 4-1 high-water mark, definition, Glossary-3 UCS signal, 4-5 serial communications overview, 12-7 UART, 13-11 UCSX8 signal, 4-5 usage, 4-2 UART receive, 13-12 WHB signal, 4-5 FLAGS register, 2-2, 2-3 WLB signal, 4-5...
  • Page 365 Index initialization, 17-20 interface signals, 17-13 half duplex interrupts, 17-19 definition, Glossary-4 monitor channel, 17-14 description, 12-8 operation, 17-5 handling USB data, 18-18 overview, 1-8 PCM highway conversion with ISDN, 12-5 hardware considerations receiving data, 17-7 chip select, 5-10 registers, 17-5 DRAM, 6-6 signal conversion, 17-14 emulator support, 4-5...
  • Page 366 Index HSPAB3 register, 13-4 IEPCTL register, 18-8 HSPBDV register, 13-4 IEPDAT register, 18-8 HSPCON0 register, 13-4 IEPDEF1 register, 18-8 HSPCON1 register, 13-4 IEPDEF2 register, 18-8 HSPIMSK register, 13-4 IMASK register, 7-5 HSPM0 register, 13-4 immediate operands, CPU, 2-9 HSPM1 register, 13-4 in-circuit emulator (ICE) support, 1-12 HSPM2 register, 13-4 incrementing DMA address, 8-15...
  • Page 367 Index INT0 detected overflow exception, 7-19 IOM-2 INT0 overflow detected, 7-19 See also GCI. IRET instruction, 7-10 definition, Glossary-5 latency, definition, Glossary-4 IRET instruction, 7-10 maskable ISCTL register, 18-7 block diagram, 7-15 ISDN application configuring, 7-7 basic-rate GCI, 16-10 cycle, 7-13 GCI-PCM highway conversion, 12-5 overview, 7-14 ISDN-to-ethernet, 1-14...
  • Page 368 Index operands, 2-9 operands, register and immediate, 2-9 organization and address generation, 2-5 operation refresh cycle, 6-1 chip select, 5-4 upper chip select, 4-5, 5-5 DMA, 8-7 message pipe, definition, Glossary-5 DRAM, 6-3 emulator support, 4-2 misaligned circular buffer, 8-25 GCI, 17-5 MMCS register, 5-3 HDLC, 15-7...
  • Page 369 Index PCM_TSC_B signal, 3-26 POLLST register, 7-5 PCM_TSC_C signal, 3-26 port, definition, Glossary-7 PCM_TSC_D signal, 3-27 POTS definition, Glossary-7 PCM_TXD_A signal, 3-25 linecard application, 12-4 PCM_TXD_B signal, 3-26 power PCM_TXD_C signal, 3-26 ground pins, 3-16 PCM_TXD_D signal, 3-26 power pins, 3-16 PCS I/O space, 5-9 power-on reset, definition, Glossary-7 PCS7–PCS0 signals, description, 3-18, 5-6...
  • Page 370 Index RES signal description, 3-15 RAS1–RAS0 signals emulator support, 4-4 description, 3-19 RESCON register, 3-4 emulator support, 4-3, 4-4 reserved pins, 3-16 raw DCE reset definition, Glossary-7 definition, Glossary-7 description, 16-11 definition of types, 3-9 RD signal system, 3-5 description, 3-13 USB, 18-17 emulator support, 4-4 reset configuration pins...
  • Page 371 Index SDxCBD register, 8-6, 8-7 transmit cycle, 8-35 transmit descriptor format, 8-39 SDxCON register, 8-6, 8-7 transmit flow diagram, 8-37 SDxCRAD register, 8-6, 8-7 usage, 8-31 SDxCTAD register, 8-6, 8-7 using without CPU intervention, 8-42 SDxRRAH register, 8-6, 8-7 with HDLC, 15-18 SDxRRCAL register, 8-6, 8-7 software considerations SDxSTAT register, 8-6, 8-7...
  • Page 372 Index status, UART receive, 13-10 stream pipe, definition, Glossary-8 TDM, definition, Glossary-8 suspend, USB, 18-16 terminal adapter, ISDN, overview, 1-14 synchronization terminal count, DMA, 8-14 DMA, 8-17 terminology, interrupt, 7-8 isochronous, 18-6, 18-23 TIC bus synchronization type, definition, Glossary-8 bits, 17-16 synchronized transfer, definition, Glossary-8 downstream format, 17-16 synchronous communication overview, 12-6...
  • Page 373 Index simplified block diagram, 16-3 transmitting address bit, 13-9 software considerations, 16-14 transmitting data, 13-5 time slots, 16-8 usage, 13-4 usage, 16-7 using FIFO, 13-12 with GCI, 16-14 with DMA, 8-16 worst case autobaud error, 13-17 TSTMP register, 18-7 UCLK signal, 3-15 TSTMPM register, 18-7 UCS signal TSxCON register, 16-7...
  • Page 374 Index data transfer via control endpoint, 18-29 USBSEL1 signal, 3-7 data transfer via interrupt endpoint, 18-30 USBSEL2 signal, 3-7 data transmission types, 18-16 USBSOF signal, 3-27 definition, Glossary-9 USBXCVR signal, 3-7 device, definition, Glossary-9 UTXDMNS signal, 3-27 endpoint definitions, 18-30 UTXDPLS signal, 3-28 endpoint programming, 18-12 endpoint, definition, Glossary-9...
  • Page 375 Index WLB signal description, 3-14 emulator support, 4-5 word transfers, DMA, 8-15 word, definition, Glossary-10 worst-case error, autobaud, 13-17 WR signal description, 3-14 emulator support, 4-5 X1 signal, 3-15 X2 signal, 3-15 XON/XOFF flow control, DMA receive, 8-24 zero-bit deletion, definition, Glossary-10 zero-bit insertion, definition, Glossary-10 Am186™CC/CH/CU Microcontrollers User’s Manual Index-17...
  • Page 376 Index Index-18 Am186™CC/CH/CU Microcontrollers User’s Manual...

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