Nuvoton N9H26 Series Technical Reference Manual

Arm926ej-s based 32-bit microcontroller

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N9H26 Technical Reference Manual

ARM926EJ-S Based

32-bit Microcontroller

N9H26 Series

Technical Reference Manual

The information described in this document is the exclusive intellectual property of

Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.

Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based

system design. Nuvoton assumes no responsibility for errors or omissions.

All data and specifications are subject to change without notice.

For additional information or questions, please contact: Nuvoton Technology Corporation.

www.nuvoton.com

Publication Release Date: Sept. 10, 2018

- 1 -

Revision V1.01

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Summary of Contents for Nuvoton N9H26 Series

Page 1 The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions.
Page 2: Table Of Contents
1 GENERAL DESCRIPTION................13 2 FEATURES ....................14 3 PARTS INFORMATION LIST AND PIN CONFIGURATION......19 3.1 N9H26 Series Part Number Naming Guide ............. 19 3.2 N9H26 Series Part Selection Guide ................. 20 3.3 Pin Configuration ......................21 3.3.1 N9H26 series Pin Diagram ................... 21 3.4 Pin Description ......................
Page 3 N9H26 Technical Reference Manual 5.4.2 Features ......................... 218 5.4.3 Architecture ........................218 5.4.4 2D BLT Accelerator Control Register Map ..............220 5.4.5 Register Description ..................... 222 5.4.6 2D BLT Accelerator Memory Management Unit (BLT MMU) ......... 237 5.4.7 BLT TLB Structure and BLT MMU Operation Flow ..........238 5.4.8 BLT MMU Control Registers Map ................
Page 4 N9H26 Technical Reference Manual 5.8.1 overview ......................... 368 5.8.2 Features ......................... 368 5.8.3 VPOST Controller Interface ..................368 5.8.4 VPOST Controller Block Diagram ................370 5.8.5 VPOST Controller Functional Description ..............370 5.8.6 VPOST display interface AC/DC characteristic ............372 5.8.7 VPOST Controller Control Registers Map ..............
Page 5 N9H26 Technical Reference Manual 5.14 USB Host Controller (USBH) ................612 5.14.1 Overview ........................612 5.14.2 Features ......................... 612 5.14.3 Block Diagram ....................... 613 5.14.4 Functional Descriptions ....................614 5.14.5 Register Map ......................... 616 5.14.6 Register Description ..................... 618 5.15 USB Host Controller (UHC) ................
Page 6 N9H26 Technical Reference Manual 5.20.1 Overview ........................805 5.20.2 Features ......................... 805 5.20.3 RTC Block Diagram ..................... 806 5.20.4 RTC Function Description ................... 806 5.20.5 System Power Control Flow..................808 5.20.6 RTC Register Mapping ....................812 5.20.7 Register Descriptions ....................813 5.21 I2C Synchronous Serial Interface Controller ...........
Page 7 5.31.2 Function Description ....................1012 6 ELECTRICAL CHARACTERISTICS ............1029 6.1 Absolute Maximum Ratings ................... 1029 6.2 DC Electrical Characteristics ................. 1030 6.2.1 N9H26 Series DC Electrical Characteristics ............1030 Publication Release Date: Sept. 10, 2018 - 7 - Revision V1.01...
Page 8 6.3.12 Specifications of 24-bit Delta-Sigma CODEC ............1044 6.3.13 Specification of Low Voltage Reset ................. 1045 6.3.14 Specifications of Power-on Reset (3.3V) ..............1045 6.3.15 Thermal characteristics of N9H26 series LQFP-128 Package ......1045 7 PACKAGE DIMENSIONS ................1046 7.1 LQFP 128L (14x14x1.4mm footprint 2.0mm) ............1046 7.1.1 PCB Reflow Profile Suggestion ................
Page 9 N9H26 Technical Reference Manual LIST OF FIGURES Figure 3.1-1 N9H26 Series Part Number Naming Guide ............... 19 Figure 3.3-1 N9H26xxN LQFP 128 Pin Diagram ................21 Figure 4.1-1 N9H26 Series Block Diagram ..................33 Figure 5.4-1 Architecture Diagram ....................218 Figure 5.4-2 Architecture Diagram ....................
Page 10 N9H26 Technical Reference Manual Figure 5.16-5 Descriptor Table Format ..................708 Figure 5.17-1 AIC Functional Block Diagram ................745 Figure 5.18-1 GPIO: Input/Output Port with Program Controlled Weakly Pull-High, Schmitt- Trigger Input, Drive Strength, Slew Rate(PBSCUDL0408R) ..........765 Figure 5.19-1 TIMER Block Diagram ................... 794 Figure 5.19-2 Watchdog Timer Block Diagram ................
Page 11 N9H26 Technical Reference Manual Figure 5.30-1 SDIO Controller Block Diagram ................1002 Figure 6.3-1 Typical LXT Crystal Application Circuit ..............1033 Publication Release Date: Sept. 10, 2018 - 11 - Revision V1.01...
Page 12: List Of Tables
N9H26 Technical Reference Manual LIST OF TABLES Table 5.12-1SD/SDHC/SDIO/MMC Card Pad Assignment ............485 Table 5.12-2 NAND/SM Card Pad Assignment ................485 Table 5.14-3 Parity/Redundant number of BCH algorithm ............502 Table 5.29-1 SD / SDHC / SDIO / MMC Card Pad Assignment ..........1002 Table 5.31-2 DMA Controller Block Diagram ................
Page 13: General Description
(Sound Processing Unit), ADC, DAC and AAC accelerator for saving the BOM cost in various kinds of application needs to be the best choice. The N9H26 series could also be ported under Linux OS to leverage the driver availability of emerging functionalities such as Wi-Fi, etc., maximum resolutions for N9H26 is1024x768 @ TFT LCD panel. On the other hand, the open source code environment provides the product development more flexibility and Nuvoton’s continuous optimizations in Linux provide customers with a cost-effective solution.
Page 14: Features
N9H26 Technical Reference Manual FEATURES  CPU  ARM926EJ-S 32-bit RISC CPU with 8KB I-Cache & 8KB D-Cache  CPU 240MHz is for typical operation and the speed could be up to 264MHz if function without USB Host  JTAG interface supported for development and debugging ...
Page 15 N9H26 Technical Reference Manual  Support specified window decode mode  Support quantization-table adjustment for bit-rate and quality control in encode mode  Support rotate function in encode mode  Packet Format  Support to encode interleaved YUYV format input image, output bitstream 4:2:2 and 4:2:0 format ...
Page 16 N9H26 Technical Reference Manual  CCIR656 interface supported  RGB Through mode supported  For 16/18/24-bit bus  Parallel pixel data output mode (1-pixel/1-clock)  Color format transform supported:  Color format transform between YCbCr422 and RGB565  Color format transform from YCbCr422 to RGB888 ...
Page 17: Internal Sram
N9H26 Technical Reference Manual  PWM  4 PWM channel outputs supported  16-bit counter supported for each PWM channel  Two 8-bit pre-scalars supported and each pre-scalar shared by two PWM channels  Two clock-dividers supported and each divider shared by two PWM channels ...
Page 18 N9H26 Technical Reference Manual  Power-on timeout is supported for low battery protection  GPIO  80 programmable general purpose I/Os supported and separated into 5 groups  Individual configuration supported for each I/O signal  Configurable interrupt control functions supported ...
Page 19: Parts Information List And Pin Configuration
N9H26 Technical Reference Manual PARTS INFORMATION LIST AND PIN CONFIGURATION 3.1 N9H26 Series Part Number Naming Guide Figure 3.1-1 N9H26 Series Part Number Naming Guide Publication Release Date: Sept. 10, 2018 - 19 - Revision V1.01...
Page 20: N9H26 Series Part Selection Guide
N9H26 Technical Reference Manual 3.2 N9H26 Series Part Selection Guide N9H26K Series Operting Core Memory H/W Accelerator Analog Peripheral Power Temperature Part No. H.264, LQFP- 32MB √ 24 3 √ √ √ √ √ 4/5W 24 √ 80 2 √...
Page 21: Pin Configuration
N9H26 Technical Reference Manual 3.3 Pin Configuration 3.3.1 N9H26 series Pin Diagram Figure 3.3-1 N9H26xxN LQFP 128 Pin Diagram Publication Release Date: Sept. 10, 2018 - 21 - Revision V1.01...
Page 22: Pin Description
N9H26 Technical Reference Manual 3.4 Pin Description Pin No Name Type Group Description SD0_D[2] SD Interface Port 0 Data Bit 2. TRST_b JTAG Alternative JTAG Interface Test Reset, Low Active. GPE[4] GPIOE GPIO Port E Bit 4. LVD_O SYSTEM Low Voltage Detect Indicator, Low Active. SD0_D[3] SD Interface Port 0 Data Bit 3.
Page 23 N9H26 Technical Reference Manual GPB[10] GPIOB GPIO Port B Bit 10. SPI1_CLK_a SPI1 Alternative SPI Interface Port 1 Clock. LVDATA[20] LCD Interface Data Bit 20. GPB[9] GPIOB GPIO Port B Bit 9. LVDATA[19] LCD Interface Data Bit 19. GPB[8] GPIOB GPIO Port B Bit 8.
Page 24 N9H26 Technical Reference Manual UD_REXT USBD20 External Resister 12.1K Resistor Connected to Ground. ADC_VDD33 SAR_ADC SAR-ADC Power. ADC_TP_XM SAR_ADC Touch Panel XM. SPI1_DI_b SPI1 Alternative SPI Interface Port 1 Data In. SDIO_D[2]_b SDIO Alternative SDIO Interface Data Bit 2. GPG[14] GPIOG GPIO Port G Bit 14.
Page 25 N9H26 Technical Reference Manual UH_VDD12 USBH20 USB 2.0 Host Core Logic Power. ISCK_a Alternative I2C Interface Clock. GPB[13] GPIOB GPIO Port B Bit 13. ISDA_a Alternative I2C Interface Data. GPB[14] GPIOB GPIO Port B Bit 14. SPI0_D[3]_c SPI0 Alternative SPI Interface Port 0 Data Bit 3. LVSYNC LCD Interface Vertical SYNC, High Active.
Page 26 N9H26 Technical Reference Manual CHIPCFG[8] ChipCFG Chip Power On Configuration Data Bit 8. KPI_SO[4] KPI_SO KPI Scan Out Bit 4. LVDATA[5] LCD Interface Data Bit 5. GPC[5] GPIOC GPIO Port C Bit 5. CHIPCFG[9] ChipCFG Chip Power On Configuration Data Bit 9. KPI_SO[5] KPI_SO KPI Scan Out Bit 5.
Page 27 N9H26 Technical Reference Manual KPI_SO[11] KPI_SO KPI Scan Out Bit 11. KPI_SO[3] KPI_SO KPI Scan Out Bit 3. LVDATA[12] LCD Interface Data Bit 12. SDIO_CMD_a SDIO Alternative SDIO Interface Command. GPC[12] GPIOC GPIO Port C Bit 12. KPI_SO[12] KPI_SO KPI Scan Out Bit 12. KPI_SO[4] KPI_SO KPI Scan Out Bit 4.
Page 28 N9H26 Technical Reference Manual GPB[15] GPIOB GPIO Port B Bit 15. TRST_a JTAG Alternative JTAG Interface Test Reset, Low Active. HUR_RTS HUART High Speed UART Request To Send. SPI0_CS1_ SPI0 SPI Interface Port 0 Device Select 1. UHL0_DM_a USBH11_0 Alternative USB 1.1 Host Lite Port 0 D-. GPD[4] GPIOD GPIO Port D Bit 4.
Page 29 N9H26 Technical Reference Manual GPG[5] GPIOG GPIO Port G Bit 5. I2S_WS_b Alternative I2S Interface Left/Right Channel Clock. SPI1_DI_c SPI1 Alternative SPI Interface Port 1 Data In. SDIO_CD_b SDIO Alternative SDIO Interface Card Detect Indicator, Low Active. GPG[4] GPIOG GPIO Port G Bit 4. I2S_DOUT_b Alternative I2S Interface Data Output.
Page 30 N9H26 Technical Reference Manual ISDA_c Alternative I2C Interface Data. LMVSYNC LCD Interface MPU Mode Vertical Sync., High Active. GPA[11] GPIOA GPIO Port A Bit 11. VDD12 VDD12 Core Logic Power. ND[0] NAND NAND Interface Data Bit 0. CHIPCFG[0] ChipCFG Chip Power On Configuration Data Bit 0. ND[1] NAND NAND Interface Data Bit 1.
Page 31 N9H26 Technical Reference Manual GPD[8] GPIOD GPIO Port D Bit 8. NRE_ NAND NAND Interface Read Enable, Low Active SD2_CLK SD Interface Port 2 Clock. GPD[7] GPIOD GPIO Port D Bit 7. NCLE NAND NAND Interface Command Latch Enable, Low Active SD2_D[1] SD Interface Port 2 Data Bit 1.
Page 32 N9H26 Technical Reference Manual GPD[12] GPIOD GPIO Port D Bit 12. Ground Note: TYPE DESCRIPTION Input Output Input / Output Digital Power or Digital GND Analog Power or Analog GND Analog Input Publication Release Date: Sept. 10, 2018 - 32 - Revision V1.01...
Page 33: Block Diagram
H.264 H.264 (32KB) Encoder Decoder Audio Video USB 2.0 PHY UART X 2 SPI X 2 GPIO PWM X 4 USB 2.0 PHY Figure 4.1-1 N9H26 Series Block Diagram Publication Release Date: Sept. 10, 2018 - 33 - Revision V1.01...
Page 34: Functional Description
N9H26 Technical Reference Manual FUNCTIONAL DESCRIPTION 5.1 ARM926EJ-S CPU Core The ARM926EJ-S CPU core is a member of the ARM9 family of general-purpose microprocessors. The ARM926EJ-S CPU core is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important. The ARM926EJ-S CPU core supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to trade off between high performance and high code density.
Page 35: System Manager
N9H26 Technical Reference Manual 5.2 System Manager 5.2.1 Overview The following functions are included in System Manager Section  System Memory Map  Power-On Setting  Bus Arbitration Mode  Power Management  IBR (Internal Boot ROM) Sequence  System management registers for product ID, functional reset and multi-function pin control.
Page 36 N9H26 Technical Reference Manual 0xFFFF_FFFF IBR (64KB) 0xFFFF_0000 Reserved 0xFF00_A000 Rotation SRAM (32KB) 0xFF00_2000 Internal SRAM (8KB) 0xFF00_0000 Reserved 0xC000_0000 APB Bridge 0xB800_0000 AHB2 Bridge 0xB100_0000 AHB1 Bridge 0xB000_0000 Shadow Memory of DRAM (uncacheable) 0x8000_0000 Reserved 0x4000_0000 DRAM (cacheable) 0x0000_0000 Publication Release Date: Sept.
Page 37 N9H26 Technical Reference Manual Memory Space Base Address Alias Descriptions 0x0000_0000 – 0x7FFF_FFFF SDRAM_BA SDRAM Memory Space 0x8000_0000 – 0xAFFF_FFFF Shadow Space for SDRAM 0xFF00_0000 – 0xFF00_1FFF 0xFF00_0000 SRAM_BA SRAM Memory Space (8KB) 0xFF00_2000 – 0xFF00_9FFF 0xFF00_2000 RRAM_BA Rotation SRAM Memory Space (32KB) 0xFFFF_0000 –...
Page 38 N9H26 Technical Reference Manual Memory Space Base Address Alias Descriptions 0xB800_2000 – 0xB800_2FFF 0xB800_2000 TMR_BA Timer/WDT Control Registers 0xB800_3000 – 0xB800_3FFF 0xB800_3000 RTC_BA RTC Control Registers 0xB800_4000 – 0xB800_4FFF 0xB800_4000 I2C_BA I2C Control Registers 0xB800_5000 – 0xB800_5FFF 0xB800_5000 KPI_BA KPI Control Registers 0xB800_7000 –...
Page 39: Power-On Settings
N9H26 Technical Reference Manual 5.2.3 Power-On Settings The power-on setting value is used to configure the chip to enter a specific state after power-up or reset. The power-on setting value will be kept in power-on setting control register for reference. Register Bit Pin Name Descriptions...
Page 40 N9H26 Technical Reference Manual Register Bit Pin Name Descriptions Mapping SDRAM Type Selection This 2-bit power-on setting value is to indicate which type of SDRAM is used for system memory. Value Description ND[5:4] CHIPCFG[5:4] 0x00 SDR SDRAM (normal SDRAM) is used. 0x01 Low Power DDR (mDDR) SDRAM is used.
Page 41: Power-On Setting Waveform
N9H26 Technical Reference Manual Register Bit Pin Name Descriptions Mapping 0x0111 Configure CHIP to enter TIC mode. Boot from IBR Recover Mode with crystal input is 12MHz & DRAM 0x10X0 Speed=132MHz. (JTAG2) Boot From IBR Normal Mode with crystal input is 12MHz & DRAM 0x10X1 Speed=132MHz.
Page 42 N9H26 Technical Reference Manual the AHB bus transfer for each engine. In fixed priority mode of AHB-4 Bus, a programmable time-out is attached to any host except the Audio to ensure that it is not blocked indefinitely by higher priority hosts. When a low-priority master requests the arbitration (i.e., Display, Video Capture, or FMI), the associated time-out counter is loaded with the programmed value and starts decrementing.
Page 43: Power Management Mode
N9H26 Technical Reference Manual several requestors are in this situation, the priority order is: Display, Video Capture, GVE Rotation Engine and SIC. If the counter value is set as 0, then the corresponding time-out scheme for that master is disabled. 5.2.5.3 Rotate rule Example: In the default sequence of AHB DMA Masters, the priority is Audio >...
Page 44: Ibr (Internal Boot Rom) Sequence
N9H26 Technical Reference Manual 5.2.7 IBR (Internal Boot ROM) Sequence Publication Release Date: Sept. 10, 2018 - 44 - Revision V1.01...
Page 45 N9H26 Technical Reference Manual System Management Control Registers Register Address Description Reset Value GCR_BA = 0xB000_0000 CHIPID GCR_BA+0x00 Chip Identification Register 0x00FA_D007 CHIPCFG GCR_BA+0x04 Chip Power-On Configuration Register 0x0003_2XXX OVCKCFG GCR_BA+0x08 Overclk configuration register 0x0000_0000 AHBCTL GCR_BA+0x10 AHB Bus Arbitration Control Register 0x0000_0000 AHBIPRST GCR_BA+0x14...
Page 46 N9H26 Technical Reference Manual Register Address Description Reset Value MISC_SL_GPC GCR_BA+0xBC GPIO C Slew Rate control 0x0000_0000 MISC_SL_GPD GCR_BA+0xC0 GPIO D Slew Rate control 0x0000_0000 MISC_SL_GPE GCR_BA+0xC4 GPIO E Slew Rate control 0x0000_0000 MISC_SL_ND GCR_BA+0xC8 ND PAD Slew Rate control 0x0000_0000 MISC_DS_GPA GCR_BA+0xCC...
Page 47 N9H26 Technical Reference Manual Chip Identification Register (CHIPID) This register provides specific read-only information for software to identify the revision and ID of chip. Register Address Description Reset Value CHIPID GCR_BA+0x00 Chip Identification Register 0x00FA_D007 Reserved CHIP_ID CHIP_ID CHIP_ID Bits Descriptions [31:24] Reserved...
Page 48 N9H26 Technical Reference Manual Chip Power-on Configuration Register (CHIPCFG) This register provides information for software to identify chip’s power-on setting. Bits [7:0] are the status of the power-on setting pins. These configuration bits could be modified by software programming. Register Address Description Reset Value...
Page 49 N9H26 Technical Reference Manual Bits Descriptions NAND BCH algorithm selection, bit NBCH is combined with COPMOD[1], i.e. CHIPCFG[11, 1] This power-on setting value define the NAND BCH type is used for NAND booting Value Description [0,0] BCH12 [11] NBCH [1,0] BCH15 [0,1] BCH24...
Page 50 N9H26 Technical Reference Manual Bits Descriptions SDRAM Type Selection This field reflects the power-on setting value about which type of SDRAM is used for system memory. 2’b00: SDR SDRAM (normal SDRAM) is used. [5:4] SDRAMSEL 2’b01: Low Power DDR (mDDR) SDRAM is used. 2’b10: DDR SDRAM is used.
Page 51 N9H26 Technical Reference Manual Bits Descriptions Bit[0] Note: Default bit status is “1” if it is not programmed, the programming process will make the bit status to be “0”. 1: On 0:Off Publication Release Date: Sept. 10, 2018 - 51 - Revision V1.01...
Page 52 N9H26 Technical Reference Manual Overclk Configuration Register (OVCKCFG) This register provides information for software to overclock setting. Bits [7:0] are the counter of the ring oscillator pulse width in GSPLL clock domain. These configuration bits could be modified by software programming.
Page 53 N9H26 Technical Reference Manual [Overclk_div] 20 Dly 20 Dly 20 Dly 20 Dly 20 Dly overclk_test_en out_099 out_099_2 out_099_4 out_099_8 overclk_test_out out_099_512 out_099_16 out_099_32 out_099_64 out_099_128 out_099_256 overclk_cnt_en active Publication Release Date: Sept. 10, 2018 - 53 - Revision V1.01...
Page 54 N9H26 Technical Reference Manual AHB Bus Arbitration Control Register (AHBCTL) Register Address Description Reset Value AHBCTL GCR_BA+0x10 AHB Bus Arbitration Control Register 0x0000_0000 Reserved Reserved Reserved Reserved IPACT IPEN Reserved PRTMOD1 PRTMOD0 Bits Descriptions [31:6] Reserved Reserved IPACT Interrupt Active Status IPEN CPU Priority Raising Enable during Interrupt Period Reserved...
Page 55 N9H26 Technical Reference Manual AHB IP Reset Control Register (AHBIPRST) Each bit of this register is to reset its corresponding functional circuit. By writing 1’b1 to any reset bit, the corresponding functional circuit will be reset, and all operating state and control registers of that functional circuit will return to their default power-on state.
Page 56 N9H26 Technical Reference Manual Bits Descriptions 1’b0: JPEG reset is no active. 1’b1: JPEG reset is active. 2D BLT Blitter Controller Reset [16] BLT_RST 1’b0: 2D BLT reset is no active 1’b1: 2D BLT reset is active H.264 Video Decoder Reset [15] VDE_RST 1’b0: Video Decoder reset is no active...
Page 57 N9H26 Technical Reference Manual Bits Descriptions EDMA Reset EDMA_RST 1’b0: EDMA reset is no active. 1’b1: EDMA reset is active. SRAM Controller Reset SRAM_RST 1’b0: SRAM controller reset is no active. 1’b1: SRAM controller reset is active. EMAC Controller Reset EMAC_RST 1’b0: EMAC controller reset is no active.
Page 58 N9H26 Technical Reference Manual APB IP Reset Control Register (APBIPRST) Each bit of this register is to reset its corresponding functional circuit. By writing 1’b1 to any reset bit, the corresponding functional circuit will be reset, and all operating state and control registers of that functional circuit will return to their default power-on state.
Page 59 N9H26 Technical Reference Manual Bits Descriptions 1’b0: RS Codec reset is no active 1’b1: RS Codec reset is active PWM Reset [10] PWMRST 1’b0: PWM reset is no active. 1’b1: PWM reset is active. RF Codec Reset RFC_RST 1’b0: RFC Codec reset is no active 1’b1: RFC Codec reset is active I2C Reset I2CRST...
Page 60 N9H26 Technical Reference Manual Miscellaneous Control Register (MISCR) Register Address Description Reset Value MISCR GCR_BA+0x20 Miscellaneous Control Register 0x0000_0000 Reserved WDTRSTEN UTMISnoop Reserved SEL_HSCUR SEL_PHASE UTMISnoop_H Reserved SEL_HSCUR_HOST SEL_PHASE_HOST Reserved EMAC Reserved CPURSTON CPURST PWRDN Bits Descriptions [31:25] Reserved Reserved WatchDog Timer Reset Connection Enable This bit is use to enable the function that connect watch-dog timer reset to RST_ pin.
Page 61 N9H26 Technical Reference Manual Bits Descriptions SEL_PHASE_HOST USB 2.0 HOST PHY Control SEL_PHASE [9:8] Reserved [7:5] Reserved EMAC Power Down Mode Control EMAC_ 1’b0: No power down. PWRDN 1’b1: EMAC enters power down mode. Reserved [3:2] Reserved CPU Reset ON (cleared by register write 0) This bit is to reset CPU continuously.
Page 62 N9H26 Technical Reference Manual SDRAM BIST Test Status Register （SDRBIST） Register Address Description Reset Value SDRBIST GCR_BA+0x24 SDRAM BIST Test Status Register 0x0000_0000 TEST_BUSY CON_BUYS BIST_BUSY TEST_FAIL CON_FAIL BIST_FAIL Reserved Reserved Reserved Reserved Bits Descriptions Test BUSY This bit indicates the SDRAM test is on going or finished. The test includes connection test and SDRAM BIST test.
Page 63 N9H26 Technical Reference Manual Bits Descriptions 0. The first checked error is record on registers TFADDR and TFDATA. 0: SDRAM BIST test is OK. 1: SDRAM BIST test failed. [25:0] Reserved Reserved Publication Release Date: Sept. 10, 2018 - 63 - Revision V1.01...
Page 64 N9H26 Technical Reference Manual EDMA 1st Service Selection Control Register (ED0SSR) Register Address Description Reset Value ED0SSR GCR_BA+0x2C EDMA 1st Service Selection Control Register 0x7720_4270 Reserved CH4_TXSEL Reserved CH3_TXSEL Reserved CH2_TXSEL Reserved CH1_TXSEL Reserved CH4_RXSEL Reserved CH3_RXSEL Reserved CH2_RXSEL Reserved CH1_RXSEL Bits Descriptions...
Page 65 N9H26 Technical Reference Manual Bits Descriptions [23] Reserved Reserved EDMA Channel 2 Tx Selection This filed defined EDMA channel 2 is to service which on-chip peripherals. If this filed is configured to be 3’b111, the TX request of EDMA channel 2 is disabled. 3’b000: SPIMS 0 3’b001: SPIMS 1 3’b010: UART 0 (Default)
Page 66 N9H26 Technical Reference Manual Bits Descriptions 3’b000: SPIMS 0 3’b001: SPIMS 1 3’b010: UART 0 (Default) 3’b011: UART 1 3’b100: ADC Controller 3’b101: RF_CODEC 3’b110: RS_CODEC 3’b111: Disable Others: Reserved Reserved Reserved EDMA Channel 2 Rx Selection This filed defined EDMA channel 2 is to service which on-chip peripherals. If this filed is configured to be 3’b111, the RX request of EDMA channel 2 is disabled.
Page 67 N9H26 Technical Reference Manual EDMA 2nd Service Selection Control Register (ED1SSR) Register Address Description Reset Value ED1SSR GCR_BA+0x30 EDMA 2nd Service Selection Control Register 0x7777_7777 Reserved CH12_TXSEL Reserved CH11_TXSEL Reserved CH10_TXSEL Reserved CH9_TXSEL Reserved CH12_RXSEL Reserved CH11_RXSEL Reserved CH10_RXSEL Reserved CH9_RXSEL Bits Descriptions...
Page 68 N9H26 Technical Reference Manual Bits Descriptions [23] Reserved Reserved EDMA Channel 6 Tx Selection This filed defined EDMA channel 6 is to service which on-chip peripherals. If this filed is configured to be 3’b111, the TX request of EDMA channel 6 is disabled. 3’b000: SPIMS 0 3’b001: SPIMS 1 3’b010: UART 0 (Default)
Page 69 N9H26 Technical Reference Manual Bits Descriptions 3’b000: SPIMS 0 3’b001: SPIMS 1 3’b010: UART 0 (Default) 3’b011: UART 1 3’b100: ADC Controller 3’b101: RF_CODEC 3’b110: RS_CODEC 3’b111: Disable Others: Reserved Reserved Reserved EDMA Channel 6 Rx Selection This filed defined EDMA channel 6 is to service which on-chip peripherals. If this filed is configured to be 3’b111, the RX request of EDMA channel 6 is disabled.
Page 70 N9H26 Technical Reference Manual Miscellaneous Status Register （MISSR） Register Address Description Reset Value MISSR GCR_BA+0x34 Miscellaneous Status Register 0x00FF_00XX KPI_WS ADC_WS UHC_WS UDC_WS UART_WS SDH_WS RTC_WS GPIO_WS KPI_WE ADC_WE UHC_WE UDC_WE UART_WE SDH_WE RTC_WE GPIO_WE UHC20_WS EMAC_WS UHC20_WE EMAC_WE POR12_RST CPU_RST WDT_RST KPI_RST...
Page 71 N9H26 Technical Reference Manual Bits Descriptions [14] EMAC_WS EMAC Wake-Up Status [13:8] Reserved Reserved UHC20_WE UHC20 Wake-Up Enable EMAC_WE EMAC Wake-Up Enable POR12_RST POR12 Reset Active Status CPU_RST CPU Reset Active Status WDT_RST WDT Reset Active Status KPI_RST KPI Reset Active Status LVR_RST LVR Reset Active Status EXT_RST...
Page 72 N9H26 Technical Reference Manual AHB4 Master’s 1st Time-out Counter Control Register (AHB4_TOC0) This register defines the 8-bit time-out counter control for the AHB4 Master’s DMA Bus Priority. In fixed priority mode of AHB4 Bus, a programmable time-out is attached to any host except the Audio to ensure that it is not blocked indefinitely by higher priority hosts.
Page 73 N9H26 Technical Reference Manual AHB4 Master’s 2nd Time-out Counter Control Register (AHB4_TOC1) This register defines the 8-bit time-out counter control for the AHB4 Master’s DMA Bus Priority. In fixed priority mode of AHB4 Bus, a programmable time-out is attached to any host except the Audio to ensure that it is not blocked indefinitely by higher priority hosts.
Page 74 N9H26 Technical Reference Manual Chip Date Code & Version Code Register (CDCVC) Register Address Description Reset Value CDCVC GCR_BA+0x48 Chip Date Code & Version Code Register 0xXXXX_XXXX YEAR MONTH VERSION Bits Descriptions [31:24] YEAR Year Code (8 bits) [23:16] MONTH Month Code (8 bits) [15:8] Day Code (8 bits)
Page 75 N9H26 Technical Reference Manual POR and LVRD Control Register (POR_LVRD) This register defines the control function description for POR and LVRD Register Address Description Reset Value POR_LVRD GCR_BA+0x74 POR and LVRD Control Register 0x0000_00XX Reserved Reserved Reserved MPLL_LKDT UPLL_LKDT APLL_LKDT POR_ENB EN_LVR EN_LVD...
Page 76 N9H26 Technical Reference Manual GPIO A Multi-function 1st Control Register (GPAFUN0) This register defines the multi-function description for GPIO A. Note: The pull-up enable of the pins shared with GPIOA is controlled by register GPIOA_PUEN directly. Users have to set the GPIOA_PUEN properly before the chip entered the standby mode. Register Address Description...
Page 77 N9H26 Technical Reference Manual Bits Descriptions Pin Name MF_GPA3 GPA[3] 4’b0000 4’b0001 4’b0010 4’b0011 GPIOA[3] KPI_SI[0] Reserved UHL_DP0 GPIOA[2] Multi-function Pin Name MF_GPA2 [11:8] MF_GPA2 GPA[2] 4’b0000 4’b0001 4’b0010 4’b0011 GPIOA[2] SFIELD_2 LMVSYNC LMVSYNC GPIOA[1] Multi-function Pin Name MF_GPA1 [7:4] MF_GPA1 GPA[1] 4’b0000...
Page 78 N9H26 Technical Reference Manual GPIO A Multi-function 2nd Control Register (GPAFUN1) This register defines the multi-function description for GPIO A. Note: The pull-up enable of the pins shared with GPIOA is controlled by register GPIOA_PUEN directly. Users have to set the GPIOA_PUEN properly before the chip entered the standby mode. Register Address Description...
Page 79 N9H26 Technical Reference Manual Bits Descriptions Pin Name MF_GPA11 URRXD 4’b0000 4’b0001 4’b0010 4’b0011 4’b0100 4’b0101 GPIOA[11] LMVSYNC ISDA URRXD UHL_DM1 SFIELD_2 GPIOA[10] Multi-function pin Name MF_GPA10 [11:8] MF_GPA10 URTXD 4’b0000 4’b0001 4’b0010 4’b0011 4’b0100 GPIOA[10] SPI1_CS1_ ISCK URTXD UHL_DP1 GPIOA[9] Multi-function Pin Name MF_GPA9...
Page 80 N9H26 Technical Reference Manual GPIO B Multi-function 1st Control Register (GPBFUN0) Note: The pull-up/down enable of the pins shared with GPIOB is controlled by register GPIOB_PUEN directly. Users have to set the GPIOB_PUEN properly before the chip entered the standby mode. Register Address Description...
Page 81 N9H26 Technical Reference Manual Bits Descriptions SVSYNC 4’b0000 4’b0001 4’b0010 4’b0011 GPIOB[3] I2S_BCLK SDCMD1 SVSYNC GPIOB[2] Multi-function Pin Name MF_GPB2 [11:8] MF_GPB2 SHSYNC 4’b0000 4’b0001 4’b0010 4’b0011 GPIOB[2] I2S_MCLK SDCLK1 SHSYNC GPIOB[1] Multi-function Pin Name MF_GPB1 [7:4] MF_GPB1 SPCLK 4’b0000 4’b0001 4’b0010 4’b0011...
Page 82 N9H26 Technical Reference Manual GPIO B Multi-function 2nd Control Register (GPBFUN1) Note: The pull-up/down enable of the pins shared with GPIOB is controlled by register GPIOB_PUEN directly. Users have to set the GPIOB_PUEN properly before the chip entered the standby mode. Register Address Description...
Page 83 N9H26 Technical Reference Manual Bits Descriptions Pin Name MF_GPB11 SPDATA[6] 4’b0000 4’b0001 4’b0010 4’b0011 4’b0100 GPIOB[11] SPI1_DI LVDATA[22] SPDATA[6] DLL_TCLKS GPIOB[10] Multi-function Pin Name MF_GPB10 [11:8] MF_GPB10 SPDATA[5] 4’b0000 4’b0001 4’b0010 4’b0011 4’b0100 GPIOB[10] SPI1_CS0_ LVDATA[21] SPDATA[5] DLL_TESTER_R[1] GPIOB[9] Multi-function Pin Name MF_GPB9 [7:4]...
Page 84 N9H26 Technical Reference Manual GPIO C Multi-function 1st Control Register (GPCFUN0) Note: The pull-up enable of the pins shared with GPIOC is controlled by register GPIOC_PUEN directly. Users have to set the GPIOC_PUEN properly before the chip entered the standby mode. Register Address Description...
Page 85 N9H26 Technical Reference Manual Bits Descriptions Pin Name MF_GPC3 LVDATA[3] 4’b0000 4’b0001 4’b0010 4’b0011 GPIOC[3] SDRM_TFAIL LVDATA[3] KPI_SO[3] GPIOC[2] Multi-function Pin Name MF_GPC2 [11:8] MF_GPC2 LVDATA[2] 4’b0000 4’b0001 4’b0010 4’b0011 GPIOC[2] SDRM_BBUSY LVDATA[2] KPI_SO[2] GPIOC[1] Multi-function Pin Name MF_GPC1 [7:4] MF_GPC1 LVDATA[1] 4’b0000...
Page 86 N9H26 Technical Reference Manual GPIO C Multi-function 2nd Control Register (GPCFUN1) Note: The pull-up enable of the pins shared with GPIOC is controlled by register GPIOC_PUEN directly. Users have to set the GPIOC_PUEN properly before the chip entered the standby mode. Register Address Description...
Page 87 N9H26 Technical Reference Manual Bits Descriptions Pin Name MF_GPC11 LVDATA[11] 4’b0000 4’b0001 4’b0010 4’b0011 4’b0100 4’b0101 GPIOC[11] SPDATA[3] LVDATA[11] KPI_SO[11] TXD0 SDIO_D3 GPIOC[10] Multi-function Pin Name MF_GPC10 [11:8] MF_GPC10 LVDATA[10] 4’b0000 4’b0001 4’b0010 4’b0011 4’b0100 4’b0101 GPIOC[10] SPDATA[2] LVDATA[10] KPI_SO[10] MDIO SDIO_D2 GPIOC[9] Multi-function...
Page 88 N9H26 Technical Reference Manual GPIO D Multi-function 1st Control Register (GPDFUN0) Note: The pull-up/down enable of the pins shared with GPIOD is controlled by register GPIOD_PUEN directly. Users have to set the GPIOD_PUEN properly before the chip entered the standby mode. Register Address Description...
Page 89 N9H26 Technical Reference Manual Bits Descriptions PinNam MF_GPD3 4’b00 4’b000 4’b00 4’b00 4’b01 4’b100 4’b110 4’b11 4’b11 GPIO HUR_ TIC_ SVSYN UHL_ LVD_ MDIO D[3] GPIOD[2] Multi-function Pin Name MF_GPD2 [11:8] MF_GPD2 4’b0000 4’b0001 4’b0010 4’b0011 4’b0100 4’b1000 4’b1110 GPIOD[2] HUR_RX PWM2 TIC_CS...
Page 90 N9H26 Technical Reference Manual GPIO D Multi-function 2nd Control Register (GPDFUN1) Note: The pull-up/down enable of the pins shared with GPIOD is controlled by register GPIOD_PUEN directly. Users have to set the GPIOD_PUEN properly before the chip entered the standby mode. Register Address Description...
Page 91 N9H26 Technical Reference Manual Bits Descriptions Pin Name MF_GPD11 LVDE 4’b0000 4’b0001 4’b0010 4’b0011 4’b1000 4’b1110 GPIOD[11] Reserved LVDE LVDE S2DATA[0] REFCLK GPIOD[10] Multi-function Pin Name MF_GPD10 [11:8] MF_GPD10 LVSYNC 4’b0000 4’b0001 4’b0010 4’b0011 4’b1000 4’b1110 GPIOD[10] Reserved LVSYNC LVSYNC S2DATA[1] GPIOD[9] Multi-function Pin Name...
Page 92 N9H26 Technical Reference Manual GPIO E Multi-function 1st Control Register (GPEFUN0) Note: The pull-up enable of the pins shared with GPIOE is controlled by register GPIOE_PUEN directly. Users have to set the GPIOE_PUEN properly before the chip entered the standby mode. Register Address Description...
Page 93 N9H26 Technical Reference Manual Bits Descriptions Pin Name MF_GPE3 SDDAT[1] 4’b0000 4’b0001 4’b0010 4’b0011 GPIOE[3] SDDAT[1] SDDAT[1] GPIOE[2] Multi-function Pin Name MF_GPE2 [11:8] MF_GPE2 SDDAT[0] 4’b0000 4’b0001 4’b0010 4’b0011 GPIOE[2] SDDAT[0] SDDAT[0] GPIOE[1] Multi-function Pin Name MF_GPE1 [7:4] MF_GPE1 LVDATA[17] 4’b0000 4’b0001 4’b0010...
Page 94 N9H26 Technical Reference Manual GPIO E Multi-function 2nd Control Register (GPEFUN1) Note: The pull-up enable of the pins shared with GPIOE is controlled by register GPIOE_PUEN directly. Users have to set the GPIOE_PUEN properly before the chip entered the standby mode. Register Address Description...
Page 95 N9H26 Technical Reference Manual Bits Descriptions NCS1_ 4’b0000 4’b0001 4’b0010 4’b0011 4’b0100 GPIOE[9] USB_PWEN NCS1_ NCS1_ SPI0_D3 GPIOE[8] Multi-function Pin Name MF_GPE8 [3:0] MF_GPE8 NCS0_ 4’b0000 4’b0001 4’b0010 4’b0011 4’b0100 GPIOE[8] Reserved NCS0_ NCS0_ SPI0_D2 Publication Release Date: Sept. 10, 2018 - 95 - Revision V1.01...
Page 96 N9H26 Technical Reference Manual Miscellaneous Multi-function Control Register (MISFUN) Register Address Description Reset Value MISFUN GCR_BA+0xA8 Miscellaneous Multi-function Control Register 0x0000_0001 Reserved Reserved Reserved Reserved MF_I2S Bits Descriptions [31:1] Reserved Reserved I2S I/F Functional Selection This field is to control the I2S interface is used by I2S Controller or SPU. Pin Name MF_I2S MF_I2S...
Page 97 N9H26 Technical Reference Manual SPI[3:2] and LVDATA[23:18] (GPIO H) Control Register (SPI_LVD_GPH) Register Address R/W Description Reset Value SPI_LVD_GPH GCR_BA+0xAC R/W SPI[3:2] And LVDATA[23:18] (GPIO H) Control Register 0x0000_0000 Reserved DS_SPI_GPH[7:6] DS_LVD_GPH[5:0] Reserved SL_SPI_GPH[7:6] SL_LVD_GPH[5:0] Bits Descriptions [31:24] Reserved Reserved SPI_DATA[3:2] (GPIO_H[7:6]) Pin Driver Strength Control These bits control the output Driver Strength of GPIO_H[7:6] pins.
Page 98 N9H26 Technical Reference Manual Miscellaneous Pins Control Register (MISCPCR) Register Address Description Reset Value MISCPCR GCR_BA+0xB0 Miscellaneous Pins Control Register 0x0000_0000 Reserved Reserved Reserved SL_MD SL_MA SL_MCTL SL_MCLK DS_MD DS_MA DS_MCTL DS_MCLK Bits Descriptions [31:8] Reserved Reserved MD Pins Slew Rate Control This bit control the output slew rate of 16 MD pins.
Page 99 N9H26 Technical Reference Manual Bits Descriptions This bit controls the output driving strength of 13 MA and 3 MBA pins. 1’b0: Output driving strength is 8mA (Class I Buffer). 1’b1: Output driving strength is 24mA (Class II Buffer). Memory I/F Control Pins Driving Strength Control This bit controls the output driving strength of MCKE, MCS0_, MCS1_, MRAS_, MCAS_, MWE_, MDQM, MDQS0 and MDQS1 pins.
Page 100 N9H26 Technical Reference Manual GPIO A Slew Rate Control (MISC_SL_GPA) Register Address R/W Description Reset Value MISC_SL_GPA GCR_BA+0xB4 R/W GPIO A Slew Rate Control Register 0x0000_0000 Reserved Reserved Reserved SL_GPA[11:0] SL_GPA[11:0] Bits Descriptions [31:12] Reserved Reserved GPA[11] Pin Slew Rate Control This bit control the output slew rate of GPA[11] pin.
Page 101 N9H26 Technical Reference Manual Bits Descriptions 1’b1: Output slew rate is Slow. GPA[5] Pin Slew Rate Control This bit control the output slew rate of GPA[5] pin. SL_GPA[5] 1’b0: Output slew rate is Fast. 1’b1: Output slew rate is Slow. GPA[4] Pin Slew Rate Control This bit control the output slew rate of GPA[4] pin.
Page 102 N9H26 Technical Reference Manual GPIO B Slew Rate Control (MISC_SL_GPB) Register Address R/W Description Reset Value MISC_SL_GPB GCR_BA+0xB8 R/W GPIO B Slew Rate Control Register 0x0000_0000 Reserved Reserved SL_GPB[15:0] SL_GPB[15:0] Bits Descriptions [31:16] Reserved Reserved GPB[15] Pin Slew Rate Control This bit control the output slew rate of GPB[15] pin.
Page 103 N9H26 Technical Reference Manual Bits Descriptions 1’b0: Output slew rate is Fast. 1’b1: Output slew rate is Slow. GPB[9] Pin Slew Rate Control This bit control the output slew rate of GPB[9] pin. SL_GPB[9] 1’b0: Output slew rate is Fast. 1’b1: Output slew rate is Slow.
Page 104 N9H26 Technical Reference Manual Bits Descriptions 1’b1: Output slew rate is Slow. Publication Release Date: Sept. 10, 2018 - 104 - Revision V1.01...
Page 105 N9H26 Technical Reference Manual GPIO C Slew Rate Control (MISC_SL_GPC) Register Address R/W Description Reset Value MISC_SL_GPC GCR_BA+0xBC R/W GPIO C Slew Rate Control Register 0x0000_0000 Reserved Reserved SL_GPC[15:0] SL_GPC[15:0] Bits Descriptions [31:16] Reserved Reserved GPC[15] Pin Slew Rate Control This bit control the output slew rate of GPC[15] pin.
Page 106 N9H26 Technical Reference Manual Bits Descriptions 1’b0: Output slew rate is Fast. 1’b1: Output slew rate is Slow. GPC[9] Pin Slew Rate Control This bit control the output slew rate of GPC[9] pin. SL_GPC[9] 1’b0: Output slew rate is Fast. 1’b1: Output slew rate is Slow.
Page 107 N9H26 Technical Reference Manual Bits Descriptions 1’b1: Output slew rate is Slow. Publication Release Date: Sept. 10, 2018 - 107 - Revision V1.01...
Page 108 N9H26 Technical Reference Manual GPIO D Slew Rate Control (MISC_SL_GPD) Register Address R/W Description Reset Value MISC_SL_GPD GCR_BA+0XC0 R/W GPIO D Slew Rate Control Register 0x0000_0000 Reserved Reserved SL_GPD[15:0] SL_GPD[15:0] Bits Descriptions [31:16] Reserved Reserved GPD[15] Pin Slew Rate Control This bit control the output slew rate of GPD[15] pin.
Page 109 N9H26 Technical Reference Manual Bits Descriptions 1’b1: Output slew rate is Slow. GPD[9] Pin Slew Rate Control This bit control the output slew rate of GPD[9] pin. SL_GPD[9] 1’b0: Output slew rate is Fast. 1’b1: Output slew rate is Slow. GPD[8] Pin Slew Rate Control This bit control the output slew rate of GPD[8] pin.
Page 110 N9H26 Technical Reference Manual GPIO E Slew Rate Control (MISC_SL_GPE) Register Address R/W Description Reset Value MISC_SL_GPE GCR_BA+0XC4 R/W GPIO E Slew Rate Control Register 0x0000_0000 Reserved Reserved Reserved SL_GPE[11:0] SL_GPE[11:0] Bits Descriptions [31:12] Reserved Reserved GPE[11] Pin Slew Rate Control This bit control the output slew rate of GPE[11] pin.
Page 111 N9H26 Technical Reference Manual Bits Descriptions 1’b0: Output slew rate is Fast. 1’b1: Output slew rate is Slow. GPE[5] Pin Slew Rate Control This bit control the output slew rate of GPE[5] pin. SL_GPE[5] 1’b0: Output slew rate is Fast. 1’b1: Output slew rate is Slow.
Page 112 N9H26 Technical Reference Manual ND PAD Slew Rate Control (MISC_SL_ND) Register Address R/W Description Reset Value MISC_SL_ND GCR_BA+0XC8 R/W ND PAD Slew Rate Control Register 0x0000_0000 Reserved Reserved Reserved SL_ND[7:0] Bits Descriptions [31:8] Reserved Reserved ND[7] Pin Slew Rate Control This bit control the output slew rate of ND[7] pin.
Page 113 N9H26 Technical Reference Manual Bits Descriptions 1’b1: Output slew rate is Slow. ND[1] Pin Slew Rate Control This bit control the output slew rate of ND[1] pin. SL_ND[1] 1’b0: Output slew rate is Fast. 1’b1: Output slew rate is Slow. ND[0] Pin Slew Rate Control This bit control the output slew rate of ND[0] pin.
Page 114 N9H26 Technical Reference Manual GPIO A Driver Strength Control (MISC_DS_GPA) Register Address R/W Description Reset Value MISC_DS_GPA GCR_BA+0xCC R/W GPIO A Driver Strength Control Register 0x0000_0000 Reserved Reserved Reserved DS_GPA[11:0] DS_GPA[11:0] Bits Descriptions [31:12] Reserved Reserved GPA[11:0] Pin Driver Strength Control This bit control the output Driver Strength of GPA[11:0] pin.
Page 115 N9H26 Technical Reference Manual GPIO B Driver Strength Control (MISC_DS_GPB) Register Address R/W Description Reset Value MISC_DS_GPB GCR_BA+0xD0 R/W GPIO B Driver Strength Control Register 0x0000_0000 Reserved Reserved DS_GPB[15:0] DS_GPB[15:0] Bits Descriptions [31:16] Reserved Reserved GPB[15:0] Pin Driver Strength Control This bit control the output Driver Strength of GPB[15:0] pin.
Page 116 N9H26 Technical Reference Manual GPIO C Driver Strength Control (MISC_DS_GPC) Register Address R/W Description Reset Value MISC_DS_GPC GCR_BA+0xD4 R/W GPIO C Driver Strength Control Register 0x0000_0000 DS_GPC[31:24] DS_GPC[23:16] DS_GPC[15:8] DS_GPC[7:0] Bits Descriptions GPC[31:0] Pin Driver Strength Control These bits control the output Driver Strength of GPC[15:0] pins, two bits per pin. 2’b00: 4mA [31:0] DS_GPC[31:0]...
Page 117 N9H26 Technical Reference Manual GPIO D Driver Strength Control (MISC_DS_GPD) Register Address R/W Description Reset Value MISC_DS_GPD GCR_BA+0xD8 R/W GPIO D Driver Strength Control Register 0x0000_0000 Reserved Reserved DS_GPD[15:0] DS_GPD[15:0] Bits Descriptions [31:16] Reserved Reserved GPD[15:0] Pin Driver Strength Control This bit control the output Driver Strength of GPD[15:0] pin.
Page 118 N9H26 Technical Reference Manual GPIO E Driver Strength Control (MISC_DS_GPE) Register Address R/W Description Reset Value MISC_DS_GPE GCR_BA+0xDC R/W GPIO E Driver Strength Control Register 0x0000_0000 Reserved Reserved Reserved DS_GPE[11:0] DS_GPE[11:0] Bits Descriptions [31:12] Reserved Reserved GPE[11:0] Pin Driver Strength Control This bit control the output Driver Strength of GPE[11:0] pin.
Page 119 N9H26 Technical Reference Manual ND PAD Driver Strength Control (MISC_DS_ND) Register Address Description Reset Value MISC_DS_ND GCR_BA+0xE0 ND PAD Driver Strength Control Register 0x0000_0000 Reserved Reserved Reserved DS_ND[7:0] Bits Descriptions [31:8] Reserved Reserved ND[7:0] Pin Driver Strength Control This bit control the output driver strength of ND[7:0] pin. [7:0] DS_ND[7:0] 1’b0: 4mA...
Page 120 N9H26 Technical Reference Manual SSTL2 and LVTTL Driver Strength Control (MISC_SSEL) Register Address Description Reset Value MISC_SSEL GCR_BA+0xE4 SSTL2 and LVTTL Driver Strength control 0x0000_0300 Reserved Reserved Reserved MCLK MCTL Bits Descriptions [31:10] Reserved Reserved MCLK Pin Driving Strength Control and Mode Mode Power Supply MCLK [1:0]...
Page 121 N9H26 Technical Reference Manual Bits Descriptions SSTL2 2.5V LPDDR 1.8V LVTTL 3.3V 00(12mA) 01(16mA) 10(24mA) 11(30mA) MCTL Pin Driving Strength Control and Mode Mode Power Supply MCTL [1:0] Reduced Strength Full Strength [3:2] MCTL SSTL18 1.8V SSTL2 2.5V LPDDR 1.8V LVTTL 3.3V 00(12mA)
Page 122 N9H26 Technical Reference Manual GPIO G Multi-function 1st Control Register (GPGFUN0) Note: The pull-up enable of the pins shared with GPIOG is controlled by register GPIOG_PUEN directly. Users have to set the GPIOG_PUEN properly before the chip entered the standby mode. Register Address Description...
Page 123 N9H26 Technical Reference Manual Bits Descriptions TVDAC_REXT 4’b0000 4’b0001 4’b0010 4’b0011 4’b1000 4’b1110 GPIOG[3] SDIO_CLK SPI1_CS0 I2S_BCLK S2DATA[6] CRSDV GPIOG[2] Multi-function Pin Name MF_GPG2 MF_GPG [11:8] TVDAC_TVOU 4’b0000 4’b0001 4’b0010 4’b0011 4’b010 4’b1000 4’b111 GPIOG[2 SDIO_CM SPI1_CL I2S_DOU ISCK S2DATA[7 RXER [7:4] Reserved...
Page 124 N9H26 Technical Reference Manual GPIO G Multi-function 2nd Control Register (GPGFUN1) Note: The pull-up enable of the pins shared with GPIOG is controlled by register GPIOG_PUEN directly. Users have to set the GPIOG_PUEN properly before the chip entered the standby mode. Register Address Description...
Page 125 N9H26 Technical Reference Manual Bits Descriptions Pin Name MF_GPG9 ADC_AIN[1] 4’b0000 4’b0001 4’b0010 4’b0011 GPIOG[9] KPI_SI[1] I2S_DI Reserved GPIOG[8] Multi-function Pin Name MF_GPG8 [3:0] MF_GPG8 ADC_AIN[2] 4’b0000 4’b0001 4’b0010 4’b0011 GPIOG[8] Reserved Reserved Reserved Publication Release Date: Sept. 10, 2018 - 125 - Revision V1.01...
Page 126 N9H26 Technical Reference Manual GPIO H Multi-function Control Register (GPHFUN) Note: The pull-up enable of the pins shared with GPIOH is controlled by register GPIOH_PUEN directly. Users have to set the GPIOH_PUEN properly before the chip entered the standby mode. Register Address Description...
Page 127 N9H26 Technical Reference Manual Bits Descriptions 2’b00 2’b01 2’b10 2’b11 Reserved Reserved Reserved Reserved GPIOH[10] Multi-function Pin Name MF_GPH10 [21:20] MF_GPH10 2’b00 2’b01 2’b10 2’b11 Reserved Reserved Reserved Reserved GPIOH[9] Multi-function Pin Name MF_GPH9 [19:18] MF_GPH9 2’b00 2’b01 2’b10 2’b11 Reserved Reserved Reserved...
Page 128 N9H26 Technical Reference Manual Bits Descriptions GPIOH[3] LVDATA[21] Reserved Reserved GPIOH[2] Multi-function Pin Name MF_GPH2 [5:4] MF_GPH2 2’b00 2’b01 2’b10 2’b11 GPIOH[2] LVDATA[20] Reserved Reserved GPIOH[1] Multi-function Pin Name MF_GPH1 [3:2] MF_GPH1 2’b00 2’b01 2’b10 2’b11 GPIOH[1] LVDATA[19] Reserved Reserved GPIOH[0] Multi-function Pin Name MF_GPH0...
Page 129 N9H26 Technical Reference Manual Share Pin with TVDAC Control (ShrPin_TVDAC) Register Address R/W Description Reset Value ShrPin_TVDAC GCR_BA+0xF4 Share Pins with TVDAC 0x8XXX_XXXX SMTVDAC_A Reserved Reserved Reserved Reserved Bits Descriptions Analog and Digital Share I/O Pad Control Bit for TVDAC VREF, REXT, COMP, IOUT Pins. [31] SMTVDAC_AEN 1’b1: Analog Pin...
Page 130 N9H26 Technical Reference Manual Share Pin with AUDIO Control (ShrPin_AUDIO) Register Address R/W Description Reset Value ShrPin_AUDIO GCR_BA+0xF8 Share Pins with AUDIO ADC 0xFXXX_XXXX Reserved AIN2_AEN AIN3_AEN Reserved Reserved Reserved Reserved Reserved Bits Descriptions [31] Reserved Reserved Analog and Digital Share I/O Pad Control Bit for SAR-ADC AIN2 Pins. [30] AIN2_AEN 1’b1: Analog Pin...
Page 131 N9H26 Technical Reference Manual Share Pin with TOUCH Control (ShrPin_TOUCH) Register Address R/W Description Reset Value ShrPin_TOUCH GCR_BA+0xFC Share Pins with TOUCH ADC 0xEXXX_XXXX SAR_AHS_AE TP_AEN Reserved Reserved Reserved Reserved Reserved Bits Descriptions Analog and Digital Share I/O Pad Control Bit for SAR-ADC AHS Pins. SAR_AHS_AEN [31] 1’b1: Analog Pin...
Page 132 N9H26 Technical Reference Manual ExtRST Debounce Control Register (ExtRST_DEBOUNCE) Register Address R/W Description Reset Value DEBOUNCE GCR_BA+0x100 R/W External RESET Debounce Control Register 0x0000_0000 Reserved Reserved Reserved Reserved DEBOUNCE Bits Descriptions [31:1] Reserved Reserved External RESET Debounce Control This bit is to enable or disable the External RESET debounce control. DEBOUNCE 1’b1: Enable RESET debounce.
Page 133 N9H26 Technical Reference Manual ExtRST Debounce Counter (ExtRST_DEBOUNCE_CNTR) Register Address R/W Description Reset Value DEBOUNCE_CNTR GCR_BA+0x104 External RESET Debounce Counter Register 0x0000_04B0 Reserved Reserved DEBOUNCE_CNTR[15:8] DEBOUNCE_CNTR[7:0] Bits Descriptions [31:16] Reserved Reserved This 16-bit external RESET Debouncer Counter can specify the external RESET debouce time DEBOUNCE_CN up to around 5.46ms (0xFFFF) @XIN=12MHz.
Page 134: Multi-Function Pin Note
N9H26 Technical Reference Manual 5.2.8 Multi-function Pin Note In this chip, some functional signals could be assigned to multiple pins. Normally, each functional signal could only be assigned to a pin. This section describes how the functional signal is assigned while the setting makes a functional signal be assigned to multiple pins simultaneously.
Page 135 N9H26 Technical Reference Manual Functional PWM0 Signal Direction In/Out Pin Name SPCLK Out Priority Equal Equal In Priority High Publication Release Date: Sept. 10, 2018 - 135 - Revision V1.01...
Page 136: Clock Controller
N9H26 Technical Reference Manual 5.3 Clock Controller 5.3.1 Clock controller overview The clock controller generates the clocks for the whole chip, it include all of IPs on AHB, APB and engine clock like USB, UART and so on. There are three PLLs in this chip, and the PLL clock source is from the external crystal input.
Page 137: Overview
N9H26 Technical Reference Manual 5.3.2 Overview HCLK_CKE MPLL HCLK MPLLFout ÷ 2 SRAM_CLK SRAM_CKE ÷ (HCLK234_N+1) APLL HCLK2 APLLFout HCLK3_CKE || HCLK4_CKE HCLK3 UPLL HCLK3_CKE UPLLFout HCLKsic SIC_CKE SYSTEM_S[4:0] HCLKfmi SYSTEM_N[3:0] NAND_CKE SYS_SW_DIV HCLKudc U20PHY_CKE SYS_CLK HCLKuhc USB11H_CKE HCLKemac EMAC_CKE HCLKvde (H.264 codec) VDE_CKE HCLKgve...
Page 138 N9H26 Technical Reference Manual SDIC_CLK VENC_CLK VENC_CKE VDEC_CLK VDEC_CKE ROT_CLK ROT_CKE HCLK1 HCLKedma20 EDMA20_CKE HCLKedma21 EDMA21_CKE HCLKedma22 EDMA22_CKE HCLKedma23 EDMA23_CKE HCLKedma24 EDMA24_CKE HCLKedma25 EDMA25_CKE HCLKedma26 EDMA26_CKE HCLK3 JPEG_CLK ÷ (JPG_N+1) JPEG_ECLK JPG_CKE HCLK4 HCLKcap0 SDIC_CLK ECLKcap0 CAP0_CKE HCLK4 HCLKcap1 CAP1_CKE Publication Release Date: Sept.
Page 139: Clock Source
N9H26 Technical Reference Manual 5.3.2.1 Clock Source Selector and Divider Clock Source Selector and Divider CLK_Mux4to1 CLK_SrcDiv8 CLK_SRC0 CLKo = CLKi/(Div_N+1) MPLLFout CLK_SRC1 CLK_SelOut CLK_SrcOut APLLFout CLK_SRC2 CLKi CLKo UPLLFout CLK_SRC3 Div_N[2:0] SEL[1:0] CLK_SEL[4:3] CLK_SEL[2:0] CLK_SEL[4:0] 5.3.2.2 DRAM_SW_DIV SDIC Clock Generator Clock Source MPLLFout DRAM_SrcCLK...
Page 140 N9H26 Technical Reference Manual 5.3.2.4 ADO_SW_DIV ADO (Audio) Engine Clock Generator Clock Source MPLLFout ADO_CLK ADO_SrcCLK CLK_DIVn Selector and APLLFout (÷ (ADO_N+1)) Divider UPLLFout ADO_S[4:0] ADO_N[7:0] ADO_CKE or I2S_CKE Publication Release Date: Sept. 10, 2018 - 140 - Revision V1.01...
Page 141 N9H26 Technical Reference Manual 5.3.2.5 I2S_SW_DIV I2S Clock Generator Clock Source MPLLFout I2S_CLK CLK_DIVn I2S_SrcCLK Selector and APLLFout (÷ (I2S_N+1)) Divider UPLLFout I2S_S[4:0] I2S_N[7:0] I2S_CKE 5.3.2.6 LCD_SW_DIV LCD Engine Clock Generator Clock Source MPLLFout ECLKlcd LCD_SrcCLK CLK_DIVn Selector and APLLFout (÷...
Page 142 N9H26 Technical Reference Manual 5.3.2.8 SEN_SW_DIV0 Sensor Clock Generator 0 Clock Source MPLLFout SEN_CLK0 CLK_DIVn SEN_SrcCLK Selector and APLLFout (÷ (SENSOR_N0+1)) Divider UPLLFout SENSOR_S0[4:0] SENSOR_N0[3:0] SEN_CKE0 Publication Release Date: Sept. 10, 2018 - 142 - Revision V1.01...
Page 143 N9H26 Technical Reference Manual 5.3.2.9 SEN_SW_DIV1 Sensor Clock Generator 1 Clock Source MPLLFout CLK_DIVn SEN_CLK1 SEN_SrcCLK Selector and APLLFout (÷ (SENSOR_N1+1)) Divider UPLLFout SENSOR_S1[4:0] SENSOR_N1[3:0] SEN_CKE1 5.3.2.10 USB_SW_DIV (USB1.1 Host Controller) USB_SW_DIV (USB 1.1 48MHz Clock Generator) Clock Source MPLLFout USB11_ USB_CLK CLK_DIVn...
Page 144 N9H26 Technical Reference Manual 5.3.2.12 U20PHY_SW_DIV U20PHY_SW_DIV (USB 2.0 Device PHY Clock) Clock Source MPLLFout USB20_CLK CLK_DIVn Selector and APLLFout 12MZ (÷ (U20PHY_N+1)) Divider UPLLFout U20PHY_SS[1:0] U20PHY_DS[2:0] U20PHY_N[3:0] U20PHY_CKE 5.3.2.13 H20PHY_SW_DIV H20PHY_SW_DIV (USB 2.0 Host PHY Clock) Clock Source MPLLFout HOST20_CLK CLK_DIVn Selector and...
Page 145 N9H26 Technical Reference Manual 5.3.2.15 UART1_SW_DIV UART 1 Clock Generator Clock Source MPLLFout ECLKuart1 CLK_DIVn UART1_SrcCLK Selector and APLLFout (÷ (UART1_N+1)) Divider UPLLFout UART1_S[4:0] UART1_N[2:0] UART_CKE[1] 5.3.2.16 SYS_SW_DIV System Clock Generator Clock Source MPLLFout SYS_CLK SYSTEM_SrcCLK CLK_DIVn Selector and APLLFout (÷...
Page 146 N9H26 Technical Reference Manual 5.3.2.18 KPI_SW_DIV KPI Clock Generator ECLKkpi KPI_SrcCLK CLK_DIVn (÷ (KPI_N+1)) KPI_N[6:0] KPI_CKE 5.3.2.19 PWM_SW_DIV PWM Engine Clock Generator Clock Source MPLLFout PWM_CLK CLK_DIVn PWM_SrcCLK Selector and APLLFout (÷ (PWM_N+1)) Divider UPLLFout PWM_S[4:0] PWM_N[7:0] PWM_CKE 5.3.2.20 TOUCH_SW_DIV TOUCH Engine Clock Generator Clock Source MPLLFout...
Page 147 N9H26 Technical Reference Manual 5.3.2.21 EMAC_SW_DIV EMAC Clock Generator EMACK_PHY_50M ECLKemac_ref Buffer CLK_DIVn ECLKemac_txrx (÷ (EMAC_N+1)) EMAC_N[4:0] EMAC_CKE Publication Release Date: Sept. 10, 2018 - 147 - Revision V1.01...
Page 148 N9H26 Technical Reference Manual 5.3.2.22 21 SDIO_SW_DIV SDIO Engine Clock Generator Clock Source MPLLFout SDIO_CLK CLK_ DIVn Selector and APLLFout (÷ (SDIO_N+1)) Divider UPLLFout SDIO_S[4:0] SDIO_N[7:0] SDIO_CKE 5.3.2.23 Others ECLKwdg WDOG_CKE ECLKtm0 TIMER0_CKE ECLKtm1 TIMER1_CKE Publication Release Date: Sept. 10, 2018 - 148 - Revision V1.01...
Page 149 N9H26 Technical Reference Manual The System Clock is the source of the AMBA bus, CPU and synchronous engine modules. The AMBA clock includes 5 AHB clock and 1 APB clock, HCLK, HCLK1, HCLK2, HCLK3, HCLK4 and the PCLK. The HCLK is divided by two from the system clock and the clock rate of HCLK is equal to or faster than the HCLK1 and HCLK2, HCLK3 and HCLK4.
Page 150: Registers Map
N9H26 Technical Reference Manual Registers Map Register Address Description Reset Value PWRCON CLK_BA + 00 System Power Down Control Register 0x00FF_FF03 AHBCLK CLK_BA + 04 Clock Enable Control Register 0x0000_011F APBCLK CLK_BA + 08 Clock Enable Control Register 0x0000_8100 CLKDIV0 CLK_BA + 0C Clock Divider Number Register 0 0x0000_0000...
Page 151 N9H26 Technical Reference Manual Power Down Control Register （PWRCON） The chip clock source is from an external crystal. The crystal oscillator can be control on/off by the register XTAL_EN. When turn off the crystal, the chip into power down state. To avoid outputting an unstable clock to system, clock controller implements a pre-scalar counter.
Page 152 N9H26 Technical Reference Manual Bits Descriptions 0 = Normal 1 = Indicate crystal enable change from low to high, the chip is resume from power down state. Write 0 = No action. 1 = Clear interrupt Crystal pre-divide control for Wake-up from power down mode. The chip will delay 256 x pre-scalar cycles after the reset signal to wait the Crystal to stable.
Page 153 N9H26 Technical Reference Manual AHB Devices Clock Enable Control Register （AHBCLK） These register bits are used to enable/disable clock for AMBA clock, AHB engine and peripheral Register Address Description Reset Value AHBCLK CLK_BA + 04 AHB IPs Clock Enable Control Register 0x0000_011F SDIO_CKE ADO_CKE...
Page 154 N9H26 Technical Reference Manual Bits Descriptions 0 = Disable 1 = Enable HCLK4 Clock Enable Control [24] HCLK4_CKE 0 = Disable 1 = Enable SD Card Controller Engine Clock Enable Control [23] SD_CKE 0 = Disable 1 = Enable NAND Controller Clock Enable Control [22] NAND_CKE 0 = Disable...
Page 155 N9H26 Technical Reference Manual Bits Descriptions 1 = Enable EDMA Controller Channel 1 Clock Enable Control [11] EDMA1_CKE 0 = Disable 1 = Enable EDMA Controller Channel 0 Clock Enable Control [10] EDMA0_CKE 0 = Disable 1 = Enable Reserved Reserved HCLK1 Clock Enable Control.
Page 156 N9H26 Technical Reference Manual APB Devices Clock Enable Control Register （APBCLK） These register bits are used to enable/disable clock for APB engine and peripheral. Register Address Description Reset Value APBCLK CLK_BA + 08 APB IPs Clock Enable Control Register 0x0000_8100 Reserved KPI_CKE TIC_CKE...
Page 157 N9H26 Technical Reference Manual Bits Descriptions 1 = Enable Convolution Encoder Clock Enable Control [11] CnvEnc_CKE 0 = Disable 1 = Enable TOUCH Clock Enable Control [10] TOUCH_CKE 0 = Disable 1 = Enable Timer1 Clock Enable Control 0 = Disable 1 = Enable Timer0 Clock Enable Control TIMER_CKE...
Page 158 N9H26 Technical Reference Manual Bits Descriptions 1 = Enable Publication Release Date: Sept. 10, 2018 - 158 - Revision V1.01...
Page 159 N9H26 Technical Reference Manual Clock Divider Register 0 （CLKDIV0） Before clock switch the related clock sources (pre-select and new-select) must be turn on. Register Address Description Reset Value CLKDIV0 CLK_BA + 0C Clock Divider Register 0x0000_0000 Reserved SENSOR_N0[3:0] SENSOR_S0[4:0] KPI_N[6:4] KPI_N[3:0] SYSTEM_N[3:0] Reserved...
Page 160 N9H26 Technical Reference Manual Bits Descriptions clock for KPI. ECLKkpi = KPI_SrcCLK / (KPI_N [6:0] + 1) [11:8] SYSTEM_N SYSTEM clock divide number from system clock source [7:6] Reserved Reserved KPI Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for KPI. Reserved KPI_SrcCLK = XIN System Clock Source Selection...
Page 161 N9H26 Technical Reference Manual Clock Divider Register 1 (CLKDIV1) Register Address Description Reset Value CLKDIV1 CLK_BA_+ 10 Clock Divider Register 0x0000_0000 ADO_N Reserved ADO_S VPOST_N Reserved VPOST_S Bits Descriptions Audio DAC Engine Clock Divide This field defines the clock divide number for clock divider to generate the engine clock for Audio- DAC.
Page 162 N9H26 Technical Reference Manual Bits Descriptions The actual clock divide number is (VPOST_N + 1). So, ECLKvpost = LCD_SrcCLK / (VPOST_N + 1) [7:5] Reserved Reserved VPOST Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for VPOST. 00: LCD_SrcCLK = XIN [4:3] 01: LCD_SrcCLK = MCLKout...
Page 163 N9H26 Technical Reference Manual Clock Divider Register 2 (CLKDIV2) Register Address Description Reset Value CLKDIV2 CLK_BA_+ 14 Clock Divider Register 2 0x0000_0018 SD_N Reserved U20PHY_SS SD_S U20PHY_N USB_N U20PHY_DS USB_S Bits Descriptions SD Engine Clock Divide This field defines the clock divide number for clock divider to generate the engine clock for SD controller.
Page 164 N9H26 Technical Reference Manual Bits Descriptions 001: SD_SrcCLK ÷ 2 010: SD_SrcCLK ÷ 3 011: SD_SrcCLK ÷ 4 100: SD_SrcCLK ÷ 5 101: SD_SrcCLK ÷ 6 110: SD_SrcCLK ÷ 7 111: SD_SrcCLK ÷ 8 USB20 PHY Clock Divider This field defines the clock divide number for clock divider to generate the 12MHz clock for embedded USB 2.0 PHY.
Page 165 N9H26 Technical Reference Manual Bits Descriptions 101: USB11_SrcCLK ÷ 6 110: USB11_SrcCLK ÷ 7 111: USB11_SrcCLK ÷ 8 Publication Release Date: Sept. 10, 2018 - 165 - Revision V1.01...
Page 166 N9H26 Technical Reference Manual Clock Divider Register 3 (CLKDIV3) Register Address Description Reset Value CLKDIV3 CLK_BA_+ 18 Clock Divider Register 0x0000_0000 ADC_N Reserved ADC_S UART1_N UART1_S UART0_N UART0_S Bits Descriptions ADC Engine Clock Divider This field defines the clock divide number for clock divider to generate the engine clock for ADC. [31:24] ADC_N The actual clock divide number is (ADC_N + 1).
Page 167 N9H26 Technical Reference Manual Bits Descriptions The actual clock divide number is (UART1_N + 1). So, ECLKuart1 = UART1_SrcCLK / (UART1_N + 1) UART1 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for UART1 controller. 00: UART1_SrcCLK = XIN [12:11] 01: UART1_SrcCLK = MCLKOut...
Page 168 N9H26 Technical Reference Manual Clock Divider Register 4 (CLKDIV4) Register Address Description Reset Value CLKDIV4 CLK_BA_+ 1C Clock Divider Register 0x0000_0000 Reserved CAP1_N JPG_N GPIO_N Reserved Reserved CAP0_N APB_N HCLK234_N CPU_N Bits Descriptions [31:30] Reserved Reserved Capture_1 Engine Clock Divider This field defines the clock divide number for clock divider to generate the engine clock for capture_1.
Page 169 N9H26 Technical Reference Manual Bits Descriptions APB Clock Divider Notice: APB_N[3] must be set to logic “HIGH” to configure clock divide number for enerating the PCLKof APB bus and controllers in APB bus. The actual clock divide number is (APB_N[2:0] + 1). So that, PCLK = HCLK1 / (APB_N[2:0] + 1) [11:8] APB_N...
Page 170 N9H26 Technical Reference Manual APLL Control Register （APLLCON） Register Address Description Reset Value APLLCON CLK_BA + 20 APLL Control Register 0x0000_5118 Reserved Reserved Reserved OUT_DV IN_DV IN_DV FB_DV Bits Descriptions [31:16] Reserved Reserved PLL ByPass Control [15] 0 = PLL at Normal mode 1 = By pass Fin (i.e.
Page 171 N9H26 Technical Reference Manual 5.3.2.24 Output Clock Frequency Setting    FOUT 5.3.2.25 Constrain:      FOUT 1500              FOUT Output Clock Frequency Input (Reference) Clock Frequency Input Divider (IN_DV) Feedback Divider (FB_DV ) OUT_DV = “00”...
Page 172 N9H26 Technical Reference Manual UPLL Control Register （UPLLCON） Register Address Description Reset Value UPLLCON CLK_BA + 24 UPLL Control Register 0x0000_5118 Reserved Reserved Reserved OUT_DV IN_DV IN_DV FB_DV Bits Descriptions [31:16] Reserved Reserved PLL ByPass Control [15] 0 = PLL at Normal mode 1 = By pass Fin (i.e.
Page 173 N9H26 Technical Reference Manual Bits Descriptions This field connected to pin M of PLL directly. 5.3.2.27 Output Clock Frequency Setting    FOUT 5.3.2.28 Constrain:      FOUT 1500        ...
Page 174 N9H26 Technical Reference Manual MPLL Control Register （MPLLCON） Register Address Description Reset Value MPLLCON CLK_BA + 28 MPLL Control Register 0x0000_5118 Reserved Reserved Reserved OUT_DV IN_DV IN_DV FB_DV Bits Descriptions [31:16] Reserved Reserved PLL ByPass Control [15] 0 = PLL at Normal mode 1 = By pass Fin (i.e.
Page 175 N9H26 Technical Reference Manual Bits Descriptions This field connected to pin M of PLL directly. 5.3.2.30 Output Clock Frequency Setting    FOUT 5.3.2.31 Constrain:      FOUT 1500        ...
Page 176 N9H26 Technical Reference Manual Test Clock Register (CLK_TREG) Register Address Description Reset Value CLK_TREG CLK_BA + 30 Test Clock Control Register 0x0000_0000 Reserved Reserved Reserved TEST_CKE SW_CLK TEST_SEL Bits Descriptions [31:18] Reserved Reserved Test clock output enable 1 = Test clock output enable TEST_CKE 0 = Disable the test clock Note: The test clock is output to the SEN_CLK pin.
Page 177 N9H26 Technical Reference Manual Bits Descriptions 01_0000 = HCLKcap0 01_0001 = 0 01_0010 = HCLKsic 01_0011 = HCLKnand 01_0100 = HCLKusbd 01_0101 = HCLKi2s 01_0110 = HCLKspu 01_0111 = HCLKvpost 01_1000 = HCLKtic 01_1001 = HCLKblt 01_1010 = HCLKedma1 01_1011 = HCLKedma0 01_1100 = HCLKusbh 01_1101 = HCLKsram 01_1110 = PCLK_CnvEnc...
Page 178 N9H26 Technical Reference Manual Bits Descriptions 11_1101 = HCLKedma3 11_1110 = HCLKedma4 11_1111 = SW_CLK Publication Release Date: Sept. 10, 2018 - 178 - Revision V1.01...
Page 179 N9H26 Technical Reference Manual AHB Devices Clock Enable Control Register2 （AHBCLK2） Register Address Description Reset Value AHBCLK2 CLK_BA + 34 AHB IPs Clock Enable Control Register2 0x0000_0000 Reserved Reserved Reserved ROT_CKE EDMA26_CKE EDMA25_CKE EDMA24_CKE EDMA23_CKE EDMA22_CKE EDMA21_CKE EDMA20_CKE VENC_CKE VDEC_CKE AAC_CKE EMAC_CKE Reserved...
Page 180 N9H26 Technical Reference Manual Bits Descriptions EDMA#2 Controller Channel 0 Clock Enable Control [11] EDMA20_CKE 0 = Disable 1 = Enable H.264 encoder Clock Enable Control [10] VENC_CKE 0 = Disable 1 = Enable H.264 decoder Clock Enable Control VDEC_CKE 0 = Disable 1 = Enable MDCT (AAC) Clock Enable Control...
Page 181 N9H26 Technical Reference Manual Clock Divider Register 5 (CLKDIV5) Register Address Description Reset Value CLKDIV5 CLK_BA+ 38 Clock Divider Register 0x0000_0000 TOUCH_N TOUCH_S TOUCH_S SENSOR_N1 SENSOR_S1 SENSOR_S1 PWM_N PWM_N PWM_S Bits Descriptions TOUCH Engine Clock Divider Bits [4:0] This field defines the clock divide number for clock divider to generate the engine clock for TOUCH ADC controller.
Page 182 N9H26 Technical Reference Manual Bits Descriptions SEN_CLK1 = SEN_SrcCLK1 / (SENSOR_N1 + 1) Sensor1 Clock Source Selection This field selects which clock is used to be the source of sensor clock. 00: SEN_SrcCLK1 = XIN [17:16] SENSOR_S1 01: SEN_SrcCLK1 = MCLKOut 10: SEN_SrcCLK1 = ACLKOut 11: SEN_SrcCLK1 = UCLKOut Sensor1 Clock Source Divide Selection...
Page 183 N9H26 Technical Reference Manual Clock Divider Register 6 (CLKDIV6) Register Address Description Reset Value CLKDIV6 CLK_BA+ 3C Clock Divider Register 0x0000_0000 Reserved H20PHY_N Reserved H20PHY_S Reserved OHCI_N Reserved OHCI_S Bits Descriptions [31:28] Reserved Reserved USB2.0 Host PHY Clock Divider Bits [3:0] This field defines the number for clock divider to generate the clock for USB2.0 Host PHY.
Page 184 N9H26 Technical Reference Manual Bits Descriptions USB2.0 OHCI Clock Divider Bits [3:0] This field defines the number for clock divider to generate the clock for USB2.0 OHCI controller. [11:8] OHCI_N OHCI_48M = OHCI_SrcCLK / (OHCI_N[3:0] + 1) OHCI Clock Source Selection This field selects which clock is used to be the source of sensor clock.
Page 185 N9H26 Technical Reference Manual Clock Divider Register 7 (CLKDIV7) Register Address Description Reset Value CLKDIV7 CLK_BA+ 40 Clock Divider Register 0x0000_0000 Reserved I2S_N Reserved I2S_S DRAM_N DRAM_S Bits Descriptions [31:24] Reserved Reserved I2S Clock Divider Bits [7:0] This field defines the number for clock divider to generate the clock for I2S. [23:16] I2S_N I2S_CLK = I2S_SrcCLK / (I2S_N[7:0] + 1)
Page 186 N9H26 Technical Reference Manual Bits Descriptions DDR_CLK = DRAM_SrcCLK / (DRAM_N[2:0] + 1) DRAM Clock (DDR_CLK) Source Selection This field selects which clock is used to be the source of DRAM controller. 00: DRAM_SrcCLK = XIN [4:3] 01: DRAM_SrcCLK = MCLKOut 10: DRAM_SrcCLK = ACLKOut 11: DRAM_SrcCLK = UCLKOut DRAM Clock Source Divide Selection...
Page 187 N9H26 Technical Reference Manual Clock Divider Register 8 (CLKDIV8) Register Address Description Reset Value CLKDIV8 CLK_BA+ 44 Clock Divider Register 0x0000_0000 Reserved Reserved Reserved SDIO_N SDIO_N SDIO_S Bits Descriptions [31:13] Reserved Reserved SDIO Engine Clock Divide This field defines the clock divide number for clock divider to generate the engine clock for SDIO controller.
Page 188: Sdram Controller Overview
N9H26 Technical Reference Manual 5.3.3 SDRAM Controller Overview The SDRAM Controller support SDR, DDR, Low-Power DDR and DDR2 type SDRAM. The memory device size type can be from 16M bit and up to 1G bits. Only 16-bit data bus width is supported. The total system memory size can be from 2M-byte and up to 256M-byte for different SDRAM configuration.
Page 189: Block Diagram
N9H26 Technical Reference Manual 5.3.4 Block Diagram 32-bit AXI master EAHB Arbiter AHB Arbiter for AHB1 (VPOST) for AHB5 AHBS_Type1 AXI_Slave#0 AHBS_Type2 ROM_BIST SDIC_Register IBR_ROM CtrlQueue#0 BA[2:0] 16 kbyte SDIC_DramType Addr[12:0] SDIC_FSM CS#,CAS#, (on-hot 28 states) CtrlQueue#1 RAS#,WE# SDIC_ SDIC_Refresh Scheduler SDIC_DramBist (auto_refresh)
Page 190: Sdram Control Timing
N9H26 Technical Reference Manual 5.3.5 SDRAM Control Timing The SDRAM Controller supports programmable CAS Latency and Refresh Rate control. The SDR- SDRAM initial sequence is also automatic trigger when the system power up. It also can control the SDRAM to enter self-refresh mode to reduce the power consumption in power-down mode. The SDRAM controller provides the fixed sequential burst type and some other programmable controls for the SDRAM operations include: ...
Page 191: Sdram Power-Up Sequence
N9H26 Technical Reference Manual 5.3.6 SDRAM Power-Up Sequence Before the SDRAM can be accessed for read or writing after power on, or when exiting deep power- down mode, an SDRAM device must be initialized by software to progress an initialization sequence. Because the SDR SDRAM, DDR, Low-Power DDR and DDR2 SDRAM require different initialization sequences and different parameters, the sequence is driven by software manually by using the registers SDCMD, SDMR, SDEMR, SDEMR2 and SDEMR3.
Page 192 N9H26 Technical Reference Manual 9. Apply two or more AUTOREFRESH commands. This is accomplished by writing 1 to REF_CMD of register SDCMD twice or more. The REF_CMD is auto cleared after SDRAM controller completes each CAS-BEFORE-RAS refresh command. 10. Apply a MRS (Mode Register Set) command to MR (Mode Register) with A8 low to set DDR SDRAM in normal operation without resetting the DLL.
Page 193: Sdram Interface Signals
N9H26 Technical Reference Manual SDRAM in normal operation without resetting the DLL. This is accomplished by writing appropriate value with bit [8] low to the register SDMR (SDRAM MODE Register). 14. Apply a MRS (Mode Register Set) command to EMR (Extended Mode Register) to enable OCD default state.
Page 194: Sdram Components Supported
N9H26 Technical Reference Manual 5.3.8 SDRAM Components Supported  16M-bit SDRAM Devices 1Mx16 with 2 banks: RA0 ~ RA10, CA0 ~ CA7 –  64M-bit SDRAM Devices 4Mx16 with 4 banks: RA0 ~ RA11, CA0 ~ CA7 –  128M-bit SDRAM 8Mx16 with 4 banks: RA0 ~ RA11, CA0 ~ CA8 –...
Page 195 N9H26 Technical Reference Manual 5.3.8.3 For DDR2 SDRAM Type BA2 BA1 BA0 A12 128M 12x9 R 8Mx1 256M 13x9 R 16Mx 512M 13x1 32Mx 13x1 64Mx Note: The AHB bus address HADDR prefixes have been omitted on the following tables. A13 ~ A00 are the Address pins of the SDRAM interface.
Page 196: Sdram Control Registers Map
N9H26 Technical Reference Manual 5.3.9 SDRAM Control Registers Map Register Address Description Reset Value SDIC_BA = 0xB000_3000 SDOPM SDRAM_BA + 00 SDRAM Controller Operation Mode Control Register 0x0003_00x6 SDCMD SDRAM_BA + 04 SDRAM Command Register 0x0000_0021 SDREF SDRAM_BA + 08 SDRAM Controller Refresh Control Register 0x0000_80FF SDRAM_BA + 0C...
Page 197: Register Details
N9H26 Technical Reference Manual 5.3.10 Register Details Publication Release Date: Sept. 10, 2018 - 197 - Revision V1.01...
Page 198 N9H26 Technical Reference Manual SDRAM Controller Operation Mode Control Register (SDOPM) Register Address Description Reset Value SDOPM SDRAM_BA + 00 SDRAM Controller Operation Mode Control Register 0x0003_0xx6 Reserved AutoAlign_PHASE[2:0] Reserved RdDataSel Reserved HW_RWC Phase_Shift_E DQS_PHASE OEDelay LowFreq PreActBnk AutoPDn _RST SEL_ Reserved DataClkSrc...
Page 199 N9H26 Technical Reference Manual Bits Descriptions If CL is 2, the read data output latency will be 2*t If CL is 3, the read data output latency will be t CL: CAS Latency. : Clock cycle time for LPDDR SDRAM. : Data output latency from clock for LPDDR SDRAM.
Page 200 N9H26 Technical Reference Manual Bits Descriptions Auto Pre-Charge Mode This bit controls if SDRAM controller will pre-charge all active banks while there is no new memory request. The SDRAM power consumption increases with the active bank number. If no new memory access request, the active bank can be pre-charge to save power, but the PchMode SDRAM controller may lose some performance.
Page 201 N9H26 Technical Reference Manual SDRAM Command Register (SDCMD) Register Address Description Reset Value SDCMD SDRAM_BA + 04 SDRAM Command Register 0x0000_0021 Reserved Reserved Reserved Reserved AutoExSelfRef SELF_REF REF_CMD PALL_CMD CKE_H InitState Bits Descriptions [31:6] Reserved Reserved Auto Exit Self-Refresh This controls if the SDRAM will exit self refresh mode automatically while the system interrupt occurred.
Page 202 N9H26 Technical Reference Manual Bits Descriptions CKE High This bit indicates the CKE is controlled by SDRAM controller state machine or always keeps high. CKE_H 0 = Set the CKE signal in normal state and controlled by the SDRAM controller state machine. (Default) 1 = Set the CKE signal keep in “high”...
Page 203 N9H26 Technical Reference Manual SDRAM Controller Refresh Control Register (SDREF) Register Address Description Reset Value SDREF SDRAM_BA + 08 SDRAM Controller Refresh Control Register 0x0000_80FF Reserved Reserved REF_EN REFRAT REFRAT Bits Descriptions [31:24] Reserved Reserved Refresh Period Counter Enable This bit controls if the refresh period counter is enabled. If refresh period counter is disabled, the SDRAM controller would never issue auto-refresh command to SDRAM automatically.
Page 204 N9H26 Technical Reference Manual SDRAM Size Register 0/1 （SDSIZE0/1） Register Address Description Reset Value SDSIZE0 SDRAM_BA + 10 SDRAM 0 Size Register 0x0000_000X SDSIZE1 SDRAM_BA + 14 SDRAM 1 Size Register 0x1000_0000 Reserved BASADDR BASADDR Reserved Reserved Reserved BUSWD DRAMSIZE Bits Descriptions [31:29] Reserved...
Page 205 N9H26 Technical Reference Manual Bits Descriptions SDRAM disable 128M 5.3.10.1 SDRAM TYPE (Byte) table SDR SDRAM DDR SDRAM DDR2 SDRAM SDRAM SIZE 16 bits 16 bits 16 bits 1Mx16 (16Mbits) Reserved Reserved Reserved Reserved Reserved 4Mx16 (64Mbits) 4Mx16 (64Mbits) 4Mx16 (64Mbits) 16MB 8Mx16 (128Mbits) 8Mx16 (128Mbits)
Page 206 N9H26 Technical Reference Manual SDRAM Mode Register （SDMR） The SDRAM mode registers is used to configure the Mode Register of SDRAM device. This Mode Register value will be applied to both SDRAM 0 and SDRAM 1 devices. Write this register, the SDRAM controller will generate a Load Mode Register (LMR) command to the SDRAM device.
Page 207 N9H26 Technical Reference Manual Bits Descriptions Reserved 2.5 (Inhibit) Reserved Reserved Reserved Reserved The CAS latency setting listed above is for reference. Before configuring SDRAM CAS latency, it’s necessary to confirm the CAS latency value supported by SDRAM device. Burst Type This bit indicates the burst type of SDRAM device is sequential or interleaved.
Page 208 N9H26 Technical Reference Manual SDRAM Extended Mode Register （SDEMR） The SDRAM Extended Mode Register is used to configure SDRAM Extend Mode Register. This Extended Mode Register value will be applied to both SDRAM 0 and SDRAM 1 devices. Write this register, the SDRAM controller will generate a Load Mode Register (LMR) command to the SDRAM.
Page 209 N9H26 Technical Reference Manual SDRAM Extended Mode Register 2 （SDEMR2） The SDRAM Extended Mode Register 2 is used to configure SDRAM Extend Mode Register 2. This Extended Mode Register 2 value will be applied to both SDRAM 0 and SDRAM 1 devices. Write this register, the SDRAM controller will generate a Load Mode Register (LMR) command to the SDRAM.
Page 210 N9H26 Technical Reference Manual SDRAM Extended Mode Register 3 （SDEMR3） The SDRAM Extended Mode Register 3 is used to configure SDRAM Extend Mode Register 3. This Extended Mode Register 3 value will be applied to both SDRAM 0 and SDRAM 1 devices. Write this register, the SDRAM controller will generate a Load Mode Register (LMR) command to the SDRAM.
Page 211 N9H26 Technical Reference Manual SDRAM Timing Control Register （SDTIME） This timing control register defines some SDRAM timing parameters that should be followed during SDRAM access. These timing parameters are SDRAM dependent. Refer SDRAM device’s data sheet to set these timing parameters is recommended. Register Address Description...
Page 212 N9H26 Technical Reference Manual Bits Descriptions HCLK: It’s the operating clock of SDRAM controller. ACTIVE to PRECHARGE Command Delay This timing defines the minimum delay latency from a valid ACTIVE command to PRECHARGE command. [11:8] tRAS RAS = t * (tRAS+1) HCLK HCLK: It’s the operating clock of SDRAM controller.
Page 213 N9H26 Technical Reference Manual Clock and DQS Delay Selection Register （CKDQSDS） Register Address Description Reset Value CKDQSDS SDRAM_BA + 34 Clock and DQS Delay Selection Register 0x0000_4440 Reserved Read_Wait_Cycle Reserved DataClk_DelaySel DQS1_SKEW DQS0_SKEW Reserved MCLK_OutDelaySel Bits Descriptions [31:26] Reserved Reserved 2’b00: no additional wait-cycle for data read.
Page 214 N9H26 Technical Reference Manual Bits Descriptions DQS0_CLKIn delay = DQS0_SKEW * Delay CLKMUX : It’s the gate delay of a CLKMUX gate. Delay CLKMUX [7:3] Reserved Reserved MCLK Output Delay Selection (for SDRAM-only, not for DDR/DDR2-SDRAM) This field controls the delay selection circuit for SDRAM clock MCLK generation. The delay value is controlled by the following equation: [2:0] MCLK_OutDelaySel...
Page 215 N9H26 Technical Reference Manual Write Address of DLL Mode Register (WDLLMODE） Register Address Description Reset Value DLLMODE SDRAM_BA + 54 SMIC DLL configuration 0x0000_0013 Reserved Reserved Reserved Reserved SEL_USE_DL DLL_EN DLL_PARAM Note: This register is for DLL control and write-only attribute. Bits Descriptions [31:5]...
Page 216 N9H26 Technical Reference Manual Read Address of DLL Mode Register (RDLLMODE） Register Address Description Reset Value DLLMODE SDRAM_BA + 58 SMIC DLL configuration 0x0000_0003 Reserved Reserved Reserved Reserved SEL_USE_DL DLL_EN DLL_PARAM Note: This register is for DLL control and read-only attribute. Bits Descriptions [31:5]...
Page 217 N9H26 Technical Reference Manual SDRAM Debug Register 1 （DBGREG1） Register Address Description Reset Value DBGREG SDRAM_BA + 70 SDRAM Debug Register 1 0x0000_0001 Reserved SRF_State FSM_CSTATE FSM_CSTATE FSM_CSTATE FSM_CSTATE Bits Descriptions [31:29] Reserved Reserved [28] SRF_State SDIC currently stays in Self-Refresh state. FSM Current State [27:0] FSM_CSTATE...
Page 218: Blitting Accelerator
N9H26 Technical Reference Manual 5.4 2D Blitting Accelerator 5.4.1 Overview The 2D blitting accelerator features are built on top of the FlashLite Bitmap rendering feature. It improves rendering performance of bitmap objects (source image) onto the frame buffer (destination image). There are two functions support.
Page 219: Figure 5.4-2 Architecture Diagram
N9H26 Technical Reference Manual Data Flow and Structure (2) Color Palette Source Format Transfer Filter FIFO Display Data Process Format Transfer Figure 5.4-2 Architecture Diagram Data Process TRANS_FLAG[0] : Transparency TRANS_FLAG[1] : Color Transform Color FILL_OP : Fill to a rectangle Palette FILL_STYLE[1] : No smooth...
Page 220: Blt Accelerator Control Register Map
N9H26 Technical Reference Manual 5.4.4 2D BLT Accelerator Control Register Map BLT_BA = 0xB100_D000 R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written Register Address Description Reset Value BLT_BA SET2DA BLT_BA+0x000 2D Accelerator Enable Set Up Register 0x0000_0000 SFMT...
Page 221 N9H26 Technical Reference Manual BMMU_TTB BLT_BA+0x084 BLT MMU Translation Table Base Register 0x0000_0000 BMMU_PFTVA BLT_BA+0x088 BLT MMU Page Fault Virtual Address Reg. 0x0000_0000 BMMU_CMD BLT_BA+0x08C BLT MMU Resume and Invalidate Command 0x0000_0000 BMMU_L1PT0 BLT_BA+0x090 TLB Level-One Page Table Entry 0 Descriptor 0x0000_0000 BMMU_L1PT1 BLT_BA+0x094...
Page 222: Register Description
N9H26 Technical Reference Manual 5.4.5 Register Description 2D Blitting Accelerator Enable Set Up Register (SET) Register Offset Description Reset Value BLT_BA+0x000 Enable Set Up Register 0x0000_0000 Reserved Reserved Reserved Fill_OP FILL_STYLE TRCOLOR TRANS_FLAG S_ALPHA FILL_BLEND L_ENDIAN BLIT_EN Descriptions Bits [31:12] Reserved Reserved 1 : Fill operation to a rectangle in the frame buffer is request...
Page 223 N9H26 Technical Reference Manual Descriptions Bits 0x5 : Undefined 0x4 : Undefined 0x3 : Enable Per-Pixel Transparency and Do ColorTransform Compute the color values by the ColorTransform formula, and enable Per-Pixel Transparency in the source image 0x2 : ColorTransform Compute the color values by the following formula: New red value = (old red value * redMultiplier) + redOffset New green value = (old green value * greenMultiplier) + greenOffset New blue value = (old blue value * blueMultiplier) + blueOffset...
Page 224 N9H26 Technical Reference Manual Pixel Format of Source Bitmap Register (SFMT) Register Offset Description Reset Value SFMT BLT_BA+0x004 Pixel Format of Source Bitmap Register 0x0000_0000 Reserved Reserved Reserved Reserved RGB_bpp8 RGB_bpp4 RGB_bpp2 RGB_bpp1 RGB565 ARGB8888 Bits Descriptions [31:6] Reserved Reserved BitmapPixelFormat_bpp8_clutRGB RGB_bpp8 1 : Format select...
Page 225 N9H26 Technical Reference Manual Pixel Format of Destination Bitmap Register (DFMT) Register Offset Description Reset Value DFMT BLT_BA+0x008 Pixel Format of Destination Bitmap Register 0x0000_0000 Reserved Reserved Reserved Reserved DRGB555 DRGB565 DARGB 8888 Bits Descriptions [31:3] Reserved Reserved DisplayFormat_RGB555_16 (16 bit RGB 0555 format) DRGB555 1: Format select 0: Format without select...
Page 226 N9H26 Technical Reference Manual BLT Interrupt Control and Status Register Register Offset Description Reset Value BLTINTCR BLT_BA+0x00C BLT Interrupt Control and Status Register 0x0000_0000 PMS_INTS PFT_INTS TABORT BLT_ERR BLT_INTE BLT_INTS Bits Descriptions [31:6] Reserved Reserved BLT MMU Page Miss Interrupt Status PMS_INTS 0 = No Page Miss Interrupt 1 = Page Miss Interrupt Generated...
Page 227 N9H26 Technical Reference Manual Multiplier and Offset Register (MLT) Register Offset Description Reset Value MLTA BLT_BA+0x010 Alpha Multiplier and Offset Register 0x0000_0000 MLTR BLT_BA+0x014 Red Multiplier and Offset Register 0x0000_0000 MLTG BLT_BA+0x018 Green Multiplier and Offset Register 0x0000_0000 MLTB BLT_BA+0x01c Blue Multiplier and Offset Register 0x0000_0000 Offset [15:8]...
Page 228 N9H26 Technical Reference Manual (Width, Height) of (Source, Destination) Register Register Offset Description Reset Value SWIDTH BLT_BA+0x020 Width of Source Register 0x0000_0000 SHEIGHT BLT_BA+0x024 Height of Source Register 0x0000_0000 DWIDTH BLT_BA+0x028 Width of Destination Register 0x0000_0000 DHEIGHT BLT_BA+0x02C Height of Destination Register 0x0000_0000 Reserved Reserved...
Page 229 N9H26 Technical Reference Manual Transform Element Register Register Offset Description Reset Value ELEMENTA BLT_BA+0x030 Transform Element A Register 0x0000_0000 ELEMENTB BLT_BA+0x034 Transform Element B Register 0x0000_0000 ELEMENTC BLT_BA+0x038 Transform Element C Register 0x0000_0000 ELEMENTD BLT_BA+0x03C Transform Element D Register 0x0000_0000 ELEMENT [31:24] ELEMENT [23:16] ELEMENT [15:8]...
Page 230 N9H26 Technical Reference Manual Source Remap Start Address Register Register Offset Description Reset Value SADDR BLT_BA+0x040 Source Remap Start Address Register 0x0000_0000 SADDR [31:24] SADDR [23:16] SADDR [15:8] SADDR [7:0] Bits Descriptions [31:0] SADDR Source Remap Start Address Publication Release Date: Sept. 10, 2018 - 230 - Revision V1.01...
Page 231 N9H26 Technical Reference Manual Frame Buffer Start Address Register Register Offset Description Reset Value DADDR BLT_BA+0x044 Frame Buffer Start Address Register 0x0000_0000 DADDR [31:24] DADDR [23:16] DADDR [15:8] DADDR [7:0] Bits Descriptions [31:0] DADDR Frame Buffer Start Address Publication Release Date: Sept. 10, 2018 - 231 - Revision V1.01...
Page 232 N9H26 Technical Reference Manual Stride Register Register Offset Description Reset Value SSTRIDE BLT_BA+0x048 Source Stride Register 0x0000_0000 DSTRIDE BLT_BA+0x04C Destination Stride Register 0x0000_0000 Reserved Reserved STRIDE [15:8] STRIDE [7:0] Bits Descriptions [31:16] Reserved Reserved Stride of row bytes. [15:0] STRIDE Word alignment is needed for rgb565 and color palette 1, 2, 4 and 8 bits.
Page 233 N9H26 Technical Reference Manual Offset of Source (X/Y) Register Register Offset Description Reset Value OFFSETSX BLT_BA+0x050 Offset of Source X Register 0x0000_0000 OFFSETSY BLT_BA+0x054 Offset of Source Y Register 0x0000_0000 OFFSETXY [31:24] OFFSETXY [23:16] OFFSETXY [15:8] OFFSETXY [7:0] Bits Descriptions The X,Y offset into the source to start rendering from [31:0] OFFSETXY...
Page 234 N9H26 Technical Reference Manual RGB565 Transparent Color Register Register Offset Description Reset Value TRCOLOR BLT_BA+0x058 RGB565 Transparent Color Register 0x0000_0000 Reserved Reserved TRCOLOR [15:8] TRCOLOR [7:0] Bits Descriptions [15:0] TRCOLOR RGB565 Transparent Color Publication Release Date: Sept. 10, 2018 - 234 - Revision V1.01...
Page 235 N9H26 Technical Reference Manual ARGB Color Values for Fill Operation Register Register Offset Description Reset Value FILLARGB BLT_BA+0x060 ARGB Color Values for Fill Operation Register 0x0000_0000 FILL_A FILL_R FILL_G FILL_B Bits Descriptions [31:24] FILL_A Alpha Values for Fill to a rectangle Operation. [23:16] FILL_R Red Color Values for Fill to a rectangle Operation.
Page 236 N9H26 Technical Reference Manual Color Palette Index Register Register Offset Description Reset Value BLT_BA 0x400, PALETTE 0x404 Color Palette Index Register 0x0000_0000 ~ 0x7FF Bits Descriptions [31:24] Alpha value of Color Palette [23:16] Red value of Color Palette [15:8] Green value of Color Palette [7:0] Blue value of Color Palette Publication Release Date: Sept.
Page 237: Blt Accelerator Memory Management Unit (Blt Mmu)
N9H26 Technical Reference Manual 5.4.6 2D BLT Accelerator Memory Management Unit (BLT MMU) BLT MMU converts the address mapping from virtual addresses to physical addresses during BLT data accesses or processing. Basically, a virtual memory up to 4G bytes can be translated and mapped onto the limited physical memory dependent on different specific applications.
Page 238: Blt Tlb Structure And Blt Mmu Operation Flow
N9H26 Technical Reference Manual 5.4.7 BLT TLB Structure and BLT MMU Operation Flow BLT TLB BLT TLB adopts the 2-layer TLB structures to improve the hit rates of virtual address translation. A 2- layer TLB structures are implemented with 4 sets of 16-entry per layer-1-TLB and 4 sets of 256-entry per layer-2-TLB.
Page 239: Figure 5.4-4 Blt Mmu Operation Flow
N9H26 Technical Reference Manual Figure 5.4-4 BLT MMU Operation Flow Publication Release Date: Sept. 10, 2018 - 239 - Revision V1.01...
Page 240 N9H26 Technical Reference Manual 5.4.7.1 BLT MMU Address Translation Basically, MMU translates virtual addresses into physical addresses for the external memory access, and also performs access permission checking. However, N9H26 BLT MMU only translates the virtual address mapping without the access permission checking. A mechanism of MMU table-walking hardware is used to add entries to the TLB.
Page 241 N9H26 Technical Reference Manual Publication Release Date: Sept. 10, 2018 - 241 - Revision V1.01...
Page 242: Blt Mmu Control Registers Map
N9H26 Technical Reference Manual 5.4.8 BLT MMU Control Registers Map BLT_BA = 0xB100_C000 R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written Register Address Description Reset Value BMMU_CR BLT_BA + 080 BLT MMU Control Register 0x0000_0000 BMMU_TTB...
Page 243 N9H26 Technical Reference Manual BLT MMU Control Register Register Address Description Reset Value BMMU_CR BLT_BA + 080 BLT MMU Control Register 0x0000_0000 Reserved Reserved MMU_RST Reserved PMS_EN PFT_EN Reserved MAIN_TLB Reserved MAIN_EN MMU_EN Bits Descriptions [31:17] Reserved Reserved 1 = Reset BLT MMU Control [16] MMU_RST 0 = Not reset BLT MMU Control...
Page 244 N9H26 Technical Reference Manual BLT MMU Translation Table Base Address Register Register Address Description Reset Value BMMU_TTB BLT_BA + 084 BLT MMU Translation Table Base Address 0x0000_0000 TTB Address [31:24] TTB Address [23:16] TTB Address [15:8] TTB Address [7:0] Bits Descriptions 32-bit Translation Table Base Address [31:0]...
Page 245 N9H26 Technical Reference Manual BLT MMU Page Fault Virtual Address Register Register Address Description Reset Value BMMU_PFTVA BLT_BA + 088 BLT MMU Page Fault Virtual Address 0x0000_0000 Page Fault Virtual Address [31:24] Page Fault Virtual Address [23:16] Page Fault Virtual Address [15:8] Page Fault Virtual Address [7:0] Bits Descriptions...
Page 246 N9H26 Technical Reference Manual BLT MMU Resume and Invalidate Command Register Register Address Description Reset Value BMMU_CMD BLT_BA + 08C BLT MMU Resume and Invalidate Command 0x0000_0000 Reserved Reserved MTLB_FAIL MTLB_FINISH Reserved Reserved FLUSH INVALID RESUME Bits Descriptions [31:18] Reserved Reserved Flush BLT MMU Main TLB Entries Pass/Fail Status (Read Only) [17]...
Page 247 N9H26 Technical Reference Manual BLT MMU Level-one Page Table Entry 0 Register Register Address Description Reset Value BMMU_L1PT0 BLT_BA + 090 BLT MMU Level-One Page Table Entry 0 Register 0x0000_0000 Level-One Page Table Entry 0 [31:24] Level-One Page Table Entry 0 [23:16] Level-One Page Table Entry 0 [15:8] Level-One Page Table Entry 0 [7:0] Bits...
Page 248 N9H26 Technical Reference Manual BLT MMU Level-one Page Table Entry 1 Register Register Address Description Reset Value BMMU_L1PT1 BLT_BA + 094 BLT MMU Level-One Page Table Entry 1 Register 0x0000_0000 Level-One Page Table Entry 1 [31:24] Level-One Page Table Entry 1 [23:16] Level-One Page Table Entry 1 [15:8] Level-One Page Table Entry 1 [7:0] Bits...
Page 249 N9H26 Technical Reference Manual BLT MMU Level-one Page Table Entry 2 Register Register Address Description Reset Value BMMU_L1PT2 BLT_BA + 098 BLT MMU Level-One Page Table Entry 2 Register 0x0000_0000 Level-One Page Table Entry 2 [31:24] Level-One Page Table Entry 2 [23:16] Level-One Page Table Entry 2 [15:8] Level-One Page Table Entry 2 [7:0] Bits...
Page 250 N9H26 Technical Reference Manual BLT MMU Level-one Page Table Entry 3 Register Register Address Description Reset Value BMMU_L1PT3 BLT_BA + 09C BLT MMU Level-One Page Table Entry 3 Register 0x0000_0000 Level-One Page Table Entry 3 [31:24] Level-One Page Table Entry 3 [23:16] Level-One Page Table Entry 3 [15:8] Level-One Page Table Entry 3 [7:0] Bits...
Page 251 N9H26 Technical Reference Manual BLT MMU Level-one Page Table Entry 4 Register Register Address Description Reset Value BMMU_L1PT4 BLT_BA + 0A0 BLT MMU Level-One Page Table Entry 4 Register 0x0000_0000 Level-One Page Table Entry 4 [31:24] Level-One Page Table Entry 4 [23:16] Level-One Page Table Entry 4 [15:8] Level-One Page Table Entry 4 [7:0] Bits...
Page 252 N9H26 Technical Reference Manual BLT MMU Level-one Page Table Entry 5 Register Register Address Description Reset Value BMMU_L1PT5 BLT_BA + 0A4 BLT MMU Level-One Page Table Entry 5 Register 0x0000_0000 Level-One Page Table Entry 5 [31:24] Level-One Page Table Entry 5 [23:16] Level-One Page Table Entry 5 [15:8] Level-One Page Table Entry 5 [7:0] Bits...
Page 253 N9H26 Technical Reference Manual BLT MMU Level-one Page Table Entry 6 Register Register Address Description Reset Value BMMU_L1PT6 BLT_BA + 0A8 BLT MMU Level-One Page Table Entry 6 Register 0x0000_0000 Level-One Page Table Entry 6 [31:24] Level-One Page Table Entry 6 [23:16] Level-One Page Table Entry 6 [15:8] Level-One Page Table Entry 6 [7:0] Bits...
Page 254 N9H26 Technical Reference Manual BLT MMU Level-one Page Table Entry 7 Register Register Address Description Reset Value BMMU_L1PT7 BLT_BA + 0AC BLT MMU Level-One Page Table Entry 7 Register 0x0000_0000 Level-One Page Table Entry 7 [31:24] Level-One Page Table Entry 7 [23:16] Level-One Page Table Entry 7 [15:8] Level-One Page Table Entry 7 [7:0] Bits...
Page 255 N9H26 Technical Reference Manual BLT MMU Current Virtual Address Register Register Address Description Reset Value BMMU_CVA BLT_BA + 0B0 BLT MMU Current Virtual Address Register 0x0000_0000 Current Virtual Address [31:24] Current Virtual Address [23:16] Current Virtual Address [15:8] Current Virtual Address [7:0] Bits Descriptions 32-bit Current Virtual Address...
Page 256 N9H26 Technical Reference Manual BLT MMU Current Virtual Page Number Register Register Address R/W Description Reset Value BMMU_CVPN BLT_BA + 0B4 BLT MMU Current Virtual Page Number Register 0x0000_0000 Current Virtual Page Number [31:24] Current Virtual Page Number [23:16] Current Virtual Page Number [15:8] Current Virtual Page Number [7:0] Bits Descriptions...
Page 257 N9H26 Technical Reference Manual BLT MMU Current Physical Address Register Register Address Description Reset Value BMMU_CPA BLT_BA + 0B8 BLT MMU Current Physical Address Register 0x0000_0000 Current Physical Address [31:24] Current Physical Address [23:16] Current Physical Address [15:8] Current Physical Address [7:0] Bits Descriptions 32-bit Current Physical Address...
Page 258 N9H26 Technical Reference Manual BLT MMU Current Physical Page Number Register Register Address R/W Description Reset Value BMMU_CPPN BLT_BA + 0BC BLT MMU Current Physical Page Number Register 0x0000_0000 Current Physical Page Number [31:24] Current Physical Page Number [23:16] Current Physical Page Number [15:8] Current Physical Page Number [7:0] Bits Descriptions...
Page 259: Vpe Video Data Processing Engine
N9H26 Technical Reference Manual 5.5 VPE Video Data Processing Engine 5.5.1 Overview Video Data Processing Engine (VPE) contains the acceleration engines for still images and video movies. The first function is for the image/video data format conversion and the second function is for the image/video 2D rotation or the coordinate transformation.
Page 260: Figure 5.5-1 Vpe Input Buffers
N9H26 Technical Reference Manual                (int)             In order to receive the planar YUV data from frame buffers, VPE needs some 8x8 block-based input buffers to hold the burst data.
Page 261 N9H26 Technical Reference Manual VPE supports all types of block-based data from JPEG decoder or video decoder. Video Decoder block types and block sequences are listed as follows: Block Data Y/Cb/Cr Output Pattern Type Format MCU H x V Block Sequence PL400 PL420 PL422...
Page 262 N9H26 Technical Reference Manual Data Y/Cb/Cr Block Output Pattern Format MCU H x V Type Block Sequence PL444 PK422/R Bloc Data Output Pattern Format Block Sequence MCU H x V Type PK422 RGB555 RGB565 RGB888 5.5.2.1 Video Playback Mode VPE reads the source video data, with a format as planar YUV/YCbCr 444/422/420, packet YUV 422 or RGB.
Page 263 N9H26 Technical Reference Manual 5.5.2.3 Bilinear Filter for Interpolation/Decimation and Up/Down-scaling Bilinear interpolation/decimation filters for smoothly up/down-scaling are implemented inside VPE. 4 points are precisely chosen from the source pictures, and the position of target pixels are calculated with the following bilinear filter formula to render the pixels. ...
Page 264: Vpe Picture Format
N9H26 Technical Reference Manual 5.5.3 VPE Picture Format Source Planar YUV 444/422/420 Destination Packet YUV422/RGB Destination Destination Right Source Left Source Right Left Line Line Offset Line Line Offset Offset Offset SORC Width DEST Width Format Convert & DDA & ROT Left_Line_Offset+Width+Right_Line_Offset Left_Line_Offset+Width+Right_Line_Offset Publication Release Date: Sept.
Page 265: Vpe Bilinear Filter With Dda Up/Down-Sampling
N9H26 Technical Reference Manual 5.5.4 VPE Bilinear Filter with DDA Up/Down-Sampling According to the sampling theory, a pre-filter had better be inserted before the down-sampling or decimation process, whereas a post-filter had better be added after the up-sampling or interpolation. For this reason, VPE implements bilinear decimation/interpolation filters with DDA up/down-sampling to improve better image qualities both for the down-scaling and the up-scaling pictures.
Page 266: Video Processing Engine Control Registers Map
N9H26 Technical Reference Manual 5.5.5 Video Processing Engine Control Registers Map VPE_BA = 0xB100_C800 R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written Register Address Description Reset Value VPE_TG VPE_BA + 000 Video Process Engine (VPE) Trigger Control 0x0000_0000 Register...
Page 267: Registers Description
N9H26 Technical Reference Manual 5.5.6 Registers Description Publication Release Date: Sept. 10, 2018 - 267 - Revision V1.01...
Page 268 N9H26 Technical Reference Manual Video Processing Engine Trigger Control Register Register Address Description Reset Value VPE_TG VPE_BA + 000 Video Process Engine Trigger Control Reg. 0x0000_0000 Reserved Reserved Reserved Reserved Bits Descriptions [31:1] Reserved Reserved Trigger Video Process Engine Operation (Software trigger mode) 1 = Start VPE operation, automatically cleared when VPE is completed.
Page 269 N9H26 Technical Reference Manual Video Processing Engine Source Planar Y or Packet YUV 422 Start Address Register Register Address Description Reset Value Video Process Engine Source Planar Y or Packet YUV VPE_PLYA_PK VPE_BA + 004 0x0000_0000 422 Start Address Planar Y/Packet YUV 422 Address [31:24] Planar Y/Packet YUV 422 Address [23:16] Planar Y/Packet YUV 422 Address [15:8] Planar Y/Packet YUV 422 Address [7:0]...
Page 270 N9H26 Technical Reference Manual Video Processing Engine U Space Planar Type Start Address Register Register Address R/W Description Reset Value VPE_PLUA VPE_BA + 008 Video Process Engine U Space Planar Type Start Address 0x0000_0000 Planar U Address [31:24] Planar U Address [23:16] Planar U Address [15:8] Planar U Address [7:0] Bits...
Page 271 N9H26 Technical Reference Manual Video Processing Engine V Space Planar Type Start Address Register Register Address R/W Description Reset Value VPE_PLVA VPE_BA + 00C Video Process Engine V Space Planar Type Start Address 0x0000_0000 Planar V Address [31:24] Planar V Address [23:16] Planar V Address [15:8] Planar V Address [7:0] Bits...
Page 272 N9H26 Technical Reference Manual Video Processing Engine Interrupt Status Register Register Address Description Reset Value VPE_INTS VPE_BA + 010 Video Process Engine Interrupt Status Reg. 0x0000_0000 Reserved Reserved Reserved Reserved TA_INTS DE_INTS MB_INTS PG_MISS PF_INTS VP_INTS Bits Descriptions [31:6] Reserved Reserved VPE DMA Target Abort or Data Abort Interrupt Status 0 = No DMA target abort interrupt occur.
Page 273 N9H26 Technical Reference Manual Video Processing Engine Source Packet/Planar Y Left/Right Line Offset Register (Pixel Unit) Register Address R/W Description Reset Value VPE_SLORO VPE_BA + 014 Source Packet/Planar Y Left Line and Right Line Offset 0x0000_0000 Reserved Source Packet/Planar Y Left Line Offset [12:8] Source Packet/Planar Y Left Line Offset [7:0] Reserved Source Packet/Planar Y Right Line Offset [12:8]...
Page 274 N9H26 Technical Reference Manual Video Processing Engine Vertical DDA N/M Divider (Divider for DDA Scaling Up/Down) Register Address Description Reset Value VPE_VYDSF VPE_BA + 018 Vertical Divider for DDA Scaling Up/Down 0x0000_0000 VSF_N [12:8] VSF_N [7:0] VSF_M [12:8] VSF_M [7:0] Bits Descriptions 13-bit Vertical N Scaling Factor...
Page 275 N9H26 Technical Reference Manual Video Processing Engine Horizontal DDA N/M Divider (Divider for DDA Scaling Up/Down) Register Address Description Reset Value VPE_HXDSF VPE_BA + 01C Horizontal Divider for DDA Scaling Up/Down 0x0000_0000 HSF_N [12:8] HSF_N [7:0] HSF_M [12:8] HSF_M [7:0] Bits Descriptions 13-bit Horizontal N Scaling Factor...
Page 276 N9H26 Technical Reference Manual Video Processing Engine Command Control Register Register Address Description Reset Value VPE_CMD VPE_BA + 020 Video Process Engine Command Control Reg. 0x4000_0000 CCIR601 SORC (Read Only) LEVEL TRACE DEST SORC BLOCK SEQUENCE OPERATE COMMAND uTLB-SET Y_Round X_Round SINGLE ENABLE...
Page 277 N9H26 Technical Reference Manual Bits Descriptions The Different Types of Block Sequences of Source Data Block sequences are defined as follows: 0000 = Video decoder block type is Y Luminance only. (PL YUV 400 Format) 0001 = Video decoder block type is PL YCbCr420. (Planar YUV 420 Format) 0010 = Video decoder block type is PL YCbCr420.
Page 278 N9H26 Technical Reference Manual Bits Descriptions 1 = Single Write Buffer Structure Line Mode Output 2-D Average Filter Enable (MODE = 01) [10] ENABLE 0 = Turn off the Line Mode 2-D Average Filter. 1 = Turn on the Line Mode 2-D Average Filter. Line Mode Input 1-D Average Filter Tap Coefficients (MODE = 01) BYPASS 0 = Filter is turned on during DDA up/down-scaling.
Page 279 N9H26 Technical Reference Manual Video Processing Engine Data Format Conversion Packet Format Destination Start Address Register Address R/W Description Reset Value VPE_DEST_PK VPE_BA + 024 Data Format Packet Destination Start Address 0x0000_0000 Data Format Packet Destination address [31:24] Data Format Packet Destination address [23:16] Data Format Packet Destination address [15:8] Data Format Packet Destination address [7:0] Bits...
Page 280 N9H26 Technical Reference Manual VPE Destination Packet Format Data Left/Right Line Offset Register (Pixel Unit) Register Address R/W Description Reset Value VPE_DLORO VPE_BA + 028 R/W Destination Packet Data Left Line Offset and Right Line Offset 0x0000_0000 Reserved Destination Packet Left Line Offset [12:8] Destination Packet Left Line Offset [7:0] Reserved Destination Packet Right Line Offset [12:8]...
Page 281 N9H26 Technical Reference Manual Video Processing Engine Reset Control Register Register Address Description Reset Value VPE_RESET VPE_BA + 034 Video Process Engine Reset Control Register 0x0000_0000 Reserved Reserved Reserved Reserved RST_FIFO RESET Bits Descriptions RESET VPE FIFO Control RST_FIFO 0 = Not reset VPE FIFO Control 1 = Reset VPE FIFO Control RESET VPE Operation RESET...
Page 282: Video Processing Engine Memory Management Unit (Vpe Mmu)
N9H26 Technical Reference Manual 5.5.7 Video Processing Engine Memory Management Unit (VPE MMU) VPE MMU converts the address mapping from virtual addresses to physical addresses during VPE data accesses or processing. Basically, a virtual memory up to 4G bytes can be translated and mapped onto the limited physical memory dependent on different specific applications.
Page 283 N9H26 Technical Reference Manual 20 19 The first layer 16-entry TLB 20-bit Virtual Page Number 20-bit Physical Page Number 8-bit VPN 12-bit VPN 20-bit Physical Page Number The second layer 256-entry TLB SRAM Publication Release Date: Sept. 10, 2018 - 283 - Revision V1.01...
Page 284 N9H26 Technical Reference Manual 5.5.7.3 VPE MMU Operation Flow Publication Release Date: Sept. 10, 2018 - 284 - Revision V1.01...
Page 285 N9H26 Technical Reference Manual 5.5.7.4 VPE MMU Address Translation Basically, MMU translates virtual addresses into physical addresses for the external memory access, and also performs access permission checking. However, N9H26 VPE MMU only translates the virtual address mapping without the access permission checking. A mechanism of MMU table-walking hardware is used to add entries to the TLB.
Page 286 N9H26 Technical Reference Manual Publication Release Date: Sept. 10, 2018 - 286 - Revision V1.01...
Page 287: Vpe Mmu Control Registers Map
N9H26 Technical Reference Manual 5.5.8 VPE MMU Control Registers Map VPE_BA = 0xB100_C800 R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written Register Address Description Reset Value VMMU_CR VPE_BA + 080 R/W VPE MMU Control Register 0x0000_0000 VMMU_TTB...
Page 288 N9H26 Technical Reference Manual VPE MMU Control Registers Register Address Description Reset Value VMMU_CR VPE_BA + 080 VPE MMU Control Register 0x0000_0000 Reserved Reserved Reserved Reserved MAIN_TLB Reserved MAIN_EN MMU_EN Bits Descriptions [31:5] Reserved Reserved VPE MMU Main TLB Service Channels MAIN_TLB 1 = VPE MMU Main TLB service for the source and destination DMA channels.
Page 289 N9H26 Technical Reference Manual VPE MMU Translation Table Base Address Register Register Address Description Reset Value VMMU_TTB VPE_BA + 084 VPE MMU Translation Table Base Address 0x0000_0000 TTB Address [31:24] TTB Address [23:16] TTB Address [15:8] TTB Address [7:0] Bits Descriptions 32-bit Translation Table Base Address [31:0]...
Page 290 N9H26 Technical Reference Manual VPE MMU Page Fault Virtual Address Register Register Address Description Reset Value VMMU_PFTVA VPE_BA + 088 VPE MMU Page Fault Virtual Address 0x0000_0000 Page Fault Virtual Address [31:24] Page Fault Virtual Address [23:16] Page Fault Virtual Address [15:8] Page Fault Virtual Address [7:0] Bits Descriptions...
Page 291 N9H26 Technical Reference Manual VPE MMU Resume and Invalidate Command Register Register Address Description Reset Value VMMU_CMD VPE_BA + 08C VPE MMU Resume and Invalidate Command 0x0000_0000 Reserved Reserved MTLB_FAIL MTLB_FINISH Reserved Reserved FLUSH INVALID RESUME Bits Descriptions [31:18] Reserved Reserved Flush VPE MMU Main TLB Entries Pass/Fail Status (Read Only) [17]...
Page 292 N9H26 Technical Reference Manual VPE MMU Level-one Page Table Entry 0 Register Register Address R/W Description Reset Value VMMU_L1PT0 VPE_BA + 090 VPE MMU Level-One Page Table Entry 0 Register 0x0000_0000 Level-One Page Table Entry 0 [31:24] Level-One Page Table Entry 0 [23:16] Level-One Page Table Entry 0 [15:8] Level-One Page Table Entry 0 [7:0] Bits...
Page 293 N9H26 Technical Reference Manual VPE MMU Level-one Page Table Entry 1 Register Register Address Description Reset Value VMMU_L1PT1 VPE_BA + 094 VPE MMU Level-One Page Table Entry 1 Register 0x0000_0000 Level-One Page Table Entry 1 [31:24] Level-One Page Table Entry 1 [23:16] Level-One Page Table Entry 1 [15:8] Level-One Page Table Entry 1 [7:0] Bits...
Page 294 N9H26 Technical Reference Manual VPE MMU Level-one Page Table Entry 2 Register Register Address Description Reset Value VMMU_L1PT2 VPE_BA + 098 VPE MMU Level-One Page Table Entry 2 Register 0x0000_0000 Level-One Page Table Entry 2 [31:24] Level-One Page Table Entry 2 [23:16] Level-One Page Table Entry 2 [15:8] Level-One Page Table Entry 2 [7:0] Bits...
Page 295 N9H26 Technical Reference Manual VPE MMU Level-one Page Table Entry 3 Register Register Address Description Reset Value VMMU_L1PT3 VPE_BA + 09C VPE MMU Level-One Page Table Entry 3 Register 0x0000_0000 Level-One Page Table Entry 3 [31:24] Level-One Page Table Entry 3 [23:16] Level-One Page Table Entry 3 [15:8] Level-One Page Table Entry 3 [7:0] Bits...
Page 296 N9H26 Technical Reference Manual VPE MMU Level-one Page Table Entry 4 Register Register Address Description Reset Value VMMU_L1PT4 VPE_BA + 0A0 VPE MMU Level-One Page Table Entry 4 Register 0x0000_0000 Level-One Page Table Entry 4 [31:24] Level-One Page Table Entry 4 [23:16] Level-One Page Table Entry 4 [15:8] Level-One Page Table Entry 4 [7:0] Bits...
Page 297 N9H26 Technical Reference Manual VPE MMU Level-one Page Table Entry 5 Register Register Address Description Reset Value VMMU_L1PT5 VPE_BA + 0A4 VPE MMU Level-One Page Table Entry 5 Register 0x0000_0000 Level-One Page Table Entry 5 [31:24] Level-One Page Table Entry 5 [23:16] Level-One Page Table Entry 5 [15:8] Level-One Page Table Entry 5 [7:0] Bits...
Page 298 N9H26 Technical Reference Manual VPE MMU Level-one Page Table Entry 6 Register Register Address Description Reset Value VMMU_L1PT6 VPE_BA + 0A8 VPE MMU Level-One Page Table Entry 6 Register 0x0000_0000 Level-One Page Table Entry 6 [31:24] Level-One Page Table Entry 6 [23:16] Level-One Page Table Entry 6 [15:8] Level-One Page Table Entry 6 [7:0] Bits...
Page 299 N9H26 Technical Reference Manual VPE MMU Level-one Page Table Entry 7 Register Register Address R/W Description Reset Value VMMU_L1PT7 VPE_BA + 0AC VPE MMU Level-One Page Table Entry 7 Register 0x0000_0000 Level-One Page Table Entry 7 [31:24] Level-One Page Table Entry 7 [23:16] Level-One Page Table Entry 7 [15:8] Level-One Page Table Entry 7 [7:0] Bits...
Page 300 N9H26 Technical Reference Manual VPE MMU Current Virtual Address Register Register Address Description Reset Value VMMU_CVA VPE_BA + 0B0 VPE MMU Current Virtual Address Register 0x0000_0000 Current Virtual Address [31:24] Current Virtual Address [23:16] Current Virtual Address [15:8] Current Virtual Address [7:0] Bits Descriptions 32-bit Current Virtual Address...
Page 301 N9H26 Technical Reference Manual VPE MMU Current Virtual Page Number Register Register Address R/W Description Reset Value VMMU_CVPN VPE_BA + 0B4 VPE MMU Current Virtual Page Number Register 0x0000_0000 Current Virtual Page Number [31:24] Current Virtual Page Number [23:16] Current Virtual Page Number [15:8] Current Virtual Page Number [7:0] Bits Descriptions...
Page 302 N9H26 Technical Reference Manual VPE MMU Current Physical Address Register Register Address Description Reset Value VMMU_CPA VPE_BA + 0B8 VPE MMU Current Physical Address Register 0x0000_0000 Current Physical Address [31:24] Current Physical Address [23:16] Current Physical Address [15:8] Current Physical Address [7:0] Bits Descriptions 32-bit Current Physical Address...
Page 303 N9H26 Technical Reference Manual VPE MMU Current Physical Page Number Register Register Address R/W Description Reset Value VMMU_CPPN VPE_BA + 0BC VPE MMU Current Physical Page Number Register 0x0000_0000 Current Physical Page Number [31:24] Current Physical Page Number [23:16] Current Physical Page Number [15:8] Current Physical Page Number [7:0] Bits Descriptions...
Page 304: Jpeg Codec
N9H26 Technical Reference Manual 5.6 JPEG Codec 5.6.1 Overview from Capture JPEG Codec to Playback DCT/ IRAM Quant IDCT 8x64 TRAM ZRAM 72x15 64x12x2 ORAM 16x32 QTAB IQuant 64x8x3 HTAB 352x8 Common Encode Decode Figure 5.6-1 1 JPEG Codec block diagram The JPEG Codec supports Baseline Sequential Mode JPEG still image compression and decompression that is fully compliant with ISO/IEC International Standard 10918-1 (T.81).
Page 305: Jpeg Encode
N9H26 Technical Reference Manual  Support specified window decode mode  Support quantization-table adjustment for bit-rate and quality control in encode mode  Support rotate function in encode mode If image data input or output by packet format (PLANAR_ON= 0), the feature are as following: ...
Page 306: Figure 5.6-2 Image Starting Address And Stride
N9H26 Technical Reference Manual The JPEG Codec can encode the image with three components (Y, Cb, Cr) or Y component only, where Y component represents the luminance information, and Cb & Cr represent the chrominance information in planar format. It also can encode packet YUYV in packet format. The three components are stored in frame memory separately.
Page 307: Figure 5.6-3 Primary And Thumbnail Encode
N9H26 Technical Reference Manual Thumbnail off Encode Begin Thumbnail on Encode On Thumbnail Primary Encode Encode Idel State Primary Encode End Encode Figure 5.6-3 Primary and thumbnail encode The JPEG Codec supports the planar format up-scaling and down-scaling function to adjust the encoded image size.
Page 308: Peg Encode Programming
N9H26 Technical Reference Manual Single mode Continue mode ENC_MODE=10 Bit-stream Fix buffer 0 ENC_MODE=00 JPEG Engine JPEG Buffer 0 Engine Dual buffer ENC_MODE=01 ENC_MODE=11 JPEG Buffer 0 Bit-stream Engine JPEG Fix size Engine Buffer 1 Figure 5.6-4 Single mode and continue mode 5.6.4 PEG Encode Programming The programming flow for JPEG encode operation is described as follows:...
Page 309: Figure 5.6-5 Specified Window Decode Mode
N9H26 Technical Reference Manual JPEG bit-stream in frame memory by registers JIOADDR0 or JIOADDR1 and set JPEG decode mode by register bit ENC_DEC, and then trigger the JPEG engine. When the decode operation is complete, the JPEG engine will issue an interrupt to host. The status register DYUVMODE reports the image color format (4:4:4, 4:2:2, 4:2:0, or 4:1:1) that has been decoded.
Page 310 N9H26 Technical Reference Manual error occurs, a decode error interrupt will be issued to host. When DHEAD is set and the bitstream header has been decoded, a header decode complete interrupt will be issued to host. The interrupt status is reflected on register JINTCR. Publication Release Date: Sept.
Page 311: Jpeg Engine Control Register Map
N9H26 Technical Reference Manual 5.6.6 JPEG Engine Control Register Map R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written Register Address R/W/C Description Reset Value JPG_BA = 0xB100_A000 JMCR JPG_BA + 000 JPEG Engine Mode Control Register 0x0000_0000 JHEADER...
Page 312 N9H26 Technical Reference Manual Register Address R/W/C Description Reset Value JUADDR0 JPG_BA + 080 U Component Frame Buffer-0 Start Address Register 0x0000_0000 JVADDR0 JPG_BA + 084 V Component Frame Buffer-0 Start Address Register 0x0000_0000 Y Component or Packet Format Frame Buffer-1 Start JYADDR1 JPG_BA + 088 0x0000_0000...
Page 313 N9H26 Technical Reference Manual JPEG Engine Mode Control Register (JMCR) Register Address Description Default Value JMCR JPG_BA + 000 JPEG Engine Mode Control Register 0x0000_0000 Reserved Reserved Reserved RESUMEI RESUMEO ENC_DEC WIN_DEC EY422 QT_BUSY ENG_RST JPG_EN Bits Descriptions [31:9] Reserved Reserved Resume JPEG Operation for Input On-the-Fly Mode Write a “1”...
Page 314 N9H26 Technical Reference Manual Bits Descriptions Encode Image Format EY422 0 = YUV 4:2:0 1 = YUV 4:2:2 Quantization-Table Busy Status (Read-Only) QT_BUSY 0 = Quantization-Table is ready for host access 1 = Quantization-Table is busy and can’t be accessed Soft Reset JPEG Engine (Except JPEG Control Registers) ENG_RST 0 = Disable.
Page 315 N9H26 Technical Reference Manual JPEG Encode Header Control Register (JHEADER) Register Address Description Default Value JHEADER JPG_BA + 004 JPEG Encode Header Control Register 0x0000_0000 Reserved Reserved Reserved P_JFIF P_HTAB P_QTAB P_DRI T_JFIF T_HTAB T_QTAB T_DRI Bits Descriptions [31:8] Reserved Reserved Primary JPEG Bit-stream Include JFIF Header P_JFIF...
Page 316 N9H26 Technical Reference Manual Bits Descriptions 0 = Not Include 1 = Include Publication Release Date: Sept. 10, 2018 - 316 - Revision V1.01...
Page 317 N9H26 Technical Reference Manual JPEG Image Type Control Register (JITCR) Register Address Description Default Value JITCR JPG_BA + 008 JPEG Image Type Control Register 0x0000_0000 Reserved RGB_ROUND Reserved Dec_Scatter_ Dec_on_the_F ARGB8888 Gather PLANAR_ON ORDER RGB_555_565 ROTATE DYUV_MODE EXIF EY_ONLY DHEND DTHB E3QTAB D3QTAB...
Page 318 N9H26 Technical Reference Manual Bits Descriptions 11 = The encoded image is rotated right from source image Note: The JPRIWH and JTHBWH specify the image width and height after rotation. However the JPSCALD, JTSCALD and JUPRAT specify the scale ratio before rotation. Decoded Image YUV Color Format (Read-Only) 000 = The format of decoded image is YUV 4:2:0 001 = The format of decoded image is YUV 4:2:2...
Page 319 N9H26 Technical Reference Manual JPEG Encode Primary Quantization-table Control Register (JPRIQC) Register Address Description Default Value JPRIQC JPG_BA + 010 JPEG Primary Q-Table Control Register 0x0000_00F4 Reserved Reserved Reserved P_QADJUST P_QVS Bits Descriptions [31:8] Reserved Reserved Primary Quantization-Table Adjustment If the sum of the position (x, y) of quantization-table is greater than P_QADJUST, the quantization value will be set to 127.
Page 320 N9H26 Technical Reference Manual JPEG Encode Thumbnail Quantization-table Control Register (JTHBQC) Register Address Description Default Value JTHBQC JPG_BA + 014 JPEG Thumbnail Q-Table Control Register 0x0000_00F4 Reserved Reserved Reserved T_QADJUST T_QVS Bits Descriptions [31:8] Reserved Reserved Thumbnail Quantization-Table Adjustment If the sum of the position (x, y) of quantization-table is greater than T_QADJUST, the quantization value will be set to 127.
Page 321 N9H26 Technical Reference Manual JPEG Primary Image Width/Height Register (JPRIWH) Register Address Description Default Value JPRIWH JPG_BA + 018 JPEG Primary Width/Height Register 0x0000_0000 Reserved P_HEIGHT[12:8] P_HEIGHT[7:0] Reserved P_WIDTH[12:8] P_WIDTH[7:0] Bits Descriptions [31:29] Reserved Reserved Primary Encode and Packet Format Decode Image Height A 13-bit value specifies the height of encoded and decoded JPEG image.
Page 322 N9H26 Technical Reference Manual JPEG Encode Thumbnail Image Width/Height Register (JTHBWH) (for Planar Format Only) Register Address R/W Description Default Value JTHBWH JPG_BA + 01C R/W JPEG Encode Thumbnail Width/Height Register (For Planar Format Only) 0x0000_0000 Reserved T_HEIGHT[12:8] T_HEIGHT[7:0] Reserved T_WIDTH[12:8] T_WIDTH[7:0] Bits...
Page 323 N9H26 Technical Reference Manual JPEG Encode Primary Restart Interval Value Register (JPRST) Register Address Description Default Value JPRST JPG_BA + 020 JPEG Encode Primary Restart Interval Register 0x0000_0004 Reserved Reserved Reserved P_RST[7:0] Bits Descriptions [31:8] Reserved Reserved Primary Encode Restart Interval Value [7:0] P_RST An 8-bit value specifies the restart interval for encoding primary JPEG image.
Page 324 N9H26 Technical Reference Manual JPEG Encode Thumbnail Restart Interval Value Register (JTRST) Register Address Description Default Value JTRST JPG_BA + 024 JPEG Encode Thumbnail Restart Interval 0x0000_0004 Reserved Reserved Reserved T_RST[7:0] Bits Descriptions [31:8] Reserved Reserved Thumbnail Encode Restart Interval Value [7:0] T_RST An 8-bit value specifies the restart interval for encoding thumbnail JPEG image.
Page 325 N9H26 Technical Reference Manual JPEG Decode Image Width/Height Register (JDECWH) Register Address Description Default Value JDECWH JPG_BA + 028 JPEG Decode Image Width/Height Register 0x0000_0000 DEC_HEIGHT[15:8] DEC_HEIGHT[7:0] DEC_WIDTH[15:8] DEC_WIDTH[7:0] Bits Descriptions Decode Image Height [31:16] DEC_HEIGHT A 16-bit value reports the height of decoded JPEG image. Decode Image Width A 16-bit value reports the width of decoded JPEG image.
Page 326 N9H26 Technical Reference Manual JPEG Interrupt Control and Status Register (JINTCR) Register Address Description Default Value JINTCR JPG_BA + 02C JPEG Interrupt Control and Status Register 0x0020_0000 Reserved JPG_WAITI JPG_WAITO Reserved BAbort Reserved DHE_INTE IPW_INTE OPW_INTE ENC_INTE DEC_INTE DER_INTE EER_INTE Reserved DHE_INTS IPW_INTS...
Page 327 N9H26 Technical Reference Manual Bits Descriptions 0 = Disable 1 = Enable Output Wait Interrupt Enable [12] OPW_INTE 0 = Disable 1 = Enable Encode Complete Interrupt Enable [11] ENC_INTE 0 = Disable 1 = Enable Decode Complete Interrupt Enable [10] DEC_INTE 0 = Disable...
Page 328 N9H26 Technical Reference Manual Bits Descriptions 1 = Interrupt Generated Note: When write value “1” to this bit, the interrupt will be clear. Encode (On-The-Fly) Error Interrupt Status 0 = No Interrupt EER_INTS 1 = Interrupt Generated Note: When write value “1” to this bit, the interrupt will be clear. Publication Release Date: Sept.
Page 329 N9H26 Technical Reference Manual JPEG Decoding Output Wait Frame Buffer Size Register Address Description Default Value JDOWFBS JPG_BA + 03C JPEG Decoding Output Wait Frame Buffer Size 0xFFFF_FFFF Bits Descriptions JPEG Decoding Output Wait Frame Buffer Size The JPEG output decoding process will be paused while this buffer is full and decoding process will be resumed while new buffer size/address is set and “1”...
Page 330 N9H26 Technical Reference Manual JPEG TEST Control Register (JTEST) Register Address Description Default Value JTEST JPG_BA + 040 JPEG Test Control Register 0x0000_0000 Reserved BIST_ST[9:8] BIST_ST[7:0] TEST_DOUT[7:0] TEST_ON BIST_ON BIST_FINI BIST_FAIL TEST_SEL[3:0] Bits Descriptions [31:26] Reserved Reserved Internal SRAM BIST Status (Read-Only) [25:16] BIST_ST The 8 bits indicate which one of the internal SRAM macros is fail after BIST.
Page 331 N9H26 Technical Reference Manual Bits Descriptions 0100 = vld_cycle_st[1:0] 0101 = vle_st[4:0] 0110 = blk_st[2:0] 0111 = vld_st[4:0] 1000 = dec_st[2:0] 1001 = jmi_st[3:0] 1010 = addr_st[3:0] Publication Release Date: Sept. 10, 2018 - 331 - Revision V1.01...
Page 332 N9H26 Technical Reference Manual JPEG Window Decode Mode Control Register 0 (JWINDEC0) Register Address Description Default Value JWINDEC0 JPG_BA + 044 JPEG Window Decode Mode Control Register 0 0x0000_0000 Reserved MCU_S_Y[9:8] MCU_S_Y[7:0] Reserved MCU_S_X[9:8] MCU_S_X[7:0] Bits Descriptions [31:26] Reserved Reserved MCU(Minimum Coded Unit) Start Position Y For Window Decode Mode A 10-bit value specifies the MCU start position y of the window region within the whole [25:16]...
Page 333 N9H26 Technical Reference Manual JPEG Window Decode Mode Control Register 1 (JWINDEC1) Register Address Description Default Value JWINDEC1 JPG_BA + 048 JPEG Window Decode Mode Control Register 1 0x0000_0000 Reserved MCU_E_Y[9:8] MCU_E_Y[7:0] Reserved MCU_E_X[9:8] MCU_E_X[7:0] Bits Descriptions [31:26] Reserved Reserved MCU End Position Y For Window Decode Mode [25:16] MCU_E_Y...
Page 334 N9H26 Technical Reference Manual JPEG Window Decode Mode Control Register 2 (JWINDEC2) Register Address Description Default Value JWINDEC2 JPG_BA + 04C JPEG Window Decode Mode Control Register 2 0x0000_0000 Reserved Reserved Reserved WD_WIDTH[12:8] WD_WIDTH[7:0] Bits Descriptions [31:13] Reserved Reserved Image Width (Y-Stride) For Window Decode Mode A 13-bit value specifies the memory line space (Y-Stride) for the window image within [12:0] WD_WIDTH...
Page 335 N9H26 Technical Reference Manual JPEG Memory Address Mode Control Register (JMACR) Register Address Description Default Value JMACR JPG_BA + 050 JPEG Memory Address Mode Control Register 0x0000_0000 Reserved FLY_SEL FLY_TYPE Reserved BSF_SEL[9:8] BSF_SEL[7:0] FLY_ON Reserved IP_SF_ON OP_SF_ON ENC_MODE Bits Descriptions [31:30] Reserved Reserved...
Page 336 N9H26 Technical Reference Manual Bits Descriptions Software Memory On-the-Fly Access Mode for Data Input 0 = Disable, JPEG can only be triggered after the whole image or bitstream data is stored in frame-buffer in encode or decode mode individually IP_SF_ON 1 = Enable, JPEG can encode partial image or decode partial bitstream data by re-using a small size frame-buffer;...
Page 337 N9H26 Technical Reference Manual JPEG Primary Scaling-up Control Register (JPSCALU) Register Address Description Default Value JPSCALU JPG_BA + 054 JPEG Primary Scaling-Up Control Register 0x0000_0000 Reserved Reserved Reserved Reserved Reserved A_JUMP Reserved Bits Descriptions [31:7] Reserved Reserved Primary Image Up-Scaling For Encode 0 = No up-scaling, original size (X2 and Y2 are the 1 = In encode mode, the image is arbitrarily up-scaled 1X~8X;...
Page 338 N9H26 Technical Reference Manual JPEG Primary Scaling-down Control Register (JPSCALD) Register Address Description Default Value JPSCALD JPG_BA + 058 JPEG Primary Scaling-Down Control Register 0x0000_0000 Reserved Reserved PSX_ON PS_LPF_ON Reserved PSCALX_F Reserved PSCALY_F Bits Descriptions [31:16] Reserved Reserved Primary Image Horizontal Down-Scaling For Encode/Decode 0 = Disable, no horizontal down-scale 1 = Enable [15]...
Page 339 N9H26 Technical Reference Manual Bits Descriptions planar format decode mode, the value of SCALY_F can only be 0, 1, 3, 7, i.e. scaling- down 1/1, 1/2, 1/4 and 1/8. For packet format, SCALY_F is reserved. Publication Release Date: Sept. 10, 2018 - 339 - Revision V1.01...
Page 340 N9H26 Technical Reference Manual JPEG Thumbnail Scaling-down Control Register (JTSCALD) Register Address Description Default Value JTSCALD JPG_BA + 05C JPEG Thumbnail Scaling-Down Control 0x0000_0000 Reserved Reserved TSX_ON Reserved TSCALX_F Reserved TSCALY_F Bits Descriptions [31:16] Reserved Reserved Thumbnail Image Horizontal Down-Scaling For Encode [15] TSX_ON 0 = Disable, no horizontal down-scale...
Page 341 N9H26 Technical Reference Manual JPEG Dual-buffer Control Register (JDBCR) Register Address Description Default Value JDBCR JPG_BA + 060 JPEG Dual-Buffer Control Register 0x0000_0000 Reserved Reserved Reserved DBF_EN Reserved IP_BUF Reserved OP_BUF Bits Descriptions [31:8] Reserved Reserved Dual Buffering Control DBF_EN 0 = Disable dual buffering 1 = Enable dual buffering [6:5]...
Page 342 N9H26 Technical Reference Manual JPEG Encode Primary Bit-stream Reserved Size Register (JRESERVE) Register Address R/W Description Default Value JRESERVE JPG_BA + 070 JPEG Encode Primary Bit-stream Reserved Size Register 0x0000_0000 Reserved Reserved RES_SIZE[15:8] RES_SIZE[7:0] Bits Descriptions [31:16] Reserved Reserved Primary Encode Bit-stream Reserved Size A 16-bit value specifies the reserved size (byte address) in encoded primary JPEG bit- stream.
Page 343 N9H26 Technical Reference Manual JPEG Offset Between Primary/Thumbnail Start Address Register (JOFFSET) Register Address R/W Description Default Value JOFFSET JPG_BA + 074 JPEG Offset Between Primary & Thumbnail Register 0x0000_0000 Reserved OFFSET_SIZE[23:16] OFFSET_SIZE[15:8] OFFSET_SIZE[7:0] Bits Descriptions [31:24] Reserved Reserved Primary/Thumbnail Starting Address Offset Size A 24-bit value specifies the offset size (byte address) between the starting address of [23:0] OFFSET_SIZE...
Page 344 N9H26 Technical Reference Manual JPEG Encode Bit-stream Frame Stride Register (JFSTRIDE) Register Address Description Default Value JFSTRIDE JPG_BA + 078 JPEG Encode Bit-stream Frame Stride Register 0x0000_0000 Reserved F_STRIDE[23:16] F_STRIDE[15:8] F_STRIDE[7:0] Bits Descriptions [31:24] Reserved Reserved JPEG Encode Bit-stream Frame Stride [23:0] F_STRIDE A 24-bit value specifies the memory distance between neighbor JPEG bit-stream (byte...
Page 345 N9H26 Technical Reference Manual JPEG Y Component or Packet Format Frame Buffer-0 Starting Address Register (JYADDR0) Default Register Address R/W Description Value JPG_BA + JPEG Y Component or Packet Format Frame Buffer-0 Starting Address JYADDR0 0x0000_0000 Register Y_IADDR0[31:24] Y_IADDR0[23:16] Y_IADDR0[15:0] Y_IADDR0[7:0] Bits Descriptions...
Page 346 N9H26 Technical Reference Manual JPEG U Component Frame Buffer-0 Starting Address Register (JUADDR0) Register Address R/W Description Default Value JUADDR0 JPG_BA + 080 R/W JPEG U Component Frame Buffer-0 Starting Address Register 0x0000_0000 U_IADDR0[31:24] U_IADDR0[23:16] U_IADDR0[15:8] U_IADDR0[7:0] Bits Descriptions JPEG U Component Frame Buffer-0 Starting Address [31:0] U_IADDR0 A 32-bit value specifies the starting address bits 31 to 0 of frame buffer-0 for U component...
Page 347 N9H26 Technical Reference Manual JPEG V Component Frame Buffer-0 Starting Address Register (JVADDR0) Register Address R/W Description Default Value JVADDR0 JPG_BA + 084 R/W JPEG V Component Frame Buffer-0 Starting Address Register 0x0000_0000 V_IADDR0[31:24] V_IADDR0[23:16] V_IADDR0[15:8] V_IADDR0[7:0] Bits Descriptions JPEG V Component Frame Buffer-0 Starting Address [31:0] V_IADDR0 A 32-bit value specifies the starting address bits 31 to 0 of frame buffer-0 for V component...
Page 348 N9H26 Technical Reference Manual JPEG Y Component or Packet Format Frame Buffer-1 Starting Address Register (JYADDR1) Register Address Description Default Value JPEG Y Component or Packet Format Frame Buffer-1 Starting JYADDR1 JPG_BA + 088 0x0000_0000 Address Register Y_IADDR1[31:24] Y_IADDR1[23:16] Y_IADDR1[15:8] Y_IADDR1[7:0] Bits Descriptions...
Page 349 N9H26 Technical Reference Manual JPEG U Component Frame Buffer-1 Starting Address Register (JUADDR1) Register Address R/W Description Default Value JUADDR1 JPG_BA + 08C R/W JPEG U Component Frame Buffer-1 Starting Address Register 0x0000_0000 U_IADDR1[31:24] U_IADDR1[23:16] U_IADDR1[15:8] U_IADDR1[7:0] Bits Descriptions JPEG U Component Frame Buffer-1 Starting Address [31:0] U_IADDR1 A32-bit value specifies the starting address bits 31 to 0 of frame buffer-1 for U component...
Page 350 N9H26 Technical Reference Manual JPEG V Component Frame Buffer-1 Starting Address Register (JVADDR1) Register Address R/W Description Default Value JVADDR1 JPG_BA + 090 R/W JPEG V Component Frame Buffer-1 Starting Address Register 0x0000_0000 V_IADDR1[31:24] V_IADDR1[23:16] V_IADDR1[15:8] V_IADDR1[7:0] Bits Descriptions JPEG V Component Frame Buffer-1 Starting Address [31:0] V_IADDR1 A 32-bit value specifies the starting address bits 31 to 0 of frame buffer-1 for V component...
Page 351 N9H26 Technical Reference Manual JPEG Y Component Frame Buffer Stride Register (JYSTRIDE) Register Address R/W Description Default Value JYSTRIDE JPG_BA + 094 JPEG Y Component Frame Buffer Stride Register 0x0000_0000 Reserved Reserved Reserved Y_STRIDE[11:8] Y_STRIDE[7:0] Bits Descriptions [31:12] Reserved Reserved JPEG Y Component Frame Buffer Stride A 12-bit value specifies the byte offset of memory address of vertical adjacent line for Y [11:0]...
Page 352 N9H26 Technical Reference Manual JPEG U Component Frame Buffer Stride Register (JUSTRIDE) Register Address R/W Description Default Value JUSTRIDE JPG_BA + 098 JPEG U Component Frame Buffer Stride Register 0x0000_0000 Reserved Reserved Reserved U_STRIDE[11:8] U_STRIDE[7:0] Bits Descriptions [31:12] Reserved Reserved JPEG U Component Frame Buffer Stride [11:0] U_STRIDE...
Page 353 N9H26 Technical Reference Manual JPEG V Component Frame Buffer Stride Register (JVSTRIDE) Register Address R/W Description Default Value JVSTRIDE JPG_BA + 09C JPEG V Component Frame Buffer Stride Register 0x0000_0000 Reserved Reserved Reserved V_STRIDE[11:8] V_STRIDE[7:0] Bits Descriptions [31:12] Reserved Reserved JPEG V Component Frame Buffer Stride [11:0] V_STRIDE...
Page 354 N9H26 Technical Reference Manual JPEG Bit-stream Frame Buffer-0 Starting Address Register (JIOADDR0) Register Address R/W Description Default Value JIOADDR0 JPG_BA + 0A0 R/W JPEG Bit-stream Frame Buffer-0 Starting Address Register 0x0000_0000 IO_IADDR0[31:24] IO_IADDR0[23:16] IO_IADDR0[15:8] IO_IADDR0[7:0] Bits Descriptions JPEG Bit-stream Frame Buffer-0 Starting Address [31:0] IO_IADDR0 A 32-bit value specifies the starting address bits 31 to 0 of frame buffer-0 for JPEG bit-...
Page 355 N9H26 Technical Reference Manual JPEG Bit-stream Frame Buffer-1 Starting Address Register (JIOADDR1) Register Address R/W Description Default Value JIOADDR1 JPG_BA + 0A4 R/W JPEG Bit-stream Frame Buffer-1 Starting Address Register 0x0000_0000 IO_IADDR1[31:24] IO_IADDR1[23:16] IO_IADDR1[15:8] IO_IADDR1[7:0] Bits Descriptions JPEG Bit-stream Frame Buffer-1 Starting Address [31:0] IO_IADDR1 A 32-bit value specifies the starting address bits 31 to 0 of frame buffer-1 for JPEG bit-...
Page 356 N9H26 Technical Reference Manual JPEG Encode Primary Image Bit-stream Size Register (JPRI_SIZE) Register Address R/W Description Default Value JPRI_SIZE JPG_BA + 0A8 JPEG Encode Primary Image Bit-stream Size Register 0x0000_0000 Reserved PRI_SIZE[23:16] PRI_SIZE[15:8] PRI_SIZE[7:0] Bits Descriptions [31:24] Reserved Reserved JPEG Primary Image Encode Bit-stream Size [23:0] PRI_SIZE A 24-bit value reports the bit-stream byte size of encoded primary image.
Page 357 N9H26 Technical Reference Manual JPEG Encode Thumbnail Image Bit-stream Size Register (JTHB_SIZE) Register Address R/W Description Default Value JTHB_SIZE JPG_BA + 0AC JPEG Encode Thumbnail Image Bit-stream Size Register 0x0000_0000 Reserved Reserved THB_SIZE[15:8] THB_SIZE[7:0] Bits Descriptions [31:16] Reserved Reserved JPEG Thumbnail Image Encode Bit-stream Size [15:0] THB_SIZE A 16-bit value reports the bit-stream byte size of encoded thumbnail image.
Page 358 N9H26 Technical Reference Manual JPEG Planar Format Encode Up-scale and Packet Format Decode Down-scale Ratio (JUPRAT) Default Register Address R/W Description Value JPG_BA + JPEG Planar Format Encode Up-Scale and Packet Format Decode Down-Scale JUPRAT 0x0000_0000 Ratio Register Reserved S_HEIGHT[13:8] S_HEIGHT[7:0] Reserved S_WIDTH[13:8]...
Page 359 N9H26 Technical Reference Manual JPEG Bit-stream FIFO Control Register (JBSFIFO) Register Address Description Default Value JBSFIFO JPG_BA + 0B4 JPEG Bit-stream FIFO Control Register 0x0000_0032 Reserved Reserved Reserved Reserved BSFIFO_HT Reserved BSFIFO_LT Bits Descriptions [31:7] Reserved Reserved Bit-stream FIFO High-Threshold Control While the fullness of bit-stream output FIFO is higher than the high-threshold in encode mode, the priority for output will become higher than input.
Page 360 N9H26 Technical Reference Manual JPEG Encode Source Image Height (JSRCH) Register Address Description Default Value JSRCH JPG_BA + 0B8 JPEG Encode Source Image Height Register 0x0000_0FFF Reserved Reserved Reserved JSRCH[11:8] JSRCH[7:0] Bits Descriptions [31:12] Reserved Reserved JPEG Encode Source Image Height A 12-bit value specifies source image height.
Page 361 N9H26 Technical Reference Manual JPEG Quantization-table 0 Register (JQTAB0) Register Address Description Default Value JQTAB0_0/1/2/3 ~ JPG_BA + 100~ JPEG Quantization-Table 0 Register Undefined JQTAB0_60/61/62/63 JPG_BA + 13F QTAB0_3 QTAB0_2 QTAB0_1 QTAB0_0 Bits Descriptions JPEG Quantization-Table 0 – 3 An 8-bit value specifies one element (3, 7, 11, …, 59, 63) of the Quantization-Table 0. [31:24] QTAB0_3 Note:...
Page 362 N9H26 Technical Reference Manual JPEG Quantization-table 1 Register (JQTAB1) Register Address Description Default Value JQTAB1_0/1/2/3 ~ JPG_BA + 140~ JPEG Quantization-Table 1 Register Undefined JQTAB1_60/61/62/63 JPG_BA + 17F QTAB1_3 QTAB1_2 QTAB1_1 QTAB1_0 Bits Descriptions JPEG Quantization-Table 1 – 3 An 8-bit value specifies one element of the Quantization-Table 1. [31:24] QTAB1_3 Note: When three-QTAB mode (E3QTAB) is enabled, JPEG encoder uses this table for...
Page 363 N9H26 Technical Reference Manual JPEG Quantization-table 2 Register (JQTAB2) Register Address Description Default Value JQTAB2_0/1/2/3 ~ JPG_BA + 180~ JPEG Quantization-Table 2 Register Undefined JQTAB2_60/61/62/63 JPG_BA + 1BF QTAB2_3 QTAB2_2 QTAB2_1 QTAB2_0 Bits Descriptions JPEG Quantization-Table 2 – 3 An 8-bit value specifies one element of the Quantization-Table 2. [31:24] QTAB2_3 Note: When three-QTAB mode (E3QTAB) is enabled, JPEG encoder uses this table for...
Page 364: Video Codec
N9H26 Technical Reference Manual 5.7 H.264 Video Codec 5.7.1 H.264 DECODER Overview Figure 5.7-1 H.264 Decoder block diagram H264DEC is a video decoder, which supports the H.264 standard baseline profile. H264DEC is compliant with the ITU-T Recommendation H.264|ISO/IEC 14496-10 Advanced Video Coding Standard (MPEG 4 Part 10). This decoder is capable of decoding the video streams with a resolution of up to 720 x 480 at a frame rate of up to 60 frames per second or decoding the video streams with a resolution of up to 2048 x 1024 at a frame rate of up to 10 frames per second.
Page 365: Encoder Features
N9H26 Technical Reference Manual Figure 5.7-2 H.264 ENCODER BLOCK The above block diagram shows an example of how H264ENC can be connected to an SoC system. The uncompressed video raw data is put into the system memory by using a video capture device or other data communication interface.
Page 366: Encoding Modes
N9H26 Technical Reference Manual ue(v) function is available.  Pack the performance with or without the prevention of the NAL header  Add the RBSP trailing bits in the end of a bitstream  Close and drain out the bitstream from a local buffer 5.7.6 Encoding Modes ...
Page 367: Pmv/Ec
N9H26 Technical Reference Manual the cost function for each type of blocks. All possible inter prediction mode will be examined by the sum of the best cost of the related block types. The best inter prediction mode is the one that has the lowest cost value.
Page 368: Display Interface Controller (Vpost)
N9H26 Technical Reference Manual 5.8 Display Interface Controller (VPOST) 5.8.1 overview The main purpose of VPOST Controller (include LCD Controller & TVEncoder Controller) is used to display the video/image data to LCD device or to generate the composite signal to the TV system. The LCD timing can be synchronize with TV (NTSC/PAL non-interlace/interlace timing) or set by the LCD timing control register.
Page 369: Figure 5.8-1 Vpost Controller Interface Diagram
N9H26 Technical Reference Manual LVDATA[23:0] DATA[23:0] DATA[7:0] DATA[23:0] DATA[23:0] Figure 5.8-1 VPOST Controller Interface Diagram Pin Name RGB888 RGB666 RGB565 RGB555 LVDATA[0] LVDATA[1] LVDATA[2] LVDATA[3] LVDATA[4] LVDATA[5] LVDATA[6] LVDATA[7] LVDATA[8] LVDATA[9] LVDATA[10] LVDATA[11] LVDATA[12] LVDATA[13] LVDATA[14] LVDATA[15] LVDATA[16] LVDATA[17] SPDATA[2] (LVDATA[18]) SPDATA[3] (LVDATA[19]) SPDATA[4] (LVDATA[20]) SPDATA[5] (LVDATA[21])
Page 370: Vpost Controller Block Diagram
N9H26 Technical Reference Manual 5.8.4 VPOST Controller Block Diagram AXI Bus AXICLK Domain AXI_ASYNCIF HCLK Domain AHB Bus AXI_MASTER MP_ADDRGEN OSD_ADDRGEN VPOST_ILB REG BANK MP_Buffer OSD_Buffer MIXER LB_CTRL VPOST_OLB Output Buffer LCMMUX deflicker CCIR656_TG MPU_TG LCD_TG TV_TG HCLK Domain LCDCLK Domain Figure 5.8-3 VPOST Controller Block Diagram 5.8.5 VPOST Controller Functional Description...
Page 371 N9H26 Technical Reference Manual  TVEncoder Generate TV NTSC/PAL data signal to current DAC. – Generate timing control signal to LCD device. –  LCD Timing Generator user-self control timing –  Register Bank AHB Slave interface on AHB1. – A bridge that CPU control and observe the state of LCD Controller.
Page 372: Vpost Display Interface Ac/Dc Characteristic
N9H26 Technical Reference Manual 5.8.6 VPOST display interface AC/DC characteristic SYNC Type LCD LPCLK LPCLK LHSYNC LVSYNC LVDE LVDATA[15:0] LODLY Symbol Parameter Condition Min. Typ. Max. Unit LPCLK Clock Frequency LPCLK LPCLK Clock Low Time 4.17 LPCLK Clock High Time 4.17 LHSYNC, LVSYNC, LVDE and LVDATA 1.313...
Page 373 N9H26 Technical Reference Manual MPU Type LCD LPCLK (CS_) LVDE (RS) LCSS LCSH 80 Mode: LHSYNC (WR_) LDOD LDOH LVDATA[15:0] 68 Mode: LVSYNC (EN) Symbol Parameter Condition Min. Typ. Max. Unit CS_ to WR_ Setup Time PCLK LCSS CS_ to WR_ Hold Time PCLK LCSH RS to WR_ Setup Time...
Page 374: Vpost Controller Control Registers Map
N9H26 Technical Reference Manual 5.8.7 VPOST Controller Control Registers Map R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written Register Address Description Reset Value VPOST_BA = 0xB100_2000 LCDCCtl 0x00 LCD Controller Control Register 0x0000_0000 LCDCPrm 0x04...
Page 375 N9H26 Technical Reference Manual Register Address Description Reset Value YCbCrin 0x7c YCbCr Data Input for YCbCr2RGB equation 0x0010_8080 RGBout 0x80 RGB Data Output for YCbCr2RGB equation 0x0010_1010 Reserved 0x84 Reserved 0x0000_0000 Reserved 0x88 Reserved 0x0000_0000 Reserved 0x8C Reserved 0x0101_0000 OSD_TC_MASK 0x90 OSD Transparent Mask Control 0x0000_0000...
Page 376: Vpost Controller Control Registers
N9H26 Technical Reference Manual 5.8.8 VPOST Controller Control Registers Publication Release Date: Sept. 10, 2018 - 376 - Revision V1.01...
Page 377 N9H26 Technical Reference Manual LCD Controller Control Register Register Address Description Reset Value LCDCCtl 0x00 LCD Controller Control Register 0x0000_0000 Reserved SHADOW LCD2TMODE PRDB_SEL Reserved YUV_CLIP_E YUVBL Reserved PADMSB TRUNMODE SC_EN CCIR601 FBDS LCDRUN Descriptions Bits [31:25] Reserved Reserved Register shadow mode [24] SHADOW 0: disable...
Page 378 N9H26 Technical Reference Manual Descriptions Bits [15:8] Reserved Reserved Pad MSB to LCM lower bits. PADMSB 0 = no padding 1 = padding MSB RGB888 to RGB565 truncate TRUNCATE 0 = rounding 1 = truncate Scaling Enable SC_EN Note: The register can be shadowed by Vsync. RGB2YCbCr Mode CCIR601 0 = Full Range...
Page 379 N9H26 Technical Reference Manual FBDS=3'b100 U0/Cb0 V0/Cr0 YUVBL=1'b0 FBDS=3'b101 U0/Cb0 V0/Cr0 YUVBL=1'b0 FBDS=3'b110 V0/Cr0 U0/Cb0 YUVBL=1'b0 FBDS=3'b111 V0/Cr0 U0/Cb0 YUVBL=1'b0 FBDS=3'b100 V0/Cr0 U0/Cb0 YUVBL=1'b1 FBDS=3'b101 V0/Cr0 U0/Cb0 YUVBL=1'b1 FBDS=3'b110 U0/Cb0 V0/Cr0 YUVBL=1'b1 FBDS=3'b111 U0/Cb0 V0/Cr0 YUVBL=1'b1 Publication Release Date: Sept. 10, 2018 - 379 - Revision V1.01...
Page 380 N9H26 Technical Reference Manual LCD Controller Parameter Register Register Address Description Reset Value LCDCPrm 0x04 LCD Controller Parameter Register 0x4384_8800 Odd_Field_AL Even_Field_AL F1_EL[8:1] F1_EL[0] F1_SL LCDSynTv SRGB_EL_SEL SRGB_OL_SEL LCDDataSel LCDTYPE Bits Descriptions Odd_Field_AL CCIR656 Odd Field Dummy Active Line [31:28] (4’h4) Odd Field Total Active Line=240+ Odd_Field_AL Even_Field_AL...
Page 381 N9H26 Technical Reference Manual Bits Descriptions 10 = odd line data is GBR 11 = odd line data is RBG 8bit LCD data interface Select 00 = YUV422(CCIR601) LCDDataSel 01 = dummy serial (R, G, B Dummy) [3:2] (2’b00) 10 = CCIR656 Output 11= Serial RGB interface Note: The register can be shadowed by Vsync.
Page 382 N9H26 Technical Reference Manual LCD Controller Interrupt Register Register Address Description Reset Value LCDCInt 0x08 LCD Controller Interrupt Register 0x0000_0000 Reserved Reserved MPUCPLEN TVFIELD_INT VINTEN HINTEN Reserved Reserved MPUCPL TVFIELD_INT VINT HINT Bits Descriptions [31:21] Reserved Reserved [20] MPUCPLEN MPU Frame Complete Enable [19] Reserved Reserved...
Page 383 N9H26 Technical Reference Manual MPU Read Command Data Register Address Description Reset Value MPURD 0x0C MPU Read Command Data 0x0000_0000 Reserved Reserved MPURDDATA[15:8] MPURDDATA[7:0] Bits Descriptions [31:16] Reserved Reserved MPU Read Data In [15:0] MPURDDATA The data read from MPU bus. Publication Release Date: Sept.
Page 384 N9H26 Technical Reference Manual Timing Control Register 1 Register Address Description Reset Value TCON1 0x10 Timing Control Register 1 0x0000_0000 HSPW[7:0] HBPD[11:4] HBPD[3:0] HFPD[11:8] HFPD[7:0] Bits Descriptions Horizontal sync pulse width [31:24] HSPW To determines the HSYNC pulse's high level width by counting the number of the LCD Pixel Clock.
Page 385 N9H26 Technical Reference Manual Timing Control Register 2 Register Address Description Reset Value TCON2 0x14 Timing Control Register 2 0x0000_0000 Reserved VSPW VBPD VFPD Bits Descriptions [31:25] Reserved Reserved Vertical sync pulse width [23:16] VSPW To determines the VSYNC pulse's high level width by counting the number of inactive lines. Vertical back porch [15:8] VBPD...
Page 386 N9H26 Technical Reference Manual Timing Control Register 3 Register Address Description Reset Value TCON3 0x18 Timing Control Register 3 0x0000_0000 PPL[15:8] PPL[7:0] LPP[15:8] LPP[7:0] Bits Descriptions Active Data Count Per-Line The PPL bit field specifies the number of output data in each line or row of screen. [31:16] (Frame buffer width must >= PPL) Note: The register can be shadowed by Vsync.
Page 387 N9H26 Technical Reference Manual Timing Control Register 4 Register Address Description Reset Value TCON4 0x1c Timing Control Register 4 0x2800_0040 TAPN[11:4] TAPN[3:0] MVPW[11:8] MVPW[7:0] Reserved MPU_FMARK MPU_VSYNC PCLKP Descriptions Bits Total MPU Active Pixel Number (for LCDSynTv = 0) [31:20] TAPN Note: The register can be shadowed by Vsync.
Page 388 N9H26 Technical Reference Manual HSPW HSYNC HBPD HFPD VDEN PPL+1 DPPL Horizontal Line Timing HSYNC VSPW VSYNC VBPD VFPD VDEN LPP+1 Vertical Line Timing Publication Release Date: Sept. 10, 2018 - 388 - Revision V1.01...
Page 389 N9H26 Technical Reference Manual MPU-type LCD Command Register Register Address Description Reset Value MPUCMD 0x20 MPU-type LCD Command Register 0x0000_0000 MPU_VFPIN_ DIS_SEL CMD_DISn MPU_CS MPU_ON MPU_BUSY WR_RS MPU_RWn MPU68 FMARK Reserved MPU_SI_SEL MPU_CMD[15:8] MPU_CMD[7:0] Descriptions Bits MPU VSYN/FMARK Pin Selection [31] MPU_VFPIN_SEL 1’b0: MPU VSYN/FMARK as Output Pin...
Page 390 N9H26 Technical Reference Manual Descriptions Bits 1 = Read status/data from LCD MPU interface Selection MPU68 [23] 0 = 80-series MPU interface (1’b0) 1 = 68-series MPU interface Frame Mark Detection Disable/Enable [22] FMARK 1’b0: To ignore the Frame Mark Input Signal 1’b1: To update display data after Frame Mark signal [21:20] Reserved...
Page 391 N9H26 Technical Reference Manual Mode MPU_SI_SEL Bus Width Pixel Color Depth Transfer Method Note MPU16_Mode0 4’h5 16bit 16bit transfer 16 bit MPU16_Mode1 4’h6 16bit 18bit transfer 16 bit Transfer 2 bit MPU16_Mode2 4’h7 16bit 18bit transfer 2 bit Transfer 16 bit MPU16_Mode3 4’h8 16bit...
Page 392 N9H26 Technical Reference Manual MPU-type LCD Timing Setting Register Register Address Description Reset Value MPUTS 0x24 MPU type LCD Timing Setting 0x0101_0101 CSnF2DCt WRnR2CSnRt WRnLWt CSnF2WRnFt Descriptions Bits [31:24] CSnF2DCt CSn fall edge to Data change clock counter (Ref Value: 1) [23:16] WRnR2CSnRt WRn rising edge to CSn rising clock counter (Ref Value: 1)
Page 393 N9H26 Technical Reference Manual CF2WFt:Cs fall edge to WR falling edge clock count 80 Mode Write Data Timing WaveForm LCDCLK CSnF2WRnF WRnR2CSnRt WLWt CSnF2DCt DATA CF2WFt:Cs fall edge to WR falling edge clock count 68 Mode Write Data Timing WaveForm LCDCLK CSnF2WRnF WRnR2CSnRt...
Page 394 N9H26 Technical Reference Manual OSD Control Register Register Address Description Reset Value OSD_CTL 0x28 OSD Control Register 0x0000_0000 OSD_EN Reserved OSD_TPEN OSD_FSEL OSD_TC[23:16] OSD_TC [15:8] OSD_TC[7:0] Descriptions Bits OSD Enable register 1’b0: Disable [31] OSD_EN 1’b1: Enable Note: The register can be shadowed by Vsync. [30:29] Reserved Reserved...
Page 395 N9H26 Technical Reference Manual Descriptions Bits R5=OSD_TC[14:10] G5=OSD_TC[9:5] B5=OSD_TC[4:0] RGB565: R5=OSD_TC[15:11] G6=OSD_TC[10:5] B5=OSD_TC[4:0] YUV: Y=OSD_TC[23:16]; Cb=OSD_TC[15:8] Cr=OSD_TC[7:0] RGB888: R=OSD_TC[23:16]; G=OSD_TC[15:8] B=OSD_TC[7:0] Publication Release Date: Sept. 10, 2018 - 395 - Revision V1.01...
Page 396 N9H26 Technical Reference Manual OSD Size Setting Register Register Address Description Reset Value OSD_SIZE 0x2c OSD SIZE 0x0000_0000 Reserved OSD_VSIZE[9:8] OSD_VSIZE[7:0] Reserved OSD_HSIZE[9:8] OSD_HSIZE[7:0] Descriptions Bits [31:26] Reserved Reserved OSD Vertical Size (Line) – 1 [25:16] OSD_VSIZE Note: The register can be shadowed by Vsync. [15:10] Reserved Reserved...
Page 397 N9H26 Technical Reference Manual OSD Start Position Register Register Address Description Reset Value OSD Start Position on the OSD_SP 0x30 0x0000_0000 background picture Reserved OSD_SY[9:8] OSD_SY[7:0] Reserved OSD_SX[9:8] OSD_SX[7:0] Bits Descriptions [31:26] Reserved Reserved OSD Vertical Start Position (Line) on the background picture [23:16] OSD_SY Note: The register can be shadowed by Vsync.
Page 398 N9H26 Technical Reference Manual OSD 1 Bar End Position Register Register Address Description Reset Value OSD 1st Bar End Position on OSD_1BEP 0x34 0x0000_0000 the background picture Reserved OSD_1BEY[9:8] OSD_1BEY[7:0] Reserved OSD_1BEX[9:8] OSD_1BEX[7:0] Descriptions Bits [31:26] Reserved Reserved OSD Vertical 1 Bar End Position (Line) on the background picture [23:16] OSD_1BEY...
Page 399 N9H26 Technical Reference Manual OSD Bar Offset Setting Register Register Address Description Reset Value OSD_BO 0x38 OSD Bar Offset 0x0000_0000 Reserved OSD_BOY[9:8] OSD_BOY[7:0] Reserved OSD_BOX[9:8] OSD_BOX[7:0] Descriptions Bits [31:26] Reserved Reserved OSD Vertical Bar Offset (Line) [25:16] OSD_BOY Note: The register can be shadowed by Vsync. [15:10] Reserved Reserved...
Page 400 N9H26 Technical Reference Manual [OSD parameter setting] (OSD_XSIZE, OSD_YSIZE) (OSD_SX, OSD_SY) (OSD_1BEX, OSD_1BEY) (OSD_BOY) (OSD_BOX) Publication Release Date: Sept. 10, 2018 - 400 - Revision V1.01...
Page 401 N9H26 Technical Reference Manual Color Burst Active Region Control Register Register Address Description Reset Value CBAR_CTL 0x3c Color Burst Active Region Control 0x006E_0050 VLCBAR Reserved EQ6SEL Reserved HCBEPC[9:8] HCBEPC[7:0] Reserved HCBBPC[9:8] HCBBPC[7:0] Descriptions Bits Vertical Line Color Burst Active Region 2’b00:7~309 2’b01:7~310 [31:30]...
Page 402 N9H26 Technical Reference Manual TvControl Register Register Address Description Reset Value TVCtl 0x40 TvControl Register 0x0001_0310 TvField Reserved TvFFFE Reserved NTSC_TYPE PAL_TYPE Reserved PAL288 DAC_NORMA TV_D1 Reserved LCDSrc TvSrc Noninter_Typ Reserved TVCLKINV TvDac TvInter TvSys TvColor TvSleep Descriptions Bits Tv Field Status (only read) TvField [31] 1’b0 = Even Field...
Page 403 N9H26 Technical Reference Manual LCD Source Selection 00 = Reserved LCDSrc 01 = Frame Buffer [11:10] (2’h0) 10 = Register Setting Color 11 = Internal Color Bar Note: The register can be shadowed by Vsync. Tv Source Selection 00 = Reserved TvSrc 01 = Frame Buffer [9:8]...
Page 404 N9H26 Technical Reference Manual TV Output Filter Register Register Address Description Reset Value TVOUT_FLT 0x44 TV Output Filter Register 0x0000_001A Reserved Reserved Reserved Reserved YLPF_SEL Reserved UVLPF_SEL YUP_SEL UVUP_SEL Descriptions Bits [31:7] Reserved Reserved Luma Low-pass Filter Selection (ref. 1’b0) YLPF_SEL 0 = Disable 1 = 9-tap...
Page 405 N9H26 Technical Reference Manual TV Output Adjust Register Register Address Description Reset Value TVOUT_ADJ 0x48 TV Output Active Adjust Register 0x0000_0000 Reserved VER_ACTADJ Reserved HOR_ACTADJ Reserved Reserved Descriptions Bits [31:29] Reserved Reserved [28:24] VER_ACTADJ TV Vertical Output Active Position Adjust [23:22] Reserved Reserved...
Page 406 N9H26 Technical Reference Manual Color Setting Register Register Address Description Reset Value COLORSET 0x4C RGB888 Single Color Register 0x0000_0000 PRELOAD_EN Reserved VD_SWAP_MODE Color_R Color_G Color_B Descriptions Bits 0: Original mode, load data to line buffer at Hsync pulse. (default) [31] PRELOAD_EN 1: Preload mode, load data to line buffer at previous line end.
Page 407 N9H26 Technical Reference Manual VD_SWAP_MODE mapping Table RGB888 RGB666 RGB565 [00] [01] [10] [11] [00] [01] [10] [11] [00] [01] [10] [11] Publication Release Date: Sept. 10, 2018 - 407 - Revision V1.01...
Page 408 N9H26 Technical Reference Manual Frame Buffer Start Address Register Register Address Description Reset Value FSADDR 0x50 Frame Buffer Start Address 0x0000_0000 FSADDR[31:24] FSADDR[23:16] FSADDR[15:8] FSADDR[7:0] Descriptions Bits Frame Buffer Start Address [31:0] FSADDR Note: The register can be shadowed by Vsync. Publication Release Date: Sept.
Page 409 N9H26 Technical Reference Manual TV Display Control Register Register Address Description Reset Value TvDisCtl 0x54 TV Display Start Control Register 0x00F0_1593 LCDHB[15:8] LCDHB[7:0] TVDVS TVDHS Descriptions Bits LCDHB [31:16] LCD H blank setting for Sync TV Display (8’hf0) TVDVS [15:8] TV Display Start Line Register (8’h15) TV Display Start Pixel Register...
Page 410 N9H26 Technical Reference Manual SD Start Address Register Register Address Description Reset Value OSD_ADDR 0x5C OSD Frame Buffer Start Address 0x0000_0000 OSD_ADDR[31:24] OSD_ADDR[23:16] OSD_ADDR[15:8] OSD_ADDR[7:0] Descriptions Bits OSD Frame Buffer Start Address [31:0] OSD_ADDR Note: The register can be shadowed by Vsync. Publication Release Date: Sept.
Page 411 N9H26 Technical Reference Manual TV Flick Free Filter Set1 Register Register Address Description Reset Value TV_FFFSET1 0x60 TV Flick Free Filter Setting 1 0x0000_0008 Reserved Reserved Reserved Descriptions Bits [31:8] Reserved Reserved [7:0] W22 parameter setting Weighting Coefficient Table Reference: These registers are located on the TV_FFFSET1 & TV_FFFSET2 register Publication Release Date: Sept.
Page 412 N9H26 Technical Reference Manual TV Contrast Adjust Control Register Register Address Description Reset Value TvContrast 0x64 Tv contrast adjust setting register 0x0080_8080 Reserved Cr_contrast Cb_contrast Y_contrast Descriptions Bits [31:24] Reserved Reserved [23:16] Cr_contrast Cr component contrast adjust [15:8] Cb_contrast Cb component contrast adjust [7:0] Y_contrast Y component contrast adjust...
Page 413 N9H26 Technical Reference Manual TV Bright Adjust Control Register Register Address Description Reset Value TvBright 0x68 Tv Bright adjust setting register 0x0000_0000 Reserved Cr_gain Cb_gain Y_bright Descriptions Bits [31:24] Reserved Reserved [23:16] Cr_gain Cr component bright adjust [15:8] Cb_gain Cb component bright adjust [7:0] Y_bright Y component bright adjust...
Page 414 N9H26 Technical Reference Manual TV Flick Free Filter Set2 Register Register Address Description Reset Value TV_FFFSET2 0x6C TV Flick Free Filter Setting 2 0x0001_1000 Descriptions Bits [31:28] W33 weighting setting [27:24] W23 weighting setting [23:20] W13 weighting setting [19:16] W32 weighting setting [15:12] W12 weighting setting [11:8]...
Page 415 N9H26 Technical Reference Manual Line Stripe Offset Register Register Address Description Reset Value LINE_STRIPE 0x70 Line Stripe Offset Register 0x0000_0000 OSD_LSL[15:8] OSD_LSL[7:0] F1_LSL[15:8] F1_LSL[7:0] Descriptions Bits OSD Buffer Line Stripe Offset Register [31:16] OSD_LSL Note: The register can be shadowed by Vsync. Frame Buffer Line Stripe Offset Register [15:0] F1_LSL...
Page 416 N9H26 Technical Reference Manual RGB88 Data Input Register Register Address Description Reset Value RGBin 0x74 RGB 888 Data Input for RGB2YCbCr equation 0x0000_0000 Reserved Descriptions Bits [31:24] Reserved Reserved [23:16] Red Byte Data Input [15:8] Green Byte Data Input [7:0] Blue Byte Data Input Publication Release Date: Sept.
Page 417 N9H26 Technical Reference Manual YCbCr Data Output Register Register Address Description Reset Value YCbCrout 0x78 YCbCr Data Output for RGB2YCbCr equation 0x0010_8080 Reserved Yout Cbout Crout Descriptions Bits [31:24] Reserved Reserved [23:16] Yout Red Byte Data Output [15:8] Cbout Green Byte Data Output [7:0] Crout Blue Byte Data Output...
Page 418 N9H26 Technical Reference Manual YCbCr Data Input Register Register Address Description Reset Value YCbCrin 0x7C YCbCr Data Input for YCbCr2RGB equation 0x0010_8080 Reserved Cbin Crin Descriptions Bits [31:24] Reserved Reserved [23:16] Red Byte Data Input [15:8] Cbin Green Byte Data Input [7:0] Crin Blue Byte Data Input...
Page 419 N9H26 Technical Reference Manual RGB Data Output Register Register Address Description Reset Value RGBout 0x80 RGB Data Output for YCbCr2RGB equation 0x0010_1010 Reserved Rout Gout Bout Descriptions Bits [31:24] Reserved Reserved [23:16] Rout Red Byte Data Output [15:8] Gout Green Byte Data Output [7:0] Bout Blue Byte Data Output...
Page 420 N9H26 Technical Reference Manual OSD Transparent Mask Control Register Register Address Description Reset Value OSD_TC_MASK 0x90 OSD Transparent mask control 0x0000_0000 Reserved OSD_MASK[23:16] OSD_MASK[15:8] OSD_MASK[7:0] Descriptions Bits [31:24] Reserved Reserved OSD Transparent Mask Setting for RGB555 & RGB565 & YUV422 format (OSD_CONALPHA_EN must be 0) RGB555: R5=OSD_MASK[14:10]...
Page 421 N9H26 Technical Reference Manual OSD Constant Alpha Setting Register Register Address Description Reset Value OSD_CONT_ALPHA 0x94 OSD Constant Alpha Setting 0x0000_0000 OSD_CONAL Reserved PHA_EN Reserved Reserved OSD_CONALPHA Descriptions Bits OSD Constant Enable [31] OSD_CONALPHA_EN (when OSD_CONALPHA_EN=1, the OSD_TPEN will be disable) [30:8] Reserved Reserved...
Page 422 N9H26 Technical Reference Manual VA_TEST Register Register Address Description Reset Value VA_TEST 0x98 Frame Buffer Check Sum 0x0000_0000 CHECK_STAR Reserved Reserved CHECK_SUM[15:8] CHECK_SUM[7:0] Descriptions Bits Check Sum Start Control (default 0) [31] CHECK_START 1’b1: HW will enable checksum adder from next Vsync signal. 1’b0: HW will disable checksum adder from next Vsync signal.
Page 423 N9H26 Technical Reference Manual Check Sum Data Valid Timing. SW can read after two Vsync delay Vsync CHECK_SUM adding CHECK_SUM Finish Publication Release Date: Sept. 10, 2018 - 423 - Revision V1.01...
Page 424 N9H26 Technical Reference Manual KPI_HS_DLY Register Register Address Description Reset Value KPI_HS_DLY 0x9C LCD share Hsync Bus to KPI Time Setting 0x000A_001E KPI_REF_SY Reserved KPI_HFD[10:8] KPI_HFD[7:0] Reserved KPI_HBD[10:8] KPI_HBD[7:0] Descriptions Bits Set to 1 will use larger timing range to share LCD bus: [31] KPI_REF_SYNC 0: Switch to KPI only in HSPW, 1: Switch to KPI in HFPD+HSPW+HBPD...
Page 425 N9H26 Technical Reference Manual Left guard band to protect KPI scan out signal . KPI_REF_SYNC = 0 HFPD HSPW HBPD LCD_DE LCD_Hsync KPI_BFD KPI Scanout Active KPI_HFD KPI scan-in time VPOST bus Period KPI bus Period KPI_REF_SYNC = 1 HFPD HSPW HBPD LCD_DE...
Page 426 N9H26 Technical Reference Manual Frame Buffer Size Setting Register Register Address Description Reset Value FB_SIZE 0xA0 Frame Buffer Size Setting 0x0000_0000 FB_X[15:8] FB_X[7:0] FB_Y[15:8] FB_Y[7:0] Descriptions Bits Frame Buffer Size X (picture x size -1) [31:16] FB_X Note: The register can be shadowed by Vsync. Frame Buffer Size Y (picture y size -1) [15:0] FB_Y...
Page 427 N9H26 Technical Reference Manual Scaling Output Size Setting Register Register Address Description Reset Value SCO_SIZE 0xA4 Scaling Output Size Setting 0x0000_0000 SCO_X[15:8] SCO_X[7:0] SCO_Y[15:8] SCO_Y[7:0] Descriptions Bits Scaling Output Size X (scaling up x size -1) [31:16] SCO_X Note: The register can be shadowed by Vsync. Scaling Output Size Y (scaling up y size -1) [15:0] SCO_Y...
Page 428 N9H26 Technical Reference Manual VPOST Status Register Register Address Description Reset Value VPOST_STATUS 0xA8 VPOST Status Register 0x0000_0000 Reserved Reserved Reserved Reserved OBUF_UNDE IBUF_UNDER RFLOW FLOW Descriptions Bits [31:2] Reserved Reserved The overflow flag of output buffer. (Write 1 clear) OBUF_UNDERFLOW 0: Normal.
Page 429: Sound Processing Unit (Spu)
N9H26 Technical Reference Manual 5.9 Sound Processing Unit (SPU) 5.9.1 Overview The SPU performs 32 channels audio input and 16-bit stereo output to DAC and I2S. SPU support 3 data-types (E-MDPCM (4bit), PCM16, LP8) with event and raw PCM16 mono/stereo and Tone. 5.9.2 Features ...
Page 430 N9H26 Technical Reference Manual AHB Master Signal Core Master BIU Controller SRAM I2S_SD Register Playback Slave BIU Bank I2S_WS I2S_BCLK Equalizer I2S_MCLK AHB Slave Signal SPU Interrupt Pin descriptions: I2S_SD : I2S Data out I2S_WS : I2S Word Select I2S_BCLK : I2S Bit Clock I2S_MCLK : I2S Master Clock Output SPU_INT : SPU interrupt signal Publication Release Date: Sept.
Page 431: Register Map
N9H26 Technical Reference Manual 5.9.4 Register Map R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written Register Address R/W/C Description Reset Value Base Address: 0xB100_0000 SPU_CTRL SPU_BA + 0x00 Control and Status Register 0x0000_7000 DAC_PAR SPU_BA + 0x04...
Page 432 N9H26 Technical Reference Manual Control and Status Register Register Address R/W/C Description Reset Value SPU_CTRL SPU_BA + 0x00 Control and Status Register 0x0000_7000 Reserved FIFO_SIZE Reserved SPU_RST Reserved RampUpMod Reserved I2S_JUSTIFIE Reserved I2S_EN Reserved SPU_END_FL SPU_END_CT SPU_EN Bits Descriptions Output FIFO Size [28:24] FIFO_SIZE Set this register to configure the output fifo size between 0~31.
Page 433 N9H26 Technical Reference Manual Bits Descriptions if the bit is set to low, the SPU state machine will start again. 1 = STOP the SPU, when Finish the current sample generated. 0 = Re-start the SPU process SPU End Function Flag If setting the SPU_END_CTRL high and the State Machine is stop, this flag will be set to high.
Page 434 N9H26 Technical Reference Manual DAC Parameter Register Register Address Description Reset Value DAC_PAR SPU_BA + 0x04 0x4000_0000 DAC Parameter Register PllSelMod DACRst Reserved ZeroCrossMod ZeroCrossEn EQ_ZERO_EN EQU_EN Reserved Reserved Reserved Descriptions Bits Select the SPU PLL Clock comes from. 1 = PLL Clock from DAC PLL OUT 0 = PLL Clock from Internal PLL.
Page 435: Figure 5.9-1 Setting The Pllselmod = 0
N9H26 Technical Reference Manual Note: Suggesting that using the DAC PLL mode (setting PllSelMod = 1’b1), because if using the clock divider to generate the MCLK, the performance of the audio will be decreased by the PPM shift of the correct frequency.
Page 436 N9H26 Technical Reference Manual DAC AutoGain Control Register Address Description Reset Value DAC_AG SPU_BA + 0x08 0x0000_0000 DAC Auto Gain Control SampleStep GainStep SaveGain Reserved GainMode AutoUpDown AutoStr Descriptions Bits SampleStep Sample Change Step Number [31:24] GainStep Gain Change Step Number [23:16] Save Gain Register SaveGain...
Page 437 N9H26 Technical Reference Manual Equalizer Band Gain Register 0 Register Address Description Reset Value EQGain0 SPU_BA+0x0c 0x7777_7777 Equalizer Band Gain Register 0 Gain08 Gain07 Gain06 Gain05 Gain04 Gain03 Gain02 Gain01 Descriptions Bits [31:28] Gain08 Equalizer Band 08 Gain control (4000Hz @48k) [27:24] Gain07 Equalizer Band 07 Gain control (2000Hz @48k)
Page 438 N9H26 Technical Reference Manual Equalizer Band Gain Register 1 Register Address Description Reset Value EQGain1 SPU_BA+0x10 0x000d_0077 Equalizer Band Gain Register 1 Reserved Reserved Gaindc Reserved Gain10 Gain09 Descriptions Bits [31:20] Reserved Reserved [19:16] Gaindc Equalizer PassThrough Gain control [15:8] Reserved Reserved [7:4]...
Page 439: Channel Enable
N9H26 Technical Reference Manual Channel Enable Register Address R/W/C Description Reset Value CH_EN SPU_BA + 0x14 Channel Enable 0x0000_0000 CH_EN [31:24] CH_EN [23:16] CH_EN [15:8] CH_EN [7:0] Bits Descriptions Channel Enable Register CH_EN Bit 31:0 map to Channel number 31:0 [31:0] CH_EN ...
Page 440 N9H26 Technical Reference Manual Channel Interrupt Flag Register Address R/W/C Description Reset Value CH_IRQ SPU_BA + 0x18 Channel Interrupt Flag 0x0000_0000 CH_IRQ [31:24] CH_IRQ [23:16] CH_IRQ [15:8] CH_IRQ [7:0] Bits Descriptions Channel Interrupt Flag CH_IRQ Bit 31:0 map to Channel number 31:0 [31:0] CH_IRQ ...
Page 441 N9H26 Technical Reference Manual Channel Pause Register Address R/W/C Description Reset Value CH_PAUSE SPU_BA + 0x1C Channel PAUSE 0x0000_0000 CH_PAUSE [31:24] CH_ PAUSE [23:16] CH_ PAUSE [15:8] CH_ PAUSE [7:0] Bits Descriptions Channel Pause Register CH_PAUSE Bit [31:0] map to Channel number [31:0] ...
Page 442: Channel Control Register
N9H26 Technical Reference Manual Channel Control Register Register Address R/W/C Description Reset Value CH_CTRL SPU_BA + 0x20 Channel Control Register 0x0000_0000 Reserved CH_NO[4:0] Reserved VIR_I2C_IRQ_ VIR_I2C_IRQ_ Reserved FN_IRQ_FG Reserved FN_IRQ_EN UP_IRQ UP_DFA UP_PAN UP_VOL UP_PAS_ADD Reserved CH_FN[1:0] Bits Descriptions Select Channel Number (5bits) [28:24] CH_NO Set target channel.
Page 443 N9H26 Technical Reference Manual Bits Descriptions Pan Update in Partial Update Function UP_PAN 0 = Keep Pan setting 1 = Update Pan setting Volume Update in Partial Update Function UP_VOL 0 = Keep Volume setting 1 = Update Volume setting Pass Address Update in Partial Update Function UP_PAS_ADDR 0 = Keep address setting...
Page 444 N9H26 Technical Reference Manual Source Start Address Register Address R/W/C Description Reset Value S_ADDR SPU_BA + 0x24 Source Start Address 0x0000_0000 S_ADDR [31:24] S_ADDR [23:16] S_ADDR [15:8] S_ADDR [7:0] Bits Descriptions Source Start Address, word boundary [31:0] S_ADDR The channel source starts address. Publication Release Date: Sept.
Page 445 N9H26 Technical Reference Manual Threshold Address – Share Register with Tone Pulse Length Register Address R/W/C Description Reset Value M_ADDR SPU_BA + 0x28 Threshold Address 0x0000_0000 M_ADDR [31:24] M_ADDR [23:16] M_ADDR [15:8] M_ADDR [7:0] Bits Descriptions Threshold Address, word boundary [31:0] M_ADDR When the channel current address cross this threshold address, the threshold interrupt flag will...
Page 446 N9H26 Technical Reference Manual Source End Address – Share Register with Tone Amplitude Register Address R/W/C Description Reset Value E_ADDR SPU_BA + 0x2C Source End Address 0x0000_0000 E_ADDR [31:24] E_ADDR [23:16] E_ADDR [15:8] E_ADDR [7:0] Bits Descriptions Source End Address, word boundary The channel source end address.
Page 447 N9H26 Technical Reference Manual Tone Pulse Length – Share Register with Threshold Address Register Address R/W/C Description Reset Value TONE_PULSE SPU_BA + 0x28 Tone Pulse Length 0x0000_0000 TONE_P1 [15:8] TONE_P1 [7:0] TONE_P0 [15:8] TONE_P0 [7:0] Bits Descriptions Tone Pulse Length 1 Tone Pulse Length, Unit is output sampling period.
Page 448 N9H26 Technical Reference Manual Tone Amplitude – Share Register with End Address Register Address R/W/C Description Reset Value TONE_AMP SPU_BA + 0x2C Tone Amplitude 0x0000_0000 TONE_AMP1 [15:8] TONE_AMP1 [7:0] TONE_AMP0 [15:8] TONE_AMP0 [7:0] Bits Descriptions Tone Amplitude 1, 2’s complement [15:0] TONE_AMP1 In the Tone Pulse Length 1 phase, output TONE_AMP1...
Page 449: Channel Parameter
N9H26 Technical Reference Manual Channel Parameter 1 Register Address R/W/C Description Reset Value CH_PAR_1 SPU_BA + 0x30 Channel Parameter 1 Register 0x3F1F_1F00 Reserved CH_VOL [6:0] Reserved PAN_L [4:0] Reserved PAN_R [4:0] Reserved SRC_TYPE [2:0] Bits Descriptions [31] Reserved Reserved [30:24] CH_VOL Channel Volume (7bit) [23:21]...
Page 450 N9H26 Technical Reference Manual Channel Parameter 2 Register Address R/W/C Description Reset Value CH_PAR_2 SPU_BA + 0x34 Channel Parameter 2 Register 0x0000_0400 Reserved Reserved Reserved DFA [12:8] DFA [7:0] Bits Descriptions [31:13] Reserved Reserved DFA (13bit) Set this register for pitch shifting and changing source sampling rate. DFA is divided into 3-bit integral part (DFA[12:10]) and 10-bit fractional part (DFA[9:0]).
Page 451 N9H26 Technical Reference Manual Channel Event Register Register Address R/W/C Description Reset Value CH_EVENT SPU_BA + 0x38 Channel Event Register 0x0000_0080 SUB_IDX [7:0] EVENT_IDX [7:0] Reserved EV_USR_FG EV_SLN_FG EV_LP_FG EV_END_FG END_FG TH_FG AT_CLR_EN Reserved EV_USR_EN EV_SLN_EN EV_LP_EN EV_END_EN END_EN TH_EN Bits Descriptions [31:24]...
Page 452 N9H26 Technical Reference Manual Bits Descriptions END_EN End Address Interrupt Enable TH_EN Threshold Address Interrupt Enable Publication Release Date: Sept. 10, 2018 - 452 - Revision V1.01...
Page 453 N9H26 Technical Reference Manual Channel Current Address Register Address R/W/C Description Reset Value CUR_ADDR SPU_BA + 0x40 Channel current address Register 0x0000_0000 CUR_ADDR [31:24] CUR_ADDR [23:16] CUR_ADDR [15:8] CUR_ADDR [7:0] Bits Descriptions Channel current address [31:0] CUR_ADDR It shows the information that the playback process has played on which location (address). Publication Release Date: Sept.
Page 454 N9H26 Technical Reference Manual Loop Start Address Register Address R/W/C Description Reset Value LP_ADDR SPU_BA + 0x44 Loop Start Address 0x0000_0000 LP_ADDR [31:24] LP_ADDR [23:16] LP_ADDR [15:8] LP_ADDR [7:0] Bits Descriptions Loop Start Address [31:0] LP_ADDR When loop start event occur, the address will keep in this register. Publication Release Date: Sept.
Page 455 N9H26 Technical Reference Manual Pause Address for Mono/Stereo PCM16 – Share Register with Loop Start Address Register Address R/W/C Description Reset Value PA_ADDR SPU_BA + 0x44 Pause Address for mono/stereo PCM16 format 0x0000_0000 PA_ADDR [31:24] PA_ADDR [23:16] PA_ADDR [15:8] PA_ADDR [7:0] Bits Descriptions Pause Address for mono/stereo PCM16 format...
Page 456 N9H26 Technical Reference Manual DAC Control Command Register Register Address R/W/C Description Reset Value DAC_CTRL SPU_BA + 0x50 DAC Control Interface Command 0x0000_0000 BUSY SCK_DIV DEVICE_ID ADDR DATA Bits Descriptions If this register has been written, the HW would change the command to the I2C format. It is because the DAC interface is only I2C.
Page 457 N9H26 Technical Reference Manual DAC Control Register Address: Left Channel Analog Volume Control Register (Address: 00H; Default: 00H; Access: R/W) BITS LABEL DEFAULT DESCRIPION [7:5] Reserved DAC Left Channel Gain Control. The value can be programmed from 00h to 1FH, stepped by -2dB [4:0] AVOLL 0_0000...
Page 458 N9H26 Technical Reference Manual 0001_0100 0101_0011 0000_0001 0001_0100 0101_0011 0000_0100 0001_0100 0100_1100 0000_0000 44.1K 0001_0100 0101_0011 0000_0000 0001_0100 0101_0011 0000_1000 Note: F_out = F_in * (N / M) * (1 / P); And DVIM = M – 1; DVIN = N – 1; DP = 0x08 =>...
Page 459 N9H26 Technical Reference Manual 010: Medium Big Biasing Resistor 001: Biggest Biasing Resistor Other: Reserved DAC power Down Control Register (Address: 05H; Default: FFH; Access: R/W) BITS LABEL DEFAULT DESCRIPION Bypass mode control input: 0: normal mode for PLL BYPASSPLL 1: bypass mode, PLL input goes to the PLL output frequency divider, and then to the output PLL power down control mode:...
Page 460 N9H26 Technical Reference Manual DAC Control Register (Address: 07H; Default: 00H; Access: R/W) BITS LABEL DEFAULT DESCRIPION [7:3] Reserved 0_0000 DAC Stereo/Mono Control Signal Or Digital Filter Soft Reset Control: 00: Stereo mode [2:1] DAC_MODE 01: L Mono mode 10: R Mono mode 11: (L+R)/2 Mono mode 0: Digital DAC Disabled DACEN...
Page 461: I2S Controller
N9H26 Technical Reference Manual 5.10 I2S Controller 5.10.1 Overview The audio controller consists of I2S protocols to interface with external audio CODEC. The I2S interface supports 16, 18, 20 and 24-bit left/right precision in record and playback. When operating in 18/20/24-bit precision, each left/right-channel sample is stored in a 32-bit word.
Page 462: Block Diagram
N9H26 Technical Reference Manual 5.10.3 Block diagram AHB Bus Interface AHB Slave AHB Bus Master Master RFIFO PFIFO Control Record Play Contro Contro Registers FIFO Control FIFO AUDIO Interface Figure 5.10-1 Block diagram of Audio Controller Publication Release Date: Sept. 10, 2018 - 462 - Revision V1.01...
Page 463: I2S Interface
N9H26 Technical Reference Manual 5.10.4 I2S Interface The I2S interface signals are shown as the following figure BCLK Audio Audio Controller Figure 5.10-2 The interface signal of I2S The I2S and MSB-justified format are supported; the timing diagram is shown as following figure. Figure 5.10-3 The format of I2S The sampling rate, bit shift clock frequency could be set by the control register ACTL_I2SCON.
Page 464: Audio Controller Register Map
N9H26 Technical Reference Manual 5.10.5 Audio Controller Register Map R: read only, W: write only, R/W: both read and write, C: Only value 1 can be written Register Address Description Reset Value I2S_BA = 0xB100_1000 ACTL_CON I2S_BA + 0x00 Audio control register 0x0000_0000 ACTL_RESET I2S_BA + 0x04...
Page 465: Register Description
N9H26 Technical Reference Manual 5.10.6 Register Description Audio Controller Control Register (ACTL_CON) Register Address Description Reset Value ACTL_CON I2S_BA + 0x00 Audio controller control register 0x0000_0000 The ACTL_CON register control the basic operation of audio controller. Reserved Reserved R_PAUSE_IR R_DMA_ P_DMA_IRQ_ R_FIFO_FULL R_FIFO_EMP...
Page 466 N9H26 Technical Reference Manual Bits Descriptions 1: allowed to generation P_FIFO_FULL_IRQ The P_FIFO_FULL_IRQ_EN bit is read/write Playback FIFO Empty Interrupt Request Enable bit 0: not allowed to generation P_FIFO_EMPTY_IRQ [16] P_FIFO_EMPTY_IRQ_EN 1: allowed to generation P_FIFO_EMPTY_IRQ The P_FIFO_EMPTY_IRQ_EN bit is read/write Record DMA Interrupt Request Selection bits 00: When record DMA address reach DMA record destination end address, the R_DMA_RIA_IRQ will be issued.
Page 467 N9H26 Technical Reference Manual Bits Descriptions 0: The FIFO threshold is 8 levels. 1: The FIFO threshold is 4 levels. The FIFO_TH bit is read/write [6:5] RESERVED RESERVED IRQ_DMA counter function enable Bit 0: not allowed to generation P_DMA_IRQ IRQ_DMA_CNTER_EN 1: allowed to generation P_DMA_IRQ The IRQ_DMA_CNTER_EN bit is read/write IRQ_DMA_DATA zero and sign detect enable bit...
Page 468 N9H26 Technical Reference Manual Sub-block Reset Control Register (ACTL_RESET) Register Address Description Reset Value ACTL_RESET I2S_BA + 0x04 Sub block reset control 0x0000_0000 The ACTL_RESET register control the reset operation in each sub block. Reserved Reserved ACTL_RESET RECORD_SINGLE[1:0] Reserved PLAY_STERE Reserved Reserved I2S_RECORD...
Page 469 N9H26 Technical Reference Manual Bits Descriptions The I2S_PLAY bit is read/write DMA counter function enable Bit This function is supported to count playback data for software monitoring. When one playback data is transferred to codec, the DMA counter subtracts 1. When the ACTL_COUNTER [31:0] register is Zero that set DMA_CNTER_IRQ bit =1.
Page 470 N9H26 Technical Reference Manual DMA Record Destination Base Address (ACTL_RDESB) Register Address Description Reset Value ACTL_RDESB I2S_BA + 0x08 DMA record destination base address 0x0000_0000 The value in ACTL_RDESB register is the record destination base address of DMA, and only could be changed by CPU. AUDIO_RDESB[31:24] AUDIO_RDESB[23:16] AUDIO_RDESB[15:8]...
Page 471 N9H26 Technical Reference Manual DMA Record Destination Address Length (ACTL_RDES_LENGTH) Register Address R/W Description Reset Value ACTL_RDES_LENGTH I2S_BA + 0x0C R/W DMA record destination address length 0x0000_0000 The value in ACTL_RDES_LENGTH register is the record destination address length of DMA, and the register could only be changed by CPU. AUDIO_RDES_L[31:24] AUDIO_RDES_L[23:16] AUDIO_RDES_L[15:8]...
Page 472 N9H26 Technical Reference Manual DMA Record Destination Current Address (ACTL_RDESC) Register Address Description Reset Value ACTL_RDESC I2S_BA + 0x10 DMA record destination current address 0x0000_0000 The value in ACTL_RDESC is the DMA record destination current address; this register could only be read by CPU. AUDIO_RDESC[31:24] AUDIO_RDESC[23:16] AUDIO_RDESC[15:8]...
Page 473 N9H26 Technical Reference Manual DMA Play Destination Base Address (ACTL_PDESB) Register Address Description Reset Value ACTL_PDESB I2S_BA + 0x14 DMA play destination base address 0x0000_0000 The value in ACTL_PDESB register is the play destination base address of DMA, and only could be changed by CPU.
Page 474 N9H26 Technical Reference Manual DMA Play Destination Address Length (ACTL_PDES_LENGTH) Register Address R/W Description Reset Value ACTL_PDES_LENGTH I2S_BA + 0x18 DMA play destination address length 0x0000_0000 The value in ACTL_PDES_LENGTH register is the play destination address length of DMA, and the register could only be changed by CPU. AUDIO_PDES_L[31:24] AUDIO_PDES_L[23:16] AUDIO_PDES_L[15:8]...
Page 475 N9H26 Technical Reference Manual DMA Play Destination Current Address (ACTL_PDESC) Register Address Description Reset Value ACTL_PDESC I2S_BA + 0x1C DMA play destination current address 0x0000_0000 The value in ACTL_PDESC is the play destination current address of DMA; this register could only be read by CPU. AUDIO_PDESC[31:24] AUDIO_PDESC[23:16] AUDIO_PDESC[15:8]...
Page 476 N9H26 Technical Reference Manual Audio Controller Record Status Register (ACTL_RSR) Register Address R/W Description Reset Value ACTL_RSR I2S_BA + 0x20 Audio controller FIFO and DMA status register for record 0x0000_0000 Reserved Reserved Reserved R_DMA_RIA_SN[2:0] Reserved R_FIFO_FULL R_FIFO_EMP R_DMA_RIA_I Bits Descriptions [31:8] RESERVED RESERVED...
Page 477 N9H26 Technical Reference Manual Audio Controller Playback Status Register (ACTL_PSR) Register Address R/W Description Reset Value ACTL_PSR I2S_BA + 0x24 R/W Audio controller FIFO and DMA status register for playback 0x0000_0000 Reserved Reserved Reserved P_DMA_RIA_SN[2:0] DMA_CNTER DMA_DATA_Z P_FIFO_FULL P_FIFO_EMP P_DMA_RIA_I _IRQ ERO_IRQ Bits...
Page 478 N9H26 Technical Reference Manual Bits Descriptions Playback FIFO EMPTY Indicator bit When playback FIFO is empty and the playback data is read from FIFO, the P_FIFO_EMPTY bit is set to 1. This bit indicates the FIFO empty error is happened. P_FIFO_EMPTY 0: the P_FIFO empty error is not happened.
Page 479 N9H26 Technical Reference Manual I2S Control Register (ACTL_I2SCON) Register Address Description Reset Value ACTL_I2SCON I2S_BA + 0x28 I2S control register 0x0000_0000 Reserved Reserved PRS[3:0] Reserved BCLK_SEL[1:0] WS_SEL MCLK_SEL FORMAT Reserved Bits Descriptions [31:20] RESERVED RESERVED I2S Frequency PRE_SCALER Selection bits. (FPLL is the input PLL frequency, MCLK is the output main clock) 0000: MCLK=FPLL/1 0001: MCLK=FPLL/2...
Page 480 N9H26 Technical Reference Manual Bits Descriptions 1x: RESERVED The BCLK_SEL[1:0] bits are read/write I2S Sampling Word Selection Bit If BCLK_SEL[1:0]=00, and WS_SEL=0, 32ws is selected, the word selection (WS) = MCLK/(8*32) = MCLK/(256) If BCLK_SEL[1:0]=00, and WS_SEL=1, 48ws is selected, the word selection (WS) = MCLK/(8*48) = MCLK/(384) If BCLK_SEL[1:0]=01, this bit is ignored, 32ws is selected, the word selection (WS) = MCLK/(12*32) = MCLK/(384)
Page 481 N9H26 Technical Reference Manual DOWN_COUNTER Control Register (ACTL_COUNTER) Register Address Description Reset Value ACTL_COUNTER I2S_BA + 0x2C DMA down counter register 0xFFFF_FFFF ACTL_COUNTER[31:24] ACTL_COUNTER[23:16] ACTL_COUNTER[15:8] ACTL_COUNTER[7:0] Bits Descriptions ACTL_COUNTER is Read and Write Data. [31:0] ACTL_COUNTER[31:0] The ACTL_COUNTER [31:0] bits are read and write. When the register is Zero that set DMA_CNTER_IRQ bit =1.
Page 482 N9H26 Technical Reference Manual Pause Function Length Location (ACTL_PauseLength) Register Address Description Reset Value ACTL_PauseLength I2S_BA + 0x30 Pause Function Length Location 0xFFFF_FFFF ACTL_COUNTER[31:24] ACTL_COUNTER[23:16] ACTL_COUNTER[15:8] ACTL_COUNTER[7:0] Bits Descriptions Pause Function Length Location Information When use the Pause Function to set which location should be stop, we can set the length in this register.
Page 483: Storage Interface Controller
N9H26 Technical Reference Manual 5.11 Storage Interface Controller 5.11.1 Overview The Storage Interface Controller (SIC) has DMAC unit and FMI unit. The DMAC unit provides a DMA (Direct Memory Access) function for FMI to exchange data between system memory and shared buffer (128 bytes).
Page 484: Block Diagram And Card Pad Assignment
N9H26 Technical Reference Manual 5.11.3 Block Diagram and Card Pad Assignment The block diagram and Card Pad Assignment of SIC Controller is shown as following. Figure 5.11-1 SIC Controller Block Diagram Publication Release Date: Sept. 10, 2018 - 484 - Revision V1.01...
Page 485 N9H26 Technical Reference Manual Table 5.11-1SD/SDHC/SDIO/MMC Card Pad Assignment NAME Description SD_DAT0 SD Data (bit 0) SD_DAT1 SD Data (bit 1) SD_DAT2 SD Data (bit 2) SD_DAT3 SD Data (bit 3) SD_CMD SD Command / Response SD_CLK SD Clock pin SD_CD Card Detect (Source can be GPIO or DAT3 (in SDIER) Table 5.11-2 NAND/SM Card Pad Assignment...
Page 486: Sic Controller Registers Map
N9H26 Technical Reference Manual 5.11.4 SIC Controller Registers Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value Shared Buffer (DMAC_BA = 0xB100_6000) FMI_FB_0 DMAC_BA+0x000 …… …… Shared Buffer (FIFO) 0x0000_0000 FMI_FB_32 DMAC_BA+0x07C DMAC Registers (DMAC_BA = 0xB100_6400) DMACCSR DMAC_BA+0x00...
Page 487 N9H26 Technical Reference Manual Register Offset Description Reset Value SMREAREA_CTL FMI_BA + 0xBC Smart-Media Redundant Area Control Register 0x0000_0000 SM_ECC_ST0 FMI_BA + 0xD0 Smart-Media ECC Error Status 0 0x0000_0000 SM_ECC_ST1 FMI_BA + 0xD4 Smart-Media ECC Error Status 1 0x0000_0000 SM_ECC_ST2 FMI_BA + 0xD8 Smart-Media ECC Error Status 2 0x0000_0000...
Page 488: Sic Dma Controller
N9H26 Technical Reference Manual 5.11.5 SIC DMA Controller The DMA Controller provides a DMA (Direct Memory Access) function for FMI controller to exchange data between system memory (ex. SDRAM) and shared buffer (128 bytes). Arbitration of DMA request between FMI is done by DMAC’s bus master. Software just simply fills in the starting address and enables DMAC, and then you can let DMAC to handle the data transfer automatically.
Page 489: Figure 5.11-2 Dma Controller Symbol Diagram
N9H26 Technical Reference Manual 5.11.5.2 Symbol Diagram The symbol diagram of DMA Controller is shown as following. Figure 5.11-2 DMA Controller Symbol Diagram Publication Release Date: Sept. 10, 2018 - 489 - Revision V1.01...
Page 490: Figure 5.11-3 Dma Controller Block Diagram
N9H26 Technical Reference Manual 5.11.5.3 Block Diagram The block diagram of DMA Controller is shown as following. Figure 5.11-3 DMA Controller Block Diagram Publication Release Date: Sept. 10, 2018 - 490 - Revision V1.01...
Page 491 N9H26 Technical Reference Manual 5.11.5.4 Programming Flow Here is a simple example programming flow without DMA Scatter-Gather enable. 1. Set DMACCSR [DMACEN] to enable DMAC. 2. Fill corresponding starting address in DMACSAR for FMI. 3. Enable IP to start DMA transfer. 4.
Page 492: Dmac Register Detail
N9H26 Technical Reference Manual 5.11.6 DMAC Register Detail Publication Release Date: Sept. 10, 2018 - 492 - Revision V1.01...
Page 493 N9H26 Technical Reference Manual DMAC Control and Status Register (DMACCSR) Register Offset Description Reset Value DMACCSR 0x00 DMAC Control and Status Register 0x0000_0000 Reserved Reserved Reserved FMI_BUSY Reserved Reserved SG_EN2 Reserved SW_RST DMACEN Bits Descriptions [31:10] Reserved Reserved FMI DMA Transfer is in progress This bit indicates if FMI is granted and doing DMA transfer or not.
Page 494 N9H26 Technical Reference Manual DMAC Transfer Starting Address Register (DMACSAR) Register Offset Description Reset Value DMACSAR 0x08 DMAC Transfer Starting Address Register 0x0000_0000 DMACSA[31:24] DMACSA[23:16] DMACSA[15:8] DMACSA[7:0] Bits Descriptions DMA Transfer Starting Address for FMI This field indicates a 32-bit starting address of system memory (SRAM/SDRAM) for DMAC to [31:0] DMACSA retrieve or fill in data (for FMI engine).
Page 495 N9H26 Technical Reference Manual DMAC Transfer Byte Count Register (DMACBCR) Register Offset Description Reset Value DMACBCR 0x0C DMAC Transfer Byte Count Register 0x0000_0000 Reserved BCNT[25:24] BCNT[23:16] BCNT[15:8] BCNT[7:0] Bits Descriptions [31:26] Reserved Reserved DMA Transfer Byte Count (Read Only) [25:0] BCNT This field indicates the remained byte count of DMAC transfer.
Page 496 N9H26 Technical Reference Manual DMAC Interrupt Enable Register (DMACIER) Register Offset Description Reset Value DMACIER 0x10 DMAC Interrupt Enable Register 0x0000_0001 Reserved Reserved Reserved Reserved WEOT_IE TABORT_IE Bits Descriptions [31:2] Reserved Reserved Wrong EOT Encountered Interrupt Enable WEOT_IE 0 = Disable interrupt generation when wrong EOT is encountered. 1 = Enable interrupt generation when wrong EOT is encountered.
Page 497 N9H26 Technical Reference Manual DMAC Interrupt Status Register (DMACISR) Register Offset Description Reset Value DMACISR 0x14 DMAC Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved WEOT_IF TABORT_IF Bits Descriptions [31:2] Reserved Reserved Wrong EOT Encountered Interrupt Flag When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of FMI), this bit will be set.
Page 498: Flash Memory Interface Controller (Fmi)
N9H26 Technical Reference Manual 5.12 Flash Memory Interface Controller (FMI) 5.12.1 Overview The Flash Memory Interface supports Secure-Digital SD/SDHC/SDIO/MMC and NAND-type flash. FMI is cooperated with DMAC to provide a fast data transfer between system memory and cards. There is a single 128 bytes buffer embedded in DMAC for temporary data storage (separate into two 64 bytes ping-pong FIFO).
Page 499: Symbol Diagram
N9H26 Technical Reference Manual 5.12.3 Symbol Diagram The symbol diagram of FMI Controller is shown as following. Figure 5.12-1 FMI Controller Symbol Diagram Publication Release Date: Sept. 10, 2018 - 499 - Revision V1.01...
Page 500: Block Diagram
N9H26 Technical Reference Manual 5.12.4 Block Diagram A simple block diagram of FMI Controller is shown as following. DMAC DMAC FIFO Interface I/O, Decoder Register Sync Sync HCLK Engine Clock Secure Digital Smart-Media SD Device SM Device Figure 5.12-2 FMI Controller Block Diagram Publication Release Date: Sept.
Page 501: Function Description
N9H26 Technical Reference Manual 5.12.5 Function Description Secure-Digital (SD) FMI provides an interface for SD/SDHC/SDIO/MMC card access. This SD controller provides 3 SD ports –port0, port1 and port2. Each port can provide 1-bit/4-bit data bus mode for SD, but only port0 have card detect function and SDIO interrupt.
Page 502: Figure 5.12-3 Data Arrangement For 2K Page Size And Bch Algorithm
N9H26 Technical Reference Manual NAND-type Flash/Smart-Media Controller. FMI provides an interface for NAND-type Flash/Smart-Media access. It supports 512bytes/page, 2048bytes/page, 4096bytes/page and 8192bytes/page NAND. This NAND-type Flash controller provides all required signals for NAND flash, including R/–B, –CE, CLE, ALE, –WE, –RE and data pins.
Page 503: Figure 5.12-4 Data Arrangement For 4K Page Size Nand Flash
N9H26 Technical Reference Manual Figure 5.12-4 Data arrangement for 4k page size NAND flash Figure 5.12-5 Data arrangement for 8k page size NAND flash Publication Release Date: Sept. 10, 2018 - 503 - Revision V1.01...
Page 504 N9H26 Technical Reference Manual Global Control and Status Register (FMICR) Register Offset Description Reset Value FMICR 0x000 Global Control and Status Register 0x0000_0000 Reserved Reserved Reserved Reserved Reserved SM_EN Reserved SD_EN SW_RST Bits Descriptions [31:5] Reserved Reserved Reserved Reserved Smart-Media Functionality Enable SM_EN 0 = Disable SM functionality of FMI.
Page 505 N9H26 Technical Reference Manual Global Interrupt Control Register (FMIIER) Register Offset Description Reset Value FMIIER 0x004 Global Interrupt Control Register 0x0000_0001 Reserved Reserved Reserved Reserved DTA_IE Bits Descriptions [31:1] Reserved Reserved DMAC READ/WRITE Target Abort Interrupt Enable DTA_IE 0 = Disable DMAC READ/WRITE target abort interrupt generation. 1 = Enable DMAC READ/WRITE target abort interrupt generation.
Page 506 N9H26 Technical Reference Manual Global Interrupt Status Register (FMIISR) Register Offset Description Reset Value FMIISR 0x008 Global Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved DTA_IF Bits Descriptions [31:1] Reserved Reserved DMAC READ/WRITE Target Abort Interrupt Flag (Read Only) This bit indicates DMAC received an ERROR response from internal AHB bus during DMA read/write operation.
Page 507 N9H26 Technical Reference Manual SD Control and Status Register (SDCR) Register Offset Description Reset Value SDCR 0x020 SD Control and Status Register 0x0101_0000 CLK_KEEP1 SDPORT CLK_KEEP2 SDNWR BLK_CNT SW_RST CMD_CODE CLK_KEEP0 CLK8_OE CLK74_OE R2_EN DO_EN DI_EN RI_EN CO_EN Bits Descriptions SD Clock Enable for Port 1 [31] CLK_KEEP1...
Page 508 N9H26 Technical Reference Manual Bits Descriptions This bit will be auto cleared after few clock cycles. SD Command Code [13:8] CMD_CODE This register contains the SD command code (0x00 – 0x3F). SD Clock Enable for Port 0 CLK_KEEP0 0 = Disable SD clock generation. 1 = SD clock always keeps free running.
Page 509 N9H26 Technical Reference Manual SD Command Argument Register (SDARG) Register Offset Description Reset Value SDARG 0x024 SD Command Argument Register 0x0000_0000 SD_CMD_ARG SD_CMD_ARG SD_CMD_ARG SD_CMD_ARG Bits Descriptions SD Command Argument This register contains a 32-bit value specifies the argument of SD command from host [31:0] SD_CMD_ARG controller to SD card.
Page 510 N9H26 Technical Reference Manual SD Interrupt Control Register (SDIER) Register Offset Description Reset Value SDIER 0x028 SD Interrupt Control Register 0x0000_0A00 Reserved CD0SRC Reserved Reserved Reserved WKUP_EN DITO_IE RITO_IE SDIO1_IE SDIO0_IE Reserved CD0_IE Reserved SDIO2_IE CRC_IE BLKD_IE Bits Descriptions [31] Reserved Reserved SD0 Card Detect Source Selection...
Page 511 N9H26 Technical Reference Manual Bits Descriptions 1 = Enable SDIO Interrupt Enable for Port 0 Enable/Disable interrupts generation of SD host when SDIO card 0 issues an interrupt via DAT [1] to host. [10] SDIO0_IE 0 = Disable. 1 = Enable. Reserved Reserved SD0 Card Detection Interrupt Enable...
Page 512 N9H26 Technical Reference Manual SD Interrupt Status Register (SDISR) Register Offset Description Reset Value SDISR 0x02C SD Interrupt Status Register 0x000x_008C Reserved Reserved SDIO2_IF Reserved SD2DAT1 SD1DAT1 SD0DAT1 Reserved CDPS0 Reserved Reserved DITO_IF RITO_IF SDIO1_IF SDIO0_IF Reserved CD0_IF SDDAT0 CRCSTAT CRC-16 CRC-7 CRC_IF...
Page 513 N9H26 Technical Reference Manual Bits Descriptions Data Input Time-out Interrupt Flag (Read Only) This bit indicates that SD host counts to time-out value when receiving data (waiting start bit). [13] DITO_IF 0 = Not time-out. 1 = Data input time-out. NOTE: This bit is read only, but can be cleared by writing ‘1’...
Page 514 N9H26 Technical Reference Manual Bits Descriptions CRC-7 Check Status (Read Only) SD host will check CRC-7 correctness during each response in. If that response does not contain CRC-7 information (ex. R3), then software should turn off SDIER [CRC_IE] and CRC-7 ignore this bit.
Page 515 N9H26 Technical Reference Manual SD Receiving Response Token Register 0 (SDRSP0) Register Offset Description Reset Value SDRSP0 0x030 SD Receiving Response Token Register 0 0x0000_0000 SD_RSP_TK0 SD_RSP_TK0 SD_RSP_TK0 SD_RSP_TK0 Bits Descriptions SD Receiving Response Token 0 [31:0] SD_RSP_TK0 SD host controller will receive a response token for getting a reply from SD card when SDCR [RI_EN] is set.
Page 516 N9H26 Technical Reference Manual SD Receiving Response Token Register 1 (SDRSP1) Register Offset Description Reset Value SDRSP1 0x034 SD Receiving Response Token Register 1 0x0000_0000 Reserved Reserved Reserved SD_RSP_TK1 Bits Descriptions SD Receiving Response Token 1 [7:0] SD_RSP_TK1 SD host controller will receive a response token for getting a reply from SD card when SDCR [RI_EN] is set.
Page 517 N9H26 Technical Reference Manual SD Block Length Register (SDBLEN) Register Offset Description Reset Value SDBLEN 0x038 SD Block Length Register 0x0000_01FF Reserved Reserved Reserved SDBLEN SDBLEN Bits Descriptions SD BLOCK LENGTH in Byte Unit An 11-bit value specifies the SD transfer byte count of a block. The actual byte count is [10:0] SDBLEN equal to SDBLEN+1.
Page 518 N9H26 Technical Reference Manual SD Response/Data-in Time-out Register (SDTMOUT) Register Offset Description Reset Value SDTMOUT 0x03C SD Response/Data-in Time-out Register 0x0000_0000 Reserved SDTMOUT SDTMOUT SDTMOUT Bits Descriptions SD Response/Data-in Time-out Value A 24-bit value specifies the time-out counts of response and data input. SD host controller will wait start bit of response or data-in until this value reached.
Page 519 N9H26 Technical Reference Manual Smart-media Control and Status Register (SMCR) Register Address Description Reset Value SMCR FMI_BA+0x0A0 Smart-Media Control and Status Register 0x1E88_0090 FAILED FINISH BIST_EN Reserved SM_CS1 SM_CS0 Reserved ECC_EN BCH_TSEL PSIZE Reserved SRAM_INT PROT_3BEN ECC_CHK Reserved PROT_REGIO REDUN_AUT REDUN_REN DWR_EN DRD_EN...
Page 520 N9H26 Technical Reference Manual ECC Algorithm Enable This field is used to select the ECC algorithm for data protecting. The BCH algorithm can correct 4 or 8 or 12 or 15 or 24 bits. 1 = Enable BCH code encode/decode. 0 = Disable BCH code encode/decode.
Page 521 N9H26 Technical Reference Manual Reserved Reserved Protect Region Enable This field is used to protect NAND Flash region from address 0 to address {SM_PROT_ADDR1,, SM_PROT_ADDR0} not be written. PROT_REGION_EN 0 = Disable 1 = Enable Redundant Area Auto Write Enable This field is used to auto write redundant data out to NAND Flash card.
Page 522 N9H26 Technical Reference Manual Smart-media Timing Control Register (SMTCR) Register Offset Description Reset Value SMTCR 0x0A4 Smart-Media Timing Control Register 0x0001_0105 Reserved Reserved CALE_SH HI_WID LO_WID Bits Descriptions [31:23] Reserved Reserved CLE/ALE Setup/Hold Time This field controls the CLE/ALE setup/hold time to –WE. The setup/hold time can be calculated using following equation: [22:16] CALE_SH...
Page 523 N9H26 Technical Reference Manual Smart-media Interrupt Control Register (SMIER) Register Address Description Reset Value SMIER FMI_BA+0x0A8 Smart-Media Interrupt Control Register 0x0000_0000 Reserved Reserved Reserved RB1_IE RB0_IE Reserved Reserved PROT_REGIO ECC_FLD_IE Reserved DMA_IE N_WR_IE Bits Descriptions [31:12] Reserved Reserved Ready/-Busy 1 Rising Edge Detect Interrupt Enable [11] RB1_IE 0 = Disable R/-B rising edge detect interrupt generation.
Page 524 N9H26 Technical Reference Manual Smart-media Interrupt Status Register (SMISR) Register Address Description Reset Value SMISR FMI_BA+0x0AC Smart-Media Interrupt Status Register 0x000X_0000 Reserved Reserved RB1_Status RB0_Status Reserved Reserved RB1_IF RB0_IF Reserved Reserved PROT_REGIO ECC_FLD_IF Reserved DMA_IF N_WR_IF Bits Descriptions [31:19] Reserved Reserved Ready/-Busy 1 Pin Status (Read Only) [19]...
Page 525 N9H26 Technical Reference Manual Bits Descriptions 0 = Error not occurrence. 1 = Error occurrence NOTE: This bit is read only, but can be cleared by writing ‘1’ to it. Reserved Reserved DMA Read/Write Data Complete Interrupt Flag (Read Only) 0 = DMA read/write transfer is not finished yet.
Page 526 N9H26 Technical Reference Manual Smart-media Command Port Register (SMCMD) Register Address Description Reset Value SMCMD FMI_BA+0x0B0 Smart-Media Command Port Register Reserved Reserved Reserved SMCMD Bits Descriptions [31:8] Reserved Reserved Smart-Media Command Port [7:0] SMCMD When CPU writes to this port, SM H/W circuit will send a command to Smart-Media card. Publication Release Date: Sept.
Page 527 N9H26 Technical Reference Manual Smart-media Address Port Register (SMADDR) Register Address Description Reset Value SMADDR FMI_BA+0x0B4 Smart-Media Address Port Register Reserved Reserved Reserved SMADDR Bits Descriptions End of Address Writing this bit to tell SM host if this address is the last one or not. When software first writes to address port with this bit cleared, SM host will set ALE pin to active (HIGH).
Page 528 N9H26 Technical Reference Manual Smart-media Data Port Register (SMDATA) Register Address Description Reset Value SMDATA FMI_BA+0x0B8 Smart-Media Data Port Register Reserved Reserved Reserved SMDATA Bits Descriptions [31:8] Reserved Reserved Smart-Media Data Port CPU can access NAND’s memory array through this data port. When CPU WRITE, the [7:0] SMDATA lower 8-bit data from CPU will appear on the data bus of NAND controller.
Page 529 N9H26 Technical Reference Manual Smart-media Redundant Area Control Register (SMREAREA_CTL) Register Address Description Reset Value Smart-Media Redundant Area SMREAREA_CTL FMI_BA+0x0BC 0x0000_0000 Control Register MECC MECC Reserved REA128_ext REA128_ext Bits Descriptions Mask ECC During Write Page Data. These 16 bits registers indicate NAND controller to write out ECC parity or just 0xFF for each field (every 512 bytes) the real parity data will be write out to SMRAx.
Page 530 N9H26 Technical Reference Manual Smart-media ECC Error Status 0 (SM_ECC_ST0) Register Address Description Reset Value SM_ECC_ST0 FMI_BA+0x0D0 Smart-Media ECC Error Status 0 0x0000_0000 Reserved F4_ECNT F4_STAT Reserved F3_ECNT F3_STAT Reserved F2_ECNT F2_STAT Reserved F1_ECNT F1_STAT Bits Descriptions [31] Reserved Reserved Error Count of ECC Field 4 This field contains the error counts after ECC correct calculation of Field 4.
Page 531 N9H26 Technical Reference Manual Bits Descriptions ECC Status of Field 2 This field contains the ECC correction status (BCH algorithm) of ECC-field 2. [9:8] F2_STAT 00 = No error. 01 = Correctable error. 10 = Uncorrectable error. Reserved Reserved Error Count of ECC Field 1 This field contains the error counts after ECC correct calculation of Field 1.
Page 532 N9H26 Technical Reference Manual Smart-media ECC Error Status 1 (SM_ECC_ST1) Register Address Description Reset Value SM_ECC_ST1 FMI_BA+0x0D4 Smart-Media ECC Error Status 1 0x0000_0000 Reserved F8_ECNT F8_STAT Reserved F7_ECNT F7_STAT Reserved F6_ECNT F6_STAT Reserved F5_ECNT F5_STAT Bits Descriptions [31] Reserved Reserved Error Count of ECC Field 8 This field contains the error counts after ECC correct calculation of Field 8.
Page 533 N9H26 Technical Reference Manual Bits Descriptions ECC Status of Field 6 This field contains the ECC correction status (BCH algorithm) of ECC-field 6. [9:8] F6_STAT 00 = No error. 01 = Correctable error. 10 = Uncorrectable error. Reserved Reserved Error Count of ECC Field 5 This field contains the error counts after ECC correct calculation of Field 5.
Page 534 N9H26 Technical Reference Manual Smart-media ECC Error Status 2 (SM_ECC_ST2) Register Address Description Reset Value SM_ECC_ST2 FMI_BA+0x0D8 Smart-Media ECC Error Status 2 0x0000_0000 Reserved F11_ECNT F11_STAT Reserved F10_ECNT F10_STAT Reserved F9_ECNT F9_STAT Reserved F8_ECNT F8_STAT Bits Descriptions [31] Reserved Reserved Error Count of ECC Field 11 This field contains the error counts after ECC correct calculation of Field 11.
Page 535 N9H26 Technical Reference Manual Bits Descriptions ECC Status of Field 9 This field contains the ECC correction status (BCH algorithm) of ECC-field 9. [9:8] F9_STAT 00 = No error. 01 = Correctable error. 10 = Uncorrectable error. Reserved Reserved Error Count of ECC Field 8 This field contains the error counts after ECC correct calculation of Field 8.
Page 536 N9H26 Technical Reference Manual Smart-media ECC Error Status 3 (SM_ECC_ST3) Register Address Description Reset Value SM_ECC_ST3 FMI_BA+0x0DC Smart-Media ECC Error Status 3 0x0000_0000 Reserved F15_ECNT F15_STAT Reserved F14_ECNT F14_STAT Reserved F13_ECNT F13_STAT Reserved F12_ECNT F12_STAT Bits Descriptions [31] Reserved Reserved Error Count of ECC Field 15 This field contains the error counts after ECC correct calculation of Field 15.
Page 537 N9H26 Technical Reference Manual Bits Descriptions ECC Status of Field 13 This field contains the ECC correction status (BCH algorithm) of ECC-field 13. [9:8] F13_STAT 00 = No error. 01 = Correctable error. 10 = Uncorrectable error. Reserved Reserved Error Count of ECC Field 12 This field contains the error counts after ECC correct calculation of Field 12.
Page 538 N9H26 Technical Reference Manual Smart-media Protect End Address Register 0 (SM_PROT_ADDR0) Register Address Description Reset Value Smart-Media Protect End Address SM_PROT_ADDR0 FMI_BA+0x0E0 0x0000_0000 Register 0 SM_PROT_ADDR0 SM_PROT_ADDR0 SM_PROT_ADDR0 SM_PROT_ADDR0 Bits Descriptions Smart-Media Protect End Address Register 0 setting register SM_PROT_ADDR0, SM_PROT_ADDR1 enable [31:0]...
Page 539 N9H26 Technical Reference Manual Smart-media Protect End Address Register 1 (SM_PROT_ADDR1) Register Address Description Reset Value Smart-Media Protect End Address SM_PROT_ADDR1 FMI_BA+0x0E4 0x0000_0000 Register 1 Reserved Reserved Reserved SM_PROT_ADDR1 Bits Descriptions Smart-Media Protect End Address Register 1 setting register SM_PROT_ADDR0, SM_PROT_ADDR1 enable [7:0]...
Page 540 N9H26 Technical Reference Manual BCH Error Address 0 (BCH_ERR_ADDR0) Register Address Description Reset Value BCH_ERR_ADDR0 FMI_BA+0x100 BCH Error Byte Address0. 0x0000_0000 Reserved E_ADDR_FF_1 E_ADDR_FF_1 Reserved E_ADDR_FF_0 E_ADDR_FF_0 Bits Descriptions [31:27] Reserved Reserved ECC Error Address First Field of Error 1 [26:16] E_ADDR_FF_1 This field contains a 11-bit ECC error address 1 of first field.
Page 541 N9H26 Technical Reference Manual BCH Error Address 1 (BCH_ERR_ADDR1) Register Address Description Reset Value BCH_ERR_ADDR1 FMI_BA+0x104 BCH Error Byte Address1. 0x0000_0000 Reserved E_ADDR_FF_3 E_ADDR_FF_3 Reserved E_ADDR_FF_2 E_ADDR_FF_2 Bits Descriptions [31:27] Reserved Reserved ECC Error Address First Field of Error 3 [26:16] E_ADDR_FF_3 This field contains a 11-bit ECC error address 3 of first field.
Page 542 N9H26 Technical Reference Manual BCH Error Address 2 (BCH_ERR_ADDR2) Register Address Description Reset Value BCH_ERR_ADDR2 FMI_BA+0x108 BCH Error Byte Address2. 0x0000_0000 Reserved E_ADDR_FF_5 E_ADDR_FF_5 Reserved E_ADDR_FF_4 E_ADDR_FF_4 Bits Descriptions [31:27] Reserved Reserved ECC Error Address First Field of Error 5 [26:16] E_ADDR_FF_5 This field contains a 11-bit ECC error address 5 of first field.
Page 543 N9H26 Technical Reference Manual BCH Error Address 3 (BCH_ERR_ADDR3) Register Address Description Reset Value BCH_ERR_ADDR3 FMI_BA+0x10C BCH Error Byte Address3. 0x0000_0000 Reserved E_ADDR_FF_7 E_ADDR_FF_7 Reserved E_ADDR_FF_6 E_ADDR_FF_6 Bits Descriptions [31:27] Reserved Reserved ECC Error Address First Field of Error 7 [26:16] E_ADDR_FF_7 This field contains a 11-bit ECC error address 7 of first field.
Page 544 N9H26 Technical Reference Manual BCH Error Address 4 (BCH_ERR_ADDR4) Register Address Description Reset Value BCH_ERR_ADDR4 FMI_BA+0x110 BCH Error Byte Address4. 0x0000_0000 Reserved E_ADDR_FF_9 E_ADDR_FF_9 Reserved E_ADDR_FF_8 E_ADDR_FF_8 Bits Descriptions [31:27] Reserved Reserved ECC Error Address First Field of Error 9 [26:16] E_ADDR_FF_9 This field contains a 11-bit ECC error address 9 of first field.
Page 545 N9H26 Technical Reference Manual BCH Error Address 5 (BCH_ERR_ADDR5) Register Address Description Reset Value BCH_ERR_ADDR5 FMI_BA+0x114 BCH Error Byte Address5. 0x0000_0000 Reserved E_ADDR_FF_11 E_ADDR_FF_11 Reserved E_ADDR_FF_10 E_ADDR_FF_10 Bits Descriptions [31:27] Reserved Reserved ECC Error Address First Field of Error 11 [26:16] E_ADDR_FF_11 This field contains a 11-bit ECC error address 11 of first field.
Page 546 N9H26 Technical Reference Manual BCH Error Address 6 (BCH_ERR_ADDR6) Register Address Description Reset Value BCH_ERR_ADDR6 FMI_BA+0x118 BCH Error Byte Address6. 0x0000_0000 Reserved E_ADDR_FF_13 E_ADDR_FF_13 Reserved E_ADDR_FF_12 E_ADDR_FF_12 Bits Descriptions [31:27] Reserved Reserved ECC Error Address First Field of Error 13 [26:16] E_ADDR_FF_13 This field contains a 11-bit ECC error address 13 of first field.
Page 547 N9H26 Technical Reference Manual BCH Error Address 7 (BCH_ERR_ADDR7) Register Address Description Reset Value BCH_ERR_ADDR7 FMI_BA+0x11C BCH Error Byte Address7. 0x0000_0000 Reserved E_ADDR_FF_15 E_ADDR_FF_15 Reserved E_ADDR_FF_14 E_ADDR_FF_14 Bits Descriptions [31:27] Reserved Reserved ECC Error Address First Field of Error 15 [26:16] E_ADDR_FF_15 This field contains a 11-bit ECC error address 15 of first field.
Page 548 N9H26 Technical Reference Manual BCH Error Address 8 (BCH_ERR_ADDR8) Register Address Description Reset Value BCH_ERR_ADDR8 FMI_BA+0x120 BCH Error Byte Address8. 0x0000_0000 Reserved E_ADDR_FF_17 E_ADDR_FF_17 Reserved E_ADDR_FF_16 E_ADDR_FF_16 Bits Descriptions [31:27] Reserved Reserved ECC Error Address First Field of Error 17 [26:16] E_ADDR_FF_17 This field contains a 11-bit ECC error address 17 of first field.
Page 549 N9H26 Technical Reference Manual BCH Error Address 9 (BCH_ERR_ADDR9) Register Address Description Reset Value BCH_ERR_ADDR9 FMI_BA+0x124 BCH Error Byte Address9. 0x0000_0000 Reserved E_ADDR_FF_19 E_ADDR_FF_19 Reserved E_ADDR_FF_18 E_ADDR_FF_18 Bits Descriptions [31:27] Reserved Reserved ECC Error Address First Field of Error 19 [26:16] E_ADDR_FF_19 This field contains a 11-bit ECC error address 19 of first field.
Page 550 N9H26 Technical Reference Manual BCH Error Address 10 (BCH_ERR_ADDR10) Register Address Description Reset Value BCH_ERR_ADDR10 FMI_BA+0x128 BCH Error Byte Address10. 0x0000_0000 Reserved E_ADDR_FF_21 E_ADDR_FF_21 Reserved E_ADDR_FF_20 E_ADDR_FF_20 Bits Descriptions [31:27] Reserved Reserved ECC Error Address First Field of Error 21 [26:16] E_ADDR_FF_21 This field contains a 11-bit ECC error address 21 of first field.
Page 551 N9H26 Technical Reference Manual Bits Descriptions [31:27] Reserved Reserved ECC Error Address First Field of Error 23 [26:16] E_ADDR_FF_23 This field contains a 11-bit ECC error address 23 of first field. If it is a correctable error, software can read the error data at BCH_ECC_DATA_FF23 for correcting this error. [15:11] Reserved Reserved...
Page 552 N9H26 Technical Reference Manual BCH ECC Error Data (BCH_ECC_DATA0) Register Address Description Reset Value BCH_ECC_DATA0 FMI_BA+0x160 BCH ECC Error Data 0 0x8080_8080 E_DATA_FF_3 E_DATA_FF_2 E_DATA_FF_1 E_DATA_FF_0 Bits Descriptions ECC Error Data Of First Field 3 This field contains an 8-bit BCH ECC error data 3 of first field. If it is a correctable error, [31:24] E_DATA_FF_3 software can read out the error data in this field and doing bitwise XOR with received...
Page 553 N9H26 Technical Reference Manual BCH ECC Error Data (BCH_ECC_DATA1) Register Address Description Reset Value BCH_ECC_DATA1 FMI_BA+0x164 BCH ECC Error Data 1 0x8080_8080 E_DATA_FF_7 E_DATA_FF_6 E_DATA_FF_5 E_DATA_FF_4 Bits Descriptions ECC Error Data Of First Field 7 This field contains an 8-bit BCH ECC error data 7 of first field. If it is a correctable error, [31:24] E_DATA_FF_7 software can read out the error data in this field and doing bitwise XOR with received...
Page 554 N9H26 Technical Reference Manual BCH ECC Error Data (BCH_ECC_DATA2) Register Address Description Reset Value BCH_ECC_DATA2 FMI_BA+0x168 BCH ECC Error Data 2 0x8080_8080 E_DATA_FF_11 E_DATA_FF_10 E_DATA_FF_9 E_DATA_FF_8 Bits Descriptions ECC Error Data Of First Field 11 This field contains an 8-bit BCH ECC error data 11 of first field. If it is a correctable [31:24] E_DATA_FF_11 error, software can read out the error data in this field and doing bitwise XOR with...
Page 555 N9H26 Technical Reference Manual BCH ECC Error Data (BCH_ECC_DATA3) Register Address Description Reset Value BCH_ECC_DATA3 FMI_BA+0x16C BCH ECC Error Data 3 0x8080_8080 E_DATA_FF_15 E_DATA_FF_14 E_DATA_FF_13 E_DATA_FF_12 Bits Descriptions ECC Error Data Of First Field 15 This field contains an 8-bit BCH ECC error data 15 of first field. If it is a correctable [31:24] E_DATA_FF_15 error, software can read out the error data in this field and doing bitwise XOR with...
Page 556 N9H26 Technical Reference Manual BCH ECC Error Data (BCH_ECC_DATA4) Register Address Description Reset Value BCH_ECC_DATA4 FMI_BA+0x170 BCH ECC Error Data 4 0x8080_8080 E_DATA_FF_19 E_DATA_FF_18 E_DATA_FF_17 E_DATA_FF_16 Bits Descriptions ECC Error Data Of First Field 19 This field contains an 8-bit BCH ECC error data 19 of first field. If it is a correctable [31:24] E_DATA_FF_19 error, software can read out the error data in this field and doing bitwise XOR with...
Page 557 N9H26 Technical Reference Manual BCH ECC Error Data (BCH_ECC_DATA5) Register Address Description Reset Value BCH_ECC_DATA5 FMI_BA+0x174 BCH ECC Error Data 5 0x8080_8080 E_DATA_FF_23 E_DATA_FF_22 E_DATA_FF_21 E_DATA_FF_20 Bits Descriptions ECC Error Data Of First Field 23 This field contains an 8-bit BCH ECC error data 23 of first field. If it is a correctable [31:24] E_DATA_FF_23 error, software can read out the error data in this field and doing bitwise XOR with...
Page 558 N9H26 Technical Reference Manual Smart-media Redundant Area Register (SMRA) Register Address Description Reset Value SM_RA0 FMI_BA+0x200 … … Smart-Media Redundant Area Register SM_RA117 FMI_BA+0x3D4 SM_RA SM_RA SM_RA SM_RA Bits Descriptions Smart-Media Redundant Area [31:0] SM_RA This field is parity data buffer. Note: The SRMA reset value is undefined.
Page 559: Usb 2.0 Device Controller
N9H26 Technical Reference Manual 5.13 USB 2.0 Device Controller 5.13.1 Overview The USB device controller interfaces the AHB bus and the UTMI bus. The USB controller contains both the AHB master interface and AHB slave interface. CPU programs the USB controller registers through the AHB slave interface.
Page 560: Internal Block Diagram
N9H26 Technical Reference Manual 5.13.3 Internal Block Diagram 5.13.4 USB Device Register Group Summary Register Groups Description These set of registers control the global enable of interrupts and Main Control Registers maintain the status of the interrupts These set of registers control the USB related events to/from the USB Control Registers USB host and hold the status of the USB events.
Page 561: Usb Device Control Registers Map
N9H26 Technical Reference Manual 5.13.5 USB Device Control Registers Map Register Address Description Reset Value USBD_BA = B100_8000 USBD_BA+0x00 Interrupt Register 0x0000_0000 Reserved USBD_BA+0x04 IRQ_ENB_L USBD_BA+0x08 Interrupt Enable Low Register 0x0000_0001 Reserved USBD_BA+0x0C USB_IRQ_STAT USBD_BA+0x10 USB Interrupt Status register 0x0000_0000 USB_IRQ_ENB USBD_BA+0x14 USB Interrupt Enable register...
Page 562 N9H26 Technical Reference Manual Register Address Description Reset Value EPA_CNT USBD_BA+0x7C Endpoint Atransfer count register 0x0000_0000 EPA_CFG USBD_BA+0x80 Endpoint Aconfiguration register 0x0000_0012 EndpointA’s RAM start address EPA_START_ADDR USBD_BA+0x84 0x0000_0000 EndpointA’s RAM end address EPA_END_ADDR USBD_BA+0x88 0x0000_0000 EPB_DATA_BUF USBD_BA+0x8C EndpointB data register 0x0000_0000 EPB_IRQ_STAT USBD_BA+0x90...
Page 563 N9H26 Technical Reference Manual Register Address Description Reset Value EndpointD’s RAM end address EPD_END_ADDR USBD_BA+0x100 0x0000_0000 USB MEM TEST USBD_BA+0x154 USB memory test 0x0000_0000 USB HEAD WORD0 USBD_BA+0x158 USB header word0 0x0000_0000 USB HEAD WORD1 USBD_BA+0x15C USB header word1 0x0000_0000 USB HEAD WORD2 USBD_BA+0x160 USB header word2...
Page 564: Usb Device Control Registers
N9H26 Technical Reference Manual 5.13.6 USB Device Control Registers Publication Release Date: Sept. 10, 2018 - 564 - Revision V1.01...
Page 565 N9H26 Technical Reference Manual Interrupt Register (IRQ) Register Address Description Default Value USBD_BA+0x000 Interrupt Register 0x0000_0000 Reserved Reserved Reserved Reserved EPD_INT EPC_INT EPB_INT EPA_INT CEP_INT USB_INT Bits Descriptions [31:6] Reserved This bit conveys the interrupt for Endpoints D. EPD_INT When set, the corresponding Endpoint D’s interrupt status register should be read to determine the cause of the interrupt.
Page 566 N9H26 Technical Reference Manual Interrupt Enable Low Register (IRQ_ENB_L) Register Address Description Default Value IRQ_ENB_L USBD_BA+0x008 Interrupt Enable Low Register 0x0000_0001 Reserved Reserved Reserved Reserved EPD_IE EPC_IE EPB_IE EPA_IE CEP_IE USB_IE Bits Descriptions [31:6] Reserved Interrupt Enable for Endpoint D. EPD_IE When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint D...
Page 567 N9H26 Technical Reference Manual USB Interrupt Status Register (USB_IRQ_STAT) Register Address Description Default Value USB_IRQ_STAT USBD_BA+0x010 USB Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved VBUS_IS Reserved TCLKOK_IS DMACOM_IS HISPD_IS SUS_IS RUM_IS RST_IS SOF_IS Bits Descriptions [31:9] Reserved VBUS Interrupt VBUS_IS This bit is set when the Vbus is attached/de-attached.
Page 568 N9H26 Technical Reference Manual USB Interrupt Enable Register (USB_IRQ_ENB) Register Address Description Default Value USB_IRQ_ENB USBD_BA+0x014 USB Interrupt Enable Register 0x0000_0040 Reserved Reserved Reserved VBUS_IE Reserved TCLKOK_IE DMACOM_IE HISPD_IE SUS_IE RUM_IE RST_IE SOF_IE Bits Descriptions [31:9] Reserved VBUS Detected Interrupt Enable. VBUS_IE This bit enables the Vbus detected interrupt.
Page 569 N9H26 Technical Reference Manual USB Operational Register (USB_OPER) Register Address Description Default Value USB_OPER USBD_BA+0x018 Usb Operational Register 0x0000_0002 Reserved Reserved Reserved Reserved CUR_SPD SET_HISPD GEN_RUM Bits Descriptions [31:3] Reserved USB Current Speed. CUR_SPD When set, this bit indicates that the DEVICE CONTROLLER has settled in High Speed and a zero indicates that the device has settled in Full Speed.(READ ONLY) USB High Speed.
Page 570: Frame Counter
N9H26 Technical Reference Manual USB Frame Count Register (USB_FRAME_CNT) Register Address Description Default Value USB_FRAME_CNT USBD_BA+0x01C USB Frame Count Register 0x0000_0000 Reserved Reserved Reserved FRAME_CNT FRAME_CNT MFRAME_CNT Bits Descriptions [31:14] Reserved FRAME COUNTER. [13:3] FRAME_CNT This field contains the frame count from the most recent start-of-frame packet. MICRO FRAME COUNTER.
Page 571 N9H26 Technical Reference Manual USB Address Register (USB_ADDR) Register Address Description Default Value USB_ADDR USBD_BA+0x020 USB Address Register 0x0000_0000 Reserved Reserved Reserved Reserved ADDR Bits Descriptions [31:7] Reserved This field contains the current USB address of the device. This field is cleared when a root port [6:0] ADDR reset is detected.
Page 572: Test Mode
N9H26 Technical Reference Manual USB Test Mode Register (USB_TEST) Register Address Description Default Value USB_TEST USBD_BA+0x024 USB Test Mode Register 0x0000_0000 Reserved Reserved Reserved Reserved TESTMODE Bits Descriptions [31:3] Reserved Test Mode Select. Value Test Normal Operation Test_J Test_K [2:0] TESTMODE Test_SE0_NAK Test_Packet...
Page 573 N9H26 Technical Reference Manual Control-ep Data Buffer (CEP_DATA_BUF) Register Register Address Description Default Value CEP_DATA_BUF USBD_BA+0x028 Control-ep Data Buffer 0x0000_0000 DATA_BUF DATA_BUF DATA_BUF DATA_BUF Bits Descriptions Control-ep Data Buffer. [31:0] DATA_BUF the data port for the buffer transaction (read from ram buffer). Publication Release Date: Sept.
Page 574 N9H26 Technical Reference Manual Control-ep Control and Status (CEP_CTRL_STAT) Register Register Address Description Default Value CEP_CTRL_STAT USBD_BA+0x02C Control-ep Control and Status 0x0000_0000 Reserved Reserved Reserved Reserved FLUSH ZEROLEN STLALL NAK_CLEAR Bits Descriptions [31:4] Reserved CEP-FLUSH Bit. FLUSH Writing 1 to this bit cause the packet buffer and its corresponding CEP_AVL_CNT register to be cleared.
Page 575 N9H26 Technical Reference Manual Control Endpoint Interrupt Enable (CEP_IRQ_ENB) Register Register Address Description Default Value CEP_IRQ_ENB USBD_BA+0x030 Control Endpoint Interrupt Enable 0x0000_0000 Reserved Reserved Reserved Reversed EMPTY_IE FULL_IE STACOM_IE ERR_IE STALL_IE NAK_IE DATA_RxED_I DATA_TxED_I PING_IE IN_TK_IE OUT_TK_IE SETUP_PK_IE SETUP_TK_IE Bits Descriptions [31:14] Reserved...
Page 576 N9H26 Technical Reference Manual Bits Descriptions Out Token Interrupt. OUT_TK_IE This bit enables the out token interrupt. Setup Packet Interrupt. SETUP_PK_IE This bit enables the setup packet interrupt. Setup Token Interrupt Enable. SETUP_TK_IE This bit enables the setup token interrupt. Publication Release Date: Sept.
Page 577 N9H26 Technical Reference Manual Control-ep Interrupt Status (CEP_IRQ_STAT) Register Register Address Description Default Value CEP_IRQ_STAT USBD_BA+0x034 Control-ep Interrupt Status 0x0000_0000 Reserved Reserved Reserved Reversed EMPTY_IS FULL_IS STACOM_IS ERR_IS STALL_IS NAK_IS DATA_RxED_I DATA_TxED_I PING_IS IN_TK_IS OUT_TK_IS SETUP_PK_IS SETUP_TK_IS Bits Descriptions [31:14] Reversed [13] Reversed...
Page 578 N9H26 Technical Reference Manual Bits Descriptions In Token Interrupt. IN_TK_IS This bit is set when the controlendpt receives an in token from the host. Write “1” clear. Out Token Interrupt. OUT_TK_IS This bit is set when the control-endpoint receives a out token from the host. Write “1” clear.
Page 579 N9H26 Technical Reference Manual In-transfer Data Count (IN_TRF_CNT) Register Register Address Description Default Value IN_TRF_CNT USBD_BA+0x038 In-transfer data count 0x0000_0000 Reserved Reserved Reserved IN_TRF_CNT Bits Descriptions [31:8] Reserved In-transfer data count. There is no mode selection for the control endpoint (but it operates like manual mode).The local-CPU has to fill the control-endpoint buffer with the data to be sent for an [7:0] IN_TRF_CNT...
Page 580 N9H26 Technical Reference Manual Out-transfer Data Count (OUT_TRF_CNT) Register Register Address Description Default Value OUT_TRF_CNT USBD_BA+0x03C Out-transfer data count 0x0000_0000 Reserved Reserved Reserved OUT_TRF_CNT Bits Descriptions [31:8] Reserved Out-Transfer Data Count. [7:0] OUT_TRF_CNT The DEVICE CONTROLLER maintains the count of the data received in case of an out transfer, during the control transfer.
Page 581 N9H26 Technical Reference Manual Control-ep Data Count (CEP_CNT) Register Register Address Description Default Value CEP_CNT USBD_BA+0x040 Control-ep data count 0x0000_0000 Reserved Reserved CEP_CNT CEP_CNT Bits Descriptions [31:16] Reserved Control-ep Data Count. [15:0] CEP_CNT The DEVICE CONTROLLER maintains the count of the data of control-ep. Publication Release Date: Sept.
Page 582 N9H26 Technical Reference Manual Setup1 & Setup0 Bytes (SETUP1_0) Register Register Address Description Default Value SETUP1_0 USBD_BA+0x044 Setup1 & Setup0 bytes 0x0000_0000 Reserved Reserved SETUP1 SETUP0 Bits Descriptions [31:16] Reserved Setup Byte 1[15:8]. This register provides byte 1 of the last setup packet received. For a Standard Device Request, the following bRequest Code information is returned.
Page 583 N9H26 Technical Reference Manual Bits Descriptions Bits Descriptions Direction 0 = host to device; 1 = device to host [6:5] Type 0 = Standard, 1 = Class, 2 = Vendor, 3 = Reserved [4:0] Recipient 0 = Device, 1 = Interface, 2 = Endpoint, 3 = Other, 4-31 Reserved...
Page 584 N9H26 Technical Reference Manual Setup3 & Setup2 Bytes (SETUP3_2) Register Register Address Description Default Value SETUP3_2 USBD_BA+0x048 Setup3 & Setup2 bytes 0x0000_0000 Reserved Reserved SETUP3 SETUP2 Bits Descriptions [31:16] Reserved Setup Byte 3 [15:8]. [15:8] SETUP3 This register provides byte 3 of the last setup packet received. For a Standard Device Request, the most significant byte of the wValue field is returned.
Page 585 N9H26 Technical Reference Manual Setup5 & Setup4 Bytes (SETUP5_4) Register Register Address Description Default Value SETUP5_4 USBD_BA+0x04C Setup5 & Setup4 bytes 0x0000_0000 Reserved Reserved SETUP5 SETUP4 Bits Descriptions [31:16] Reserved Setup Byte 5[15:8]. [15:8] SETUP5 This register provides byte 5 of the last setup packet received. For a Standard Device Request, the most significant byte of the wIndex field is returned.
Page 586 N9H26 Technical Reference Manual Setup7 & Setup6 Bytes (SETUP7_6) Register Register Address Description Default Value SETUP7_6 USBD_BA+0x050 Setup7 & Setup6 bytes 0x0000_0000 Reserved Reserved SETUP7 SETUP6 Bits Descriptions [31:16] Reserved Setup Byte 7[15:8]. [15:8] SETUP7 This register provides byte 7 of the last setup packet received. For a Standard Device Request, the most significant byte of the wLength field is returned.
Page 587 N9H26 Technical Reference Manual Control Ep RAM Start Addr Register (CEP_START_ADDR) Register Address Description Default Value Control Ep RAM Start Address CEP_START_ADDR USBD_BA+0x054 0x0000_0000 Register Reserved Reserved Reserved CEP_START_ADDR CEP_START_ADDR Bits Descriptions [31:12] Reserved This is the start-address of the RAM space allocated for the control-endpoint [11:0] CEP_START_ADDR Publication Release Date: Sept.
Page 588 N9H26 Technical Reference Manual Control Ep RAM End Addr Register (CEP_END_ADDR) Register Address Description Default Value CEP_END_ADDR USBD_BA+0x058 Control Ep RAM End Address Register 0x0000_0000 Reserved Reserved Reserved CEP_END_ADDR CEP_END_ADDR Bits Descriptions [31:12] Reserved [11:0] CEP_END_ADDR This is the end-address of the RAM space allocated for the control-endpoint Publication Release Date: Sept.
Page 589 N9H26 Technical Reference Manual DMA Control Status Register (DMA_CTRL_STS) Register Address Description Default Value DMA_CTRL_STS USBD_BA+0x05C DMA Control Status Register 0x0000_0000 Reserved Reserved Reserved RST_DMA SCAT_GA_EN DMA_EN DMA_RD DMA_ADDR Bits Descriptions [31:8] Reserved RST_DMA Reset DMA state machine. SCAT_GA_EN Scatter gather function enable DMA_EN DMA Enable Bit DMA Operation Bit.
Page 590 N9H26 Technical Reference Manual DMA Count Register (DMA_CNT) Register Address Description Default Value DMA_CNT USBD_BA+0x60 DMA Count Register 0x0000_0000 Reserved Reserved DMA_CNT DMA_CNT DMA_CNT Bits Descriptions [31:20] Reserved [19:0] The transfer count of the DMA operation to be performed is written to this register. DMA_CNT Publication Release Date: Sept.
Page 591 N9H26 Technical Reference Manual Endpoint A~D Data Register (EPA_DATA_BUF~ EPC_DATA_BUF) Register Address Description Default Value EPA_DATA_BUF USBD_BA+0x064 Endpoint A Data Register 0x0000_0000 EPB_DATA_BUF USBD_BA+0x08C Endpoint B Data Register 0x0000_0000 EPC_DATA_BUF USBD_BA+0x0B4 Endpoint C Data Register 0x0000_0000 EPD_DATA_BUF USBD_BA+0x0DC Endpoint D Data Register 0x0000_0000 EP_DATA_BUF EP_DATA_BUF...
Page 592 N9H26 Technical Reference Manual Endpoint A~D Interrupt Status Register (EPA_IRQ_STAT~ EPC_IRQ_STAT) Register Address Description Default Value EPA_IRQ_STAT USBD_BA+0x068 Endpoint A Interrupt Status Register 0x0000_0000 EPB_IRQ_STAT USBD_BA+0x090 Endpoint B Interrupt Status Register 0x0000_0000 EPC_IRQ_STAT USBD_BA+0x0B8 Endpoint C Interrupt Status Register 0x0000_0000 EPD_IRQ_STAT USBD_BA+0x0E0 Endpoint D Interrupt Status Register...
Page 593 N9H26 Technical Reference Manual Bits Descriptions Data OUT Token Interrupt. OUT_TK_IS This bit is set when a Data OUT token has been received from the host. This bit also set by PING tokens (in high-speed only). Writing a ‘1’ clears this bit. Data Packet Received Interrupt.
Page 594 N9H26 Technical Reference Manual Endpoint A~D Interrupt Enable Register (EPA_IRQ_ENB~ EPC_IRQ_ENB) Register Address Description Default Value EPA_IRQ_ENB USBD_BA+0x06C Endpoint A Interrupt Enable Register 0x0000_0000 EPB_IRQ_ENB USBD_BA+0x094 Endpoint B Interrupt Enable Register 0x0000_0000 EPC_IRQ_ENB USBD_BA+0x0BC Endpoint C Interrupt Enable Register 0x0000_0000 EPD_IRQ_ENB USBD_BA+0x0E4 Endpoint D Interrupt Enable Register...
Page 595 N9H26 Technical Reference Manual Bits Descriptions Data OUT Token Interrupt Enable. OUT_TK_IE When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host. Data Packet Received Interrupt Enable. DATA_RxED_IE When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
Page 596 N9H26 Technical Reference Manual Endpoint A~D Data Available Count Register (EPA_DATA_CNT~ EPC_DATA_CNT) Register Address Description Default Value EPA_DATA_CNT USBD_BA+0x070 Endpoint A Data Available count register 0x0000_0000 EPB_DATA_CNT USBD_BA+0x098 Endpoint B Data Available count register 0x0000_0000 EPC_DATA_CNT USBD_BA+0x0C0 Endpoint C Data Available count register 0x0000_0000 EPD_DATA_CNT USBD_BA+0x0E8 Endpoint D Data Available count register 0x0000_0000...
Page 597 N9H26 Technical Reference Manual Endpoint A~D Response Set/Clear Register (EPA_RSP_SC~ EPC_RSP_SC) Register Address Description Default Value EPA_RSP_SC USBD_BA+0x074 Endpoint A Response Set/Clear Register 0x0000_0000 EPB_RSP_SC USBD_BA+0x09C Endpoint B Response Set/Clear Register 0x0000_0000 EPC_RSP_SC USBD_BA+0x0C4 Endpoint C Response Set/Clear Register 0x0000_0000 EPD_RSP_SC USBD_BA+0x0EC Endpoint D Response Set/Clear Register...
Page 598 N9H26 Technical Reference Manual Bits Descriptions MODE[2:1] Mode Description 2’b00 Auto-Validate Mode 2’b01 Manual-Validate Mode 2’b10 Fly Mode 2’b11 Reserved. These bits are not valid for an out-endpoint.The auto validate mode will be activated when the reserved mode is selected. (These modes are explained detailed in later sections) If the endpoint is selected to be operating in auto-validation mode, the endpointresponds only with data payloads to be equal to EP_MPS register.
Page 599 N9H26 Technical Reference Manual Endpoint A~D Maximum Packet Size Register (EPA_MPS~ EPC_MPS) Register Address Description Default Value EPA_MPS USBD_BA+0x078 Endpoint A Maximum Packet Size Register 0x0000_0000 EPB_MPS USBD_BA+0x0A0 Endpoint B Maximum Packet Size Register 0x0000_0000 EPC_MPS USBD_BA+0x0C8 Endpoint C Maximum Packet Size Register 0x0000_0000 EPD_MPS USBD_BA+0x0F0...
Page 600 N9H26 Technical Reference Manual Endpoint A~D Transfer Count Register (EPA_TRF_CNT~ EPC_TRF_CNT) Register Address Description Default Value EPA_TRF_CNT USBD_BA+0x07C Endpoint A Transfer Count Register 0x0000_0000 EPB_TRF_CNT USBD_BA+0x0A4 Endpoint B Transfer Count Register 0x0000_0000 EPC_TRF_CNT USBD_BA+0x0CC Endpoint C Transfer Count Register 0x0000_0000 EPD_TRF_CNT USBD_BA+0x0F4 Endpoint D Transfer Count Register...
Page 601 N9H26 Technical Reference Manual Endpoint A~D Configuration Register (EPA_CFG~ EPC_CFG) Register Address Description Default Value EPA_CFG USBD_BA+0x080 Endpoint A Configuration Register 0x0000_0012 EPB_CFG USBD_BA+0x0A8 Endpoint B Configuration Register 0x0000_0022 EPC_CFG USBD_BA+0x0D0 Endpoint C Configuration Register 0x0000_0032 EPD_CFG USBD_BA+0x0F8 Endpoint D Configuration Register 0x0000_0042 Reserved Reserved...
Page 602 N9H26 Technical Reference Manual Bits Descriptions 0x10 Interrupt 0x11 Isochronous Endpoint Valid. EP_VALID When set, this bit enables this endpoint. This bit has no effect on Endpoint 0, which is always enabled. Publication Release Date: Sept. 10, 2018 - 602 - Revision V1.01...
Page 603 N9H26 Technical Reference Manual Endpoint A~D RAM Start Address Register (EPA_START_ADDR~ EPC_START_ADDR) Register Address Description Default Value Endpoint A RAM Start Address EPA_START_ADDR USBD_BA+0x084 0x0000_0000 Register Endpoint B RAM Start Address EPB_START_ADDR USBD_BA+0x0AC 0x0000_0000 Register Endpoint C RAM Start Address EPC_START_ADDR USBD_BA+0x0D4 0x0000_0000...
Page 604 N9H26 Technical Reference Manual Endpoint A~D RAM End Address Register (EPA_END_ADDR~ EPC_END_ADDR) Register Address Description Default Value Endpoint A RAM End Address EPA_END_ADDR USBD_BA+0x088 0x0000_0000 Register Endpoint B RAM End Address EPB_END_ADDR USBD_BA+0x0B0 0x0000_0000 Register Endpoint C RAM End Address EPC_END_ADDR USBD_BA+0x0D8 0x0000_0000...
Page 605 N9H26 Technical Reference Manual USB Memory Test (USB_MEM_TEST) Register Address Description Default Value USB_MEM_TEST USBD_BA+0x154 USB memory test register 0x0000_0000 Reserved Reserved Reserved Reserved Reserved FAIL_A FINISH_A ERR_A MODE_A Bits Descriptions [31:4] Reversed FAIL_A Bist result of internal RAM FINISH_A Bist finish for internal RAM ERR_A Bist error map for internal RAM...
Page 606 N9H26 Technical Reference Manual USB Head Word0 (USB_HEAD0) Register Address Description Default Value USB_head word0 USBD_BA+0x158 USB head word0 0x0000_0000 HEAD_WORD0 HEAD_WORD0 HEAD_WORD0 HEAD_WORD0 Bits Descriptions [31:0] HRAD WORD0 The first head data(byte 0 was sent first) Publication Release Date: Sept. 10, 2018 - 606 - Revision V1.01...
Page 607 N9H26 Technical Reference Manual USB Head Word1 (USB_HEAD1) Register Address Description Default Value USB_head word1 USBD_BA+0x15C USB head word1 0x0000_0000 HEAD_WORD1 HEAD_WORD1 HEAD_WORD1 HEAD_WORD1 Bits Descriptions [31:0] HRAD WORD1 The second head data(byte 0 was sent first) Publication Release Date: Sept. 10, 2018 - 607 - Revision V1.01...
Page 608 N9H26 Technical Reference Manual USB Head Word2 (USB_HEAD2) Register Address Description Default Value USB_head word2 USBD_BA+0x160 USB head word2 0x0000_0000 HEAD_WORD2 HEAD_WORD2 HEAD_WORD2 HEAD_WORD2 Bits Descriptions [31:0] HRAD WORD2 The third head data(byte 0 was sent first) Publication Release Date: Sept. 10, 2018 - 608 - Revision V1.01...
Page 609 N9H26 Technical Reference Manual Endpoint A~D RAM End Address Register (EPA_END_ADDR~ EPC_END_ADDR) Register Address Description Default Value EPA_HEAD_CNT USBD_BA+0x164 Endpoint A header count 0x0000_0000 EPB_HEAD_CNT USBD_BA+0x168 Endpoint B header count 0x0000_0000 EPC_HEAD_CNT USBD_BA+0x16C Endpoint C header count 0x0000_0000 EPD_HEAD_CNT USBD_BA+0x170 Endpoint D header count 0x0000_0000 Reserved...
Page 610 N9H26 Technical Reference Manual AHB Address Register (AHB_DMA_ADDR) Register Address Description Default Value AHB_DMA_ADDR USBD_BA+0x700 AHB address register 0x0000_0000 AHB_DMA_ADDR AHB_DMA_ADDR AHB_DMA_ADDR AHB_DMA_ADDR Bits Descriptions It specifies the address from which the DMA has to read / write. The address must [31:0] AHB_DMA_ADDR WORD (32- bits) aligned.
Page 611 N9H26 Technical Reference Manual USB PHY Control (USB_PHY_CTL) Register Address Description Default Value USB_PHY_CTL USBD_BA+0x704 USB PHY control register 0x0000_0420 Vbus_status Rserved Reserved Reserved Rserved Phy_suspend vbus_detect Reserved bisten Bits Descriptions Vbus status 1: Vbus on [31] Vbus_status 0: Vbus off It is read only [30:24] Reserved...
Page 612: Usb Host Controller (Usbh)
N9H26 Technical Reference Manual 5.14 USB Host Controller (USBH) 5.14.1 Overview The Universal Serial Bus (USB) is a fast, bi-directional, isochronous, low-cost, dynamically attachable serial interface standard intended for modem, scanners, PDAs, keyboards, mice, and digital imaging devices. The USB is a 4-wire serial cable bus that supports serial data exchange between a Host Controller and a network of peripheral devices.
Page 613: Block Diagram
N9H26 Technical Reference Manual 5.14.3 Block Diagram AHB4 (System Memory Access) AHB2 (Register Access) USB 2.0 Host controller USB 1.1 Host Controller EHCI Host Controller (OHCI) Port 1 Port 1 Port Routing Logic Port 1 USB Bus Publication Release Date: Sept. 10, 2018 - 613 - Revision V1.01...
Page 614: Functional Descriptions
N9H26 Technical Reference Manual 5.14.4 Functional Descriptions 5.14.4.1 EHCI Controller The EHCI is interfaced with the system through AHB interface. Whenever the CPU wants to initiate a register read or register write, it uses the AHB slave I/F signals and performs the necessary operation (register read writes).
Page 615 N9H26 Technical Reference Manual 4. Generate SOF token requests to the SIE. Interrupt Processing Interrupts are the communication method for HC-initiated communication with the Host Controller Driver. There are several events that may trigger an interrupt from the Host Controller. Each specific event sets a specific bit in the HcInterruptStatus register.
Page 616: Register Map
N9H26 Technical Reference Manual 5.14.5 Register Map Register Offset Description Reset Value Capability Registers (EHCI_BA = 0xB100_B000) EHCVNR EHCI_BA+0x000 EHCI Version Number Register 0x0095_0020 EHCSPR EHCI_BA+0x004 EHCI Structural Parameters Register 0x0000_0011 EHCCPR EHCI_BA+0x008 EHCI Capability Parameters Register 0x0000_0000 EHCI_BA+0x00C … Reserved Undefined EHCI_BA+0x01C...
Page 617 N9H26 Technical Reference Manual Register Offset Description Reset Value HcIntSts OHCI_BA+0x80C Host Controller Interrupt Status Register 0x0000_0000 HcIntEn OHCI_BA+0x810 Host Controller Interrupt Enable Register 0x0000_0000 HcIntDis OHCI_BA+0x814 Host Controller Interrupt Disable Register 0x0000_0000 Host Controller Communication Area HcHCCA OHCI_BA+0x818 0x0000_0000 Register Host Controller Period Current ED HcPerCED...
Page 618: Register Description
N9H26 Technical Reference Manual 5.14.6 Register Description EHCI Version Number Register Register Address Description Reset Value EHCVNR EHCI_BA+0x00 EHCI Version Number Register 0x0095_0020 Version Version Reserved CR_Length Bits Descriptions Host Controller Interface Version Number This is a two-byte register containing a BCD encoding of the EHCI revision number [31:16] Version supported by this host controller.
Page 619 N9H26 Technical Reference Manual EHCI Structural Parameters Register Register Address Description Reset Value EHCSPR EHCI_BA+0x04 EHCI Structural Parameters Register 0x0000_0011 Reserved Reserved N_CC N_PCC Reserved N_PORTS Bits Descriptions [31:16] Reserved Number of Companion Controller This field indicates the number of companion controllers associated with this USB 2.0 host controller.
Page 620 N9H26 Technical Reference Manual Bits Descriptions A zero in this field is undefined. Publication Release Date: Sept. 10, 2018 - 620 - Revision V1.01...
Page 621 N9H26 Technical Reference Manual EHCI Capability Parameters Register Register Address Description Reset Value EHCCPR EHCI_BA+0x08 EHCI Capability Parameters Register 0x0000_0000 Reserved Reserved EECP ISO_SCH_TH Reserved ASPC PFList Bits Descriptions [31:16] Reserved EHCI Extended Capabilities Pointer (EECP) [15:8] EECP 8’h0: No extended capabilities are implemented. Isochronous Scheduling Threshold 1’b0: The value of the least significant 3 bits indicates the number of micro-frames a host [7:4]...
Page 622 N9H26 Technical Reference Manual USB Command Register Register Address Description Reset Value UCMDR EHCI_BA+0x20 USB Command Register 0x0008_0000 Reserved INT_TH_CTL Reserved Reserved AsynADB ASEN PSEN FLSize HCRESET RunStop Bits Descriptions [31:24] Reserved Interrupt Threshold Control (R/W) This field is used by system software to select the maximum rate at which the host controller will issue interrupts.
Page 623 N9H26 Technical Reference Manual Bits Descriptions Doing so will yield undefined results. Asynchronous Schedule Enable (R/W) This bit controls whether the host controller skips processing the Asynchronous Sched- ule. Values mean: ASEN 0b Do not process the Asynchronous Schedule 1b Use the ASYNCLISTADDR register to access the Asynchro-nous Schedule Periodic Schedule Enable (R/W) This bit controls whether the host controller skips processing the Periodic Schedule.
Page 624 N9H26 Technical Reference Manual USB Status Register Register Address Description Reset Value USTSR EHCI_BA+0x24 USB Status Register 0x0000_1000 Reserved Reserved ASSTS PSSTS RECLA HCHalted Reserved Reserved IntAsynA HSERR FLROVER PortCHG UERRINT USBINT Bits Descriptions [31:16] Reserved Asynchronous Schedule Status (RO) The bit reports the current real status of the Asynchronous Schedule.
Page 625 N9H26 Technical Reference Manual Bits Descriptions Host System Error (R/WC) HSERR The Host Controller sets this bit to 1 when a serious error occurs during a host system access involving the Host Controller module. Frame List Rollover (R/WC) The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero.
Page 626 N9H26 Technical Reference Manual USB Interrupt Enable Register Register Address Description Reset Value UIENR EHCI_BA+0x28 USB Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved AsynAEN HSERREN FLREN PCHGEN UERREN USBIEN Bits Descriptions [31:6] Reserved Interrupt on Async Advance Enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a AsynAEN one, the host controller will issue an interrupt at the next interrupt threshold.
Page 627 N9H26 Technical Reference Manual USB Frame Index Register Register Address Description Reset Value UFINDR EHCI_BA+0x2C USB Frame Index Register 0x0000_0000 Reserved Reserved Reserved FrameIND FrameIND Bits Descriptions [31:14] Reserved Frame Index The value in this register increment at the end of each time frame (e.g. micro-frame). Bits [N:3] are used for the Frame List current index.
Page 628 N9H26 Technical Reference Manual USB Periodic Frame List Base Address Register Register Address Description Reset Value UPFLBAR EHCI_BA+0x34 USB Periodic Frame List Base Address Register 0x0000_0000 BADDR BADDR BADDR Reserved Reserved Bits Descriptions Base Address (Low) [31:12] BADDR These bits correspond to memory address signals [31:12], respectively. [11:0] Reserved Reserved...
Page 629 N9H26 Technical Reference Manual USB Current Asynchronous List Address Register Register Address Description Reset Value UCALAR EHCI_BA+0x38 USB Current Asynchronous List Address Register 0x0000_0000 Reserved Bits Descriptions Link Pointer Low (LPL) [31:5] These bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head (QH).
Page 630 N9H26 Technical Reference Manual USB Asynchronous Schedule Sleep Timer Register Register Address Description Reset Value UASSTR EHCI_BA+0x3C USB Asynchronous Schedule Sleep Timer Register 0x0000_0000 Reserved Reserved Reserved ASTMR ASTMR Bits Descriptions [31:11] Reserved Asynchronous Schedule Sleep Timer This field defines the AsyncSchedSleepTime of EHCI spec. The asynchronous schedule sleep timer is used to control how often the host controller [11:0] ASSTMR...
Page 631 N9H26 Technical Reference Manual USB Configure Flag Register Register Address Description Reset Value UCFGR EHCI_BA+0x60 USB Configure Flag Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Descriptions [31:1] Reserved Configure Flag (CF) Host software sets this bit as the last action in its process of configuring the Host Controller.
Page 632 N9H26 Technical Reference Manual USB Port 0 Status and Control Register Register Address Description Reset Value UPSCR0 EHCI_BA+0x64 USB Port 0 Status and Control Register 0x0000_2000 Reserved Reserved PTstCtrl Reserved LStatus Reserved PRST Suspend FPResum OCCHG OCACT PENCHG CSCHG CSTS Bits Descriptions [31:20]...
Page 633 N9H26 Technical Reference Manual Bits Descriptions Line Status (RO) These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines. These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence.
Page 634 N9H26 Technical Reference Manual Bits Descriptions This field is zero if Port Power is zero. Force Port Resume (R/W) 1= Resume detected/driven on port. 0=No resume (Kstate) detected/driven on port. Default = 0. This functionality defined for manipulating this bit depends on the value of the Suspend bit.
Page 635 N9H26 Technical Reference Manual Bits Descriptions This field is zero if Port Power is zero. Current Connect Status (RO) 1=Device is present on port. 0=No device is present. Default = 0. This value reflects the CSTS current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set.
Page 636 N9H26 Technical Reference Manual USB PHY 0 Control Register (USBPCR0) Register Address Description Reset Value USBPCR0 EHCI_BA+0xC4 USB PHY 0 Control Register 0x0000_0060 Reserved Reserved Reserved ClkValid NegTX NegRX Suspend Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bits Descriptions [31:12] Reserved UTMI Clock Valid...
Page 637 N9H26 Technical Reference Manual Publication Release Date: Sept. 10, 2018 - 637 - Revision V1.01...
Page 638 N9H26 Technical Reference Manual Host Controller Revision Register (HcRev) Register Address Description Reset Value HcRev OHCI_BA+0x800 Host Controller Revision Register 0x0000_0110 Reserved Reserved Reserved Bits Descriptions [31:8] Reserved Revision Indicates the Open HCI Specification revision number implemented by the Hardware. [7:0] Host Controller supports 1.0 specification.
Page 639 N9H26 Technical Reference Manual Host Controller Control Register (HcControl) Register Address Description Reset Value HcControl OHCI_BA+0x804 Host Controller Control Register 0x0000_0000 Reserved Reserved Reserved RWakeEn RWake IntRoute HcFunc BlkEn CtrlEn ISOEn PeriEn CtrlBlkRatio Bits Descriptions [31:11] Reserved Remote Wakeup Connected Enable [10] RWakeEn If a remote wakeup signal is supported, this bit enables that operation.
Page 640 N9H26 Technical Reference Manual Bits Descriptions Interrupt EDs may be serviced). While processing the Periodic List, the Host Controller will check this bit when it finds an isochronous ED. Periodic List Enable PeriEn When set, this bit enables processing of the Periodic (interrupt and isochronous) list. The Host Controller checks this bit prior to attempting any periodic transfers in a frame.
Page 641 N9H26 Technical Reference Manual Host Controller Command Status Register (HcComSts) Register Address Description Reset Value HcComSts OHCI_BA+0x808 Host Controller Command Status Register 0x0000_0000 Reserved Reserved SchOverRun Reserved Reserved OCReq BlkFill CtrlFill HCReset Bits Descriptions [31:18] Reserved Schedule Overrun Count [17:16] SchOverRun This field is increment every time the SchedulingOverrun bit in HcInterruptStatus is set.
Page 642 N9H26 Technical Reference Manual Host Controller Interrupt Status Register (HcIntSts) Register Address Description Reset Value HcIntSts OHCI_BA+0x80C Host Controller Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved Reserved RHSC FNOF UnRecErr Resume WBDnHD SchOR Bits Descriptions [31] Reserved Ownership Change [30] This bit is set when the OwnershipChangeRequest bit of HcCommandStatus is set.
Page 643 N9H26 Technical Reference Manual Host Controller Interrupt Enable Register (HcIntEn) Register Address Description Reset Value HcIntEn OHCI_BA+0x810 Host Controller Interrupt Enable Register 0x0000_0000 IntEn OCEn Reserved Reserved Reserved Reserved RHSCEn FNOFEn URErrEn ResuEn SOFEn WBDHEn SchOREn Bits Descriptions Master Interrupt Enable [31] IntEn This bit is a global interrupt enable.
Page 644 N9H26 Technical Reference Manual Bits Descriptions 1: Enables interrupt generation due to Write-back Done Head. Scheduling Overrun Enable SchOREn 0: Ignore 1: Enables interrupt generation due to Scheduling Overrun. Publication Release Date: Sept. 10, 2018 - 644 - Revision V1.01...
Page 645 N9H26 Technical Reference Manual Host Controller Interrupt Disable Register (HcIntDis) Register Address Description Reset Value HcIntDis OHCI_BA+0x814 Host Controller Interrupt Disable Register 0x0000_0000 IntDis OCDis Reserved Reserved Reserved Reserved RHSCDis FNOFDis URErrDis ResuDis SOFDis WBDHDis SchORDis Bits Descriptions Master Interrupt Disable [31] IntDis Global interrupt disable.
Page 646 N9H26 Technical Reference Manual Bits Descriptions Scheduling Overrun Disable SchORDis 0: Ignore 1: Disables interrupt generation due to Scheduling Overrun. Publication Release Date: Sept. 10, 2018 - 646 - Revision V1.01...
Page 647 N9H26 Technical Reference Manual Host Controller Communication Area Register (HcHCCA) Register Address Description Reset Value HcHCCA OHCI_BA+0x818 Host Controller Communication Area Register 0x0000_0000 HCCA HCCA HCCA Reserved Bits Descriptions Host Controller Communication Area [31:7] HCCA Pointer to HCCA base address. [7:0] Reserved Publication Release Date: Sept.
Page 648 N9H26 Technical Reference Manual Host Controller Period Current ED Register (HcPerCED) Register Address Description Reset Value HcPerCED OHCI_BA+0x81C Host Controller Period Current ED Register 0x0000_0000 PeriCED PeriCED PeriCED PeriCED Reserved Bits Descriptions Periodic Current ED [31:4] PeriCED Pointer to the current Periodic List ED. [3:0] Reserved Publication Release Date: Sept.
Page 649 N9H26 Technical Reference Manual Host Controller Control Head ED Register (HcCtrHED) Register Address Description Reset Value HcCtrHED OHCI_BA+0x820 Host Controller Control Head ED Register 0x0000_0000 CtrlHED CtrlHED CtrlHED CtrlHED Reserved Bits Descriptions Control Head ED [31:4] CtrlHED Pointer to the Control List Head ED. [3:0] Reserved Publication Release Date: Sept.
Page 650 N9H26 Technical Reference Manual Host Controller Control Current ED Register (HcCtrCED) Register Address Description Reset Value HcCtrCED OHCI_BA+0x824 Host Controller Control Current ED Register 0x0000_0000 CtrlCED CtrlCED CtrlCED CtrlCED Reserved Bits Descriptions Control Current Head ED [31:4] CtrlCED Pointer to the current Control List Head ED. [3:0] Reserved Publication Release Date: Sept.
Page 651 N9H26 Technical Reference Manual Host Controller Bulk Head ED Register (HcBlkHED) Register Address Description Reset Value HcBlkHED OHCI_BA+0x828 Host Controller Bulk Head ED Register 0x0000_0000 BlkHED BlkHED BlkHED BlkHED Reserved Bits Descriptions Bulk Head ED [31:4] BlkHED Pointer to the Bulk List Head ED. [3:0] Reserved Publication Release Date: Sept.
Page 652 N9H26 Technical Reference Manual Host Controller Bulk Current Head ED Register (HcBlkCED) Register Address Description Reset Value HcBlkCED OHCI_BA+0x82C Host Controller Bulk Current ED Register 0x0000_0000 BlkCED BlkCED BlkCED BlkCED Reserved Bits Descriptions Bulk Current Head ED [31:4] BlkCED Pointer to the current Bulk List Head ED. [3:0] Reserved Publication Release Date: Sept.
Page 653 N9H26 Technical Reference Manual Host Controller Done Head Register (HcDoneH) Register Address Description Reset Value HcDoneH OHCI_BA+0x830 Host Controller Done Head Register 0x0000_0000 DoneH DoneH DoneH DoneH Reserved Bits Descriptions Done Head [31:4] DoneH Pointer to the current Done List Head ED. [3:0] Reserved Publication Release Date: Sept.
Page 654 N9H26 Technical Reference Manual Host Controller Frame Interval Register (HcFmIntv) Register Address Description Reset Value HcFmIntv OHCI_BA+0x834 Host Controller Frame Interval Register 0x0000_2EDF FmIntvT FSDPktCnt FSDPktCnt Reserved FmInterval FmInterval Bits Descriptions Frame Interval Toggle [31] FmIntvT This bit is toggled by HCD when it loads a new value into FrameInterval. FS Largest Data Packet [30: 16] FSDPktCnt...
Page 655 N9H26 Technical Reference Manual Host Controller Frame Remaining Register (HcFmRem) Register Address Description Reset Value HcFmRem OHCI_BA+0x838 Host Controller Frame Remaining Register 0x0000_0000 FmRemT Reserved Reserved Reserved FmRemain FmRemain Bits Descriptions Frame Remaining Toggle [31] FmRemT Loaded with FrameIntervalToggle when FrameRemaining is loaded. [30:14] Reserved Frame Remaining...
Page 656 N9H26 Technical Reference Manual Host Controller Frame Number Register (HcFNum) Register Address Description Reset Value HcFNum OHCI_BA+0x83C Host Controller Frame Number Register 0x0000_0000 Reserved Reserved FmNum FmNum Bits Descriptions [31:16] Reserved Frame Number [15:0] FmNum This 16-bit incrementing counter field is incremented coincident with the loading of FrameRemaining.
Page 657 N9H26 Technical Reference Manual Host Controller Periodic Start Register (HcPerSt) Register Address Description Reset Value HcPerSt OHCI_BA+0x840 Host Controller Periodic Start Register 0x0000_0000 Reserved Reserved Reserved PeriStart PeriStart Bits Descriptions [31:14] Reserved Periodic Start [13:0] PeriStart This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
Page 658 N9H26 Technical Reference Manual Host Controller Root Hub Descriptor A Register (HcRhDeA) Register Address Description Reset Value HcRhDeA OHCI_BA+0x848 Host Controller Root Hub Descriptor A Register 0x0100_0002 PwrGDT Reserved Reserved NOCP OCPM DevType DPortNum Bits Descriptions Power On to Power Good Time This field value is represented as the number of 2 ms intervals, which ensuring that the power switching is effective within 2 ms.
Page 659 N9H26 Technical Reference Manual Bits Descriptions 0 = Global Switching 1 = Individual Switching Number Downstream Ports [7:0] DPortNum HYDRA-4 supports two downstream ports. Publication Release Date: Sept. 10, 2018 - 659 - Revision V1.01...
Page 660 N9H26 Technical Reference Manual Host Controller Root Hub Status Register (HcRhSts) Register Address Description Reset Value HcRhSts OHCI_BA+0x850 Host Controller Root Hub Status Register 0x0000_0000 RWEClr Reserved Reserved OCIC LPSC DRWEn Reserved Reserved Bits Descriptions Clear Remote Wakeup Enable [31] RWEClr Writing a '1' to this bit clears DeviceRemoteWakeupEnable.
Page 661 N9H26 Technical Reference Manual Bits Descriptions (Write) ClearGlobalPower Writing a '1' issues a ClearGlobalPower command to the ports. Writing a '0' has no effect. Publication Release Date: Sept. 10, 2018 - 661 - Revision V1.01...
Page 662 N9H26 Technical Reference Manual Host Controller Root Hub Port Status (HcRhPrt [1: 2]) Register Address Description Reset Value HcRhPrt1 OHCI_BA+0x854 Host Controller Root Hub Port Status [1] 0x0000_0000 Reserved Reserved PRSC POCIC PSSC PESC Reserved LSDev Reserved Bits Descriptions [31:21] Reserved Port Reset Status Change This bit indicates that the port reset signal has completed.
Page 663 N9H26 Technical Reference Manual Bits Descriptions (Read) LowSpeedDeviceAttached This bit defines the speed (and bud idle) of the attached device. It is only valid when CurrentConnectStatus is set. 0 = Full Speed device LSDev 1 = Low Speed device (Write) ClearPortPower Writing a '1' clears PortPowerStatus.
Page 664 N9H26 Technical Reference Manual Bits Descriptions (Write) ClearPortEnable Writing '1' a clears PortEnableStatus. Writing a '0' has no effect. Publication Release Date: Sept. 10, 2018 - 664 - Revision V1.01...
Page 665 N9H26 Technical Reference Manual USB Operational Mode Enable Register (OpModEn) Register Address Description Reset Value OpModEn OHCI_BA+0xA04 USB Operational Mode Enable Register 0X0000_0000 Reserved Reserved DisPrt0 Reserved SIEPDis Reserved OCALow Reserved ABORT DBR16 Bits Descriptions [31:18] Reserved [17] Reserved Disable Port 0 This bit controls if the connection between USB host controller and transceiver of port 0 is disabled.
Page 666 N9H26 Technical Reference Manual Bits Descriptions 1: ERROR response received Data Buffer Region 16 DBR16 When set, the size of the data buffer region is 16 bytes. Otherwise, the size is 32 bytes. Publication Release Date: Sept. 10, 2018 - 666 - Revision V1.01...
Page 667: Usb Host Controller (Uhc)
N9H26 Technical Reference Manual 5.15 USB Host Controller (UHC) 5.15.1 Overview The Universal Serial Bus (USB) is a low-cost, low-to mid-speed peripheral interface standard intended for modem, scanners, PDAs, keyboards, mice, and other devices that do not require a high- bandwidth parallel interface.
Page 668: Block Diagram
N9H26 Technical Reference Manual 5.15.3 Block Diagram USB Host Controller AHB Interface AHB Slave AHB Master Host Controller Frame List Processor Management Master Interrupts Data Buffer USB Interface Clock Gen. Root Control Port1 Port0 Publication Release Date: Sept. 10, 2018 - 668 - Revision V1.01...
Page 669: Operation
N9H26 Technical Reference Manual 5.15.4 Operation 5.15.4.1 OHCI Controller 5.15.4.2 AHB Interface The OpenHCI Host Controller is connected to the system by the AHB bus. The design requires both master and slave bus operations. As a master, the Host Controller is responsible for running cycles on the AHB bus to access EDs and TDs as well as transferring data between memory and the local data buffer.
Page 670 N9H26 Technical Reference Manual by USB. The SIE is responsible for managing all transactions to the USB. It controls the bus protocol, packet generation/extraction, data parallel-to-serial conversion, CRC coding, bit stuffing, and NRZI encoding. All transactions on the USB are requested from the List Processor and Frame Manager. Root Hub The Root Hub is a collection of ports that are individually controlled and a hub that maintains control/status over functions common to all ports.
Page 671: Register Map
N9H26 Technical Reference Manual 5.15.5 Register Map Register Offset Description Reset Value Capability Registers (UHC_BA =0xB100_9000) HcRev UHC_BA+0x000 Host Controller Revision Register 0x0000_0110 HcControl UHC_BA+0x004 Host Controller Control Register 0x0000_0000 HcComSts UHC_BA+0x008 Host Controller Command Status Register 0x0000_0000 HcIntSts UHC_BA+0x00C Host Controller Interrupt Status Register 0x0000_0000 HcIntEn...
Page 672: Register Details
N9H26 Technical Reference Manual 5.15.6 Register Details Publication Release Date: Sept. 10, 2018 - 672 - Revision V1.01...
Page 673 N9H26 Technical Reference Manual Host Controller Revision Register (HcRev) Register Address Description Reset Value HcRev UHC_BA+0x000 Host Controller Revision Register 0x0000_0110 Reserved Reserved Reserved Bits Descriptions [31:9] Reserved Revision Indicates the Open HCI Specification revision number implemented by the Hardware. [8:0] Host Controller supports 1.1 specification.
Page 674 N9H26 Technical Reference Manual Host Controller Control Register (HcControl) Register Address Description Reset Value HcControl UHC_BA+0x004 Host Controller Control Register 0x0000_0000 Reserved Reserved Reserved Reserved Reserved IntRoute HcFunc BlkEn CtrlEn ISOEn PeriEn CtrlBlkRatio Bits Descriptions [31:11] Reserved [10] Reserved Reserved Interrupt Routing This bit is used for interrupt routing: IntRoute...
Page 675 N9H26 Technical Reference Manual Bits Descriptions The Host Controller checks this bit prior to attempting any periodic transfers in a frame. Control Bulk Service Ratio Specifies the number of Control Endpoints serviced for every Bulk Endpoint. Encoding [1:0] CtrlBlkRatio is N-1 where N is the number of Control Endpoints (i.e. ‘00’ = 1 Control Endpoint; ‘11’ = 3 Control Endpoints) Publication Release Date: Sept.
Page 676 N9H26 Technical Reference Manual Host Controller Command Status Register (HcComSts) Register Address Description Reset Value HcComSts UHC_BA+0x008 Host Controller Command Status Register 0x0000_0000 Reserved Reserved SchOverRun Reserved Reserved Reserved BlkFill CtrlFill Reserved Bits Descriptions [31:18] Reserved Schedule Overrun Count [17:16] SchOverRun This field is increment every time the SchedulingOverrun bit in HcInterruptStatus is set.
Page 677 N9H26 Technical Reference Manual Host Controller Interrupt Status Register (HcIntSts) Register Address Description Reset Value HcIntSts UHC_BA+0x00C Host Controller Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved Reserved RHSC FNOF Reserved Resume WBDnHD SchOR Bits Descriptions [31] Reserved Ownership Change [30] This bit is set when the OwnershipChangeRequest bit of HcCommandStatus is set.
Page 678 N9H26 Technical Reference Manual Host Controller Interrupt Enable Register (HcIntEn) Register Address Description Reset Value HcIntEn UHC_BA+0x010 Host Controller Interrupt Enable Register 0x0000_0000 IntEn OCEn Reserved Reserved Reserved Reserved RHSCEn FNOFEn Reserved ResuEn SOFEn WBDHEn SchOREn Bits Descriptions Master Interrupt Enable [31] IntEn This bit is a global interrupt enable.
Page 679 N9H26 Technical Reference Manual Bits Descriptions Scheduling Overrun Enable SchOREn 0: Ignore 1: Enables interrupt generation due to Scheduling Overrun. Host Controller Interrupt Disable Register (HcIntDis) Register Address Description Reset Value HcIntDis UHC_BA+0x014 Host Controller Interrupt Disable Register 0x0000_0000 IntDis OCDis Reserved Reserved...
Page 680 N9H26 Technical Reference Manual Bits Descriptions 1: Disables interrupt generation due to Start of Frame. Write Back Done Head Disable WBDHDis 0: Ignore 1: Disables interrupt generation due to Write-back Done Head. Scheduling Overrun Disable SchORDis 0: Ignore 1: Disables interrupt generation due to Scheduling Overrun. Publication Release Date: Sept.
Page 681 N9H26 Technical Reference Manual Host Controller Communication Area Register (HcHCCA) Register Address Description Reset Value HcHCCA UHC_BA+0x018 Host Controller Communication Area Register 0x0000_0000 HCCA HCCA HCCA Reserved Bits Descriptions Host Controller Communication Area [31:8] HCCA Pointer to HCCA base address. [7:0] Reserved Publication Release Date: Sept.
Page 682 N9H26 Technical Reference Manual Host Controller Period Current ED Register (HcPerCED) Register Address Description Reset Value HcPerCED UHC_BA+0x01C Host Controller Period Current ED Register 0x0000_0000 PeriCED PeriCED PeriCED PeriCED Reserved Bits Descriptions Periodic Current ED [31:4] PeriCED Pointer to the current Periodic List ED. [3:0] Reserved Publication Release Date: Sept.
Page 683 N9H26 Technical Reference Manual Host Controller Control Head ED Register (HcCtrHED) Register Address Description Reset Value HcCtrHED UHC_BA+0x020 Host Controller Control Head ED Register 0x0000_0000 CtrlHED CtrlHED CtrlHED CtrlHED Reserved Bits Descriptions Control Head ED [31:4] CtrlHED Pointer to the Control List Head ED. [3:0] Reserved Publication Release Date: Sept.
Page 684 N9H26 Technical Reference Manual Host Controller Control Current ED Register (HcCtrCED) Register Address Description Reset Value HcCtrCED UHC_BA+0x024 Host Controller Control Current ED Register 0x0000_0000 CtrlCED CtrlCED CtrlCED CtrlCED Reserved Bits Descriptions Control Current Head ED [31:4] CtrlCED Pointer to the current Control List Head ED. [3:0] Reserved Publication Release Date: Sept.
Page 685 N9H26 Technical Reference Manual Host Controller Bulk Head ED Register (HcBlkHED) Register Address Description Reset Value HcBlkHED UHC_BA+0x028 Host Controller Bulk Head ED Register 0x0000_0000 BlkHED BlkHED BlkHED BlkHED Reserved Bits Descriptions Bulk Head ED [31:4] BlkHED Pointer to the Bulk List Head ED. [3:0] Reserved Publication Release Date: Sept.
Page 686 N9H26 Technical Reference Manual Host Controller Bulk Current Head ED Register (HcBlkCED) Register Address Description Reset Value HcBlkCED UHC_BA+0x02C Host Controller Bulk Current ED Register 0x0000_0000 BlkCED BlkCED BlkCED BlkCED Reserved Bits Descriptions Bulk Current Head ED [31:4] BlkCED Pointer to the current Bulk List Head ED. [3:0] Reserved Publication Release Date: Sept.
Page 687 N9H26 Technical Reference Manual Host Controller Done Head Register (HcDoneH) Register Address Description Reset Value HcDoneH UHC_BA+0x030 Host Controller Done Head Register 0x0000_0000 DoneH DoneH DoneH DoneH Reserved Bits Descriptions Done Head [31:4] DoneH Pointer to the current Done List Head ED. [3:0] Reserved Publication Release Date: Sept.
Page 688 N9H26 Technical Reference Manual Host Controller Frame Interval Register (HcFmIntv) Register Address Description Reset Value HcFmIntv UHC_BA+0x034 Host Controller Frame Interval Register 0x0000_2EDF FmIntvT Reserved FSDPktCnt FSDPktCnt Reserved FmInterval FmInterval Bits Descriptions Frame Interval Toggle [31] FmIntvT This bit is toggled by HCD when it loads a new value into FrameInterval. [30] Reserved FS Largest Data Packet...
Page 689 N9H26 Technical Reference Manual Host Controller Frame Remaining Register (HcFmRem) Register Address Description Reset Value HcFmRem UHC_BA+0x038 Host Controller Frame Remaining Register 0x0000_0000 FmRemT Reserved Reserved Reserved FmRemain FmRemain Bits Descriptions Frame Remaining Toggle [31] FmRemT Loaded with FrameIntervalToggle when FrameRemaining is loaded. [30:14] Reserved Frame Remaining...
Page 690 N9H26 Technical Reference Manual Host Controller Frame Number Register (HcFNum) Register Address Description Reset Value HcFNum UHC_BA+0x03C Host Controller Frame Number Register 0x0000_0000 Reserved Reserved FmNum FmNum Bits Descriptions [31:16] Reserved Frame Number [15:0] FmNum This 16-bit incrementing counter field is incremented coincident with the loading of FrameRemaining.
Page 691 N9H26 Technical Reference Manual Host Controller Periodic Start Register (HcPerSt) Register Address Description Reset Value HcPerSt UHC_BA+0x040 Host Controller Periodic Start Register 0x0000_0000 Reserved Reserved Reserved PeriStart PeriStart Bits Descriptions [31:14] Reserved Periodic Start [13:0] PeriStart This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
Page 692 N9H26 Technical Reference Manual Host Controller Low Speed Threshold Register (HcLSTH) Register Address Description Reset Value HcLSTH UHC_BA+0x044 Host Controller Low Speed Threshold Register 0x0000_0628 Reserved Reserved Reserved Bits Descriptions [31:12] Reserved Low Speed Threshold This field contains a value which is compared to the FrameRemaining field prior to [11:0] initiating a Low Speed transaction.
Page 693 N9H26 Technical Reference Manual Host Controller Root Hub Descriptor A Register (HcRhDeA) Register Address Description Reset Value 0x1000_0002 HcRhDeA UHC_BA+0x048 Host Controller Root Hub Descriptor A Register Reserved PwrGDT Reserved Reserved NOCP OCPM Reserved Reserved Reserved DPortNum Bits Descriptions [31:26] Reserved Power On to Power Good Time This field value is represented as the number of 2 ms intervals, which ensuring that the...
Page 694 N9H26 Technical Reference Manual Bits Descriptions [7:4] Reserved Number Downstream Ports [3:0] DPortNum HYDRA-4 supports two downstream ports. It is read only. Publication Release Date: Sept. 10, 2018 - 694 - Revision V1.01...
Page 695 N9H26 Technical Reference Manual Host Controller Root Hub Descriptor B Register (HcRhDeB) Register Address Description Reset Value HcRhDeB UHC_BA+0x04C Host Controller Root Hub Descriptor B Register 0x0000_0000 Reserved Reserved PPCM Reserved Reserved Reserved DevRemove Reserved Bits Descriptions [31:19] Reserved Port Power Control Mask Global-power switching.
Page 696 N9H26 Technical Reference Manual Host Controller Root Hub Status Register (HcRhSts) Register Address Description Reset Value HcRhSts UHC_BA+0x050 Host Controller Root Hub Status Register 0x0000_0000 Reserved Reserved OCIC Reserved DRWEn Reserved Reserved Reserved Bits Descriptions [31:18] Reserved Over Current Indicator Change [17] OCIC This bit is set when OverCurrentIndicator changes.
Page 697 N9H26 Technical Reference Manual Host Controller Root Hub Port Status (HcRhPrt [1: 2]) Register Address Description Reset Value HcRhPrt1 UHC_BA+0x054 Host Controller Root Hub Port Status [1] 0x0000_0000 HcRhPrt0 UHC_BA+0x058 Host Controller Root Hub Port Status [0] 0x0000_0000 Reserved Reserved PRSC POCIC PSSC...
Page 698 N9H26 Technical Reference Manual Bits Descriptions (Read) LowSpeedDeviceAttached This bit defines the speed (and bud idle) of the attached device. It is only valid when CurrentConnectStatus is set. 0 = Full Speed device LSDev 1 = Low Speed device (Write) ClearPortPower Writing a '1' clears PortPowerStatus.
Page 699 N9H26 Technical Reference Manual Bits Descriptions NOTE: If DeviceRemoveable is set (not removable) this bit is always '1'. (Write) ClearPortEnable Writing '1' a clears PortEnableStatus. Writing a '0' has no effect. Publication Release Date: Sept. 10, 2018 - 699 - Revision V1.01...
Page 700 N9H26 Technical Reference Manual USB Miscellaneous Control Register (MiscCtrl) Register Address Description Reset Value MiscCtrl UHC_BA+0x200 USB Miscellaneous Control Register 0X0000_0000 Reserved StbyEn Reserved Reserved Reserved Reserved Bits Descriptions [31:28] Reserved USB Tranceiver Standby Enable This bit controls if USB 1.1 transceiver could enter the standby mode to reduce power consumption.
Page 701 N9H26 Technical Reference Manual USB Operational Mode Enable Register (OpModEn) Register Address Description Reset Value OpModEn UHC_BA+0x204 USB Operational Mode Enable Register 0X0000_0000 Reserved Reserved DisPrt0 DisPrt1 Reserved SIEPDis Reserved PPCLow OCALow Reserved ABORT DBR16 Bits Descriptions [31:18] Reserved Disable Port 0 This bit controls if the connection between USB host controller and transceiver of port 0 is disabled.
Page 702 N9H26 Technical Reference Manual Bits Descriptions 0: Port power control is high active 1: Port power control is low active Over Current Active Low This bit controls the polarity of over current flag from external power IC. OCALow 0: Over current flag is high active 1: Over current flag is low active Reserved AHB Bus ERROR Response...
Page 703: Enhanced Dma Controller
N9H26 Technical Reference Manual 5.16 Enhanced DMA Controller The N9H26 contains an enhanced direct memory access (EDMA) controller that transfers data to and from memory or transfer data to and from APB. The EDMA controller has 6-channel DMA that include 2 channel VDMA (Video-DMA, Memory-to-Memory) and four channels PDMA (Peripheral-to-Memory or Memory-to-Peripheral).
Page 704: Symbol Diagram
N9H26 Technical Reference Manual 5.16.2 Symbol Diagram 5.16.2.1 The symbol diagram of EDMA controller is shown as fallowing. Figure 5.16-1 EDMA Controller Symbol Diagram Publication Release Date: Sept. 10, 2018 - 704 - Revision V1.01...
Page 705: Block Diagram
N9H26 Technical Reference Manual 5.16.3 Block Diagram Figure 5.16-2 EDMA Controller Block Diagram 5.16.4 Function Description The N9H26 contains an enhanced direct memory access (EDMA) controller that transfers data to and from memory or transfer data to and from APB. The EDMA controller has 6-channel DMA that include 2 channels VDMA (Video-DMA, Memory-to-Memory) and four channels PDMA (Peripheral-to-Memory or Memory-to-Peripheral).
Page 706: Figure 5.16-3 Peripheral Interface Signal
N9H26 Technical Reference Manual not in wrap around mode, the transfer will start transfer until DMA_CBCRx reaches zero (in wrap around mode, when DMA_CBCRx equal zero, the DMA will reload DMA_CBCRx and work around until software disable DMA_CSRx [DMACEN]), If an error occurs during the EDMA operation, the channel stops unless software clears the error condition and sets the DMA_CSRx [SW_RST] to reset the EDMA channel and set EDMA_CSRx [EDMACEN] and [Trig_EN] bits field to start again.
Page 707: Figure 5.16-4 .Handsharking Signal
N9H26 Technical Reference Manual Figure 5.16-4 .handsharking signal The N9H26 series also support hardware scatter-gather function, software can set DMA_CSRx [SG_EN] to enable scatter-gather function. When in scatter-gather function mode, some register will automatically updated by descriptor table. The descriptor table format and program flow is show as following: Here is a simple example programming flow with DMA Scatter-Gather enable.
Page 708: Figure 5.16-5 Descriptor Table Format
N9H26 Technical Reference Manual Figure 5.16-5 Descriptor Table Format Publication Release Date: Sept. 10, 2018 - 708 - Revision V1.01...
Page 709: Edma Controller Registers Map
N9H26 Technical Reference Manual 5.16.5 EDMA Controller Registers Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value VDMA_BA = 0xB000_8000 (Channel 0 Base Address) , VDMA_BA = 0xB000_8800 (EDMA2 Channel 0 Base Address) VDMA_BA = 0xB000_8500 (Channel 5 Base Address) VDMA_CSR VDMA_BA + 0x00...
Page 710 N9H26 Technical Reference Manual Register Offset Description Reset Value PDMA_SGAR PDMA_BA + 0x10 PDMA Scatter-Gather Start Address 0x0000_0000 PDMA Current Source Address PDMA_CSAR PDMA_BA + 0x14 0x0000_0000 Register PDMA Current Destination Address PDMA_CDAR PDMA_BA + 0x18 0x0000_0000 Register PDMA Current Transfer Byte Count PDMA_CBCR PDMA_BA + 0x1C 0x0000_0000...
Page 711: Edma Control Register
N9H26 Technical Reference Manual 5.16.6 EDMA Control Register VDMA Control and Status Register (VDMA_CSR) Register Offset Description Reset Value VDMA_CSR 0x000 VMAC Control and Status Register (EDMA CH0) 0x0000_0000 Reserved Trig_EN Reserved Reserved SG_EN VDMA_RST DAD_SEL SAD_SEL Reserved SW_RST VDMACEN Bits Descriptions [31:24]...
Page 712 N9H26 Technical Reference Manual Bits Descriptions [3:2] Reserved Reserved Software Engine Reset 0 = Writing 0 to this bit has no effect. SW_RST 1 = Writing 1 to this bit will reset the internal state machine and pointers. The contents of control register will not be cleared.
Page 713 N9H26 Technical Reference Manual VDMA Transfer Source Address Register (VDMA_SAR) Register Offset Description Reset Value VDMA_SAR 0x004 VDMA Transfer Source Address Register. 0x0000_0000 VDMA_SAR [31:24] VDMA_SAR [23:16] VDMA_SAR [15:8] VDMA_SAR [7:0] Bits Descriptions VDMA Transfer Source Address Register This field indicates a 32-bit source address of VDMA. When in scatter-gather mode, this field [31:0] VDMA_SAR will be updated automatically by descriptor table, so when in scatter-gather mode this field is...
Page 714 N9H26 Technical Reference Manual VDMA Transfer Destination Address Register (VDMA_DAR) Register Offset Description Reset Value VDMA_DAR4 0x008 VDMA Transfer Destination Address Register. 0x0000_0000 VDMA_DAR [31:24] VDMA_DAR [23:16] VDMA_DAR [15:8] VDMA_DAR [7:0] Bits Descriptions VDMA Transfer Destination Address Register This field indicates a 32-bit destination address of VDMA. When in scatter-gather mode, this [31:0] VDMA_DAR field will be updated automatically by descriptor table, so when in scatter-gather mode this...
Page 715 N9H26 Technical Reference Manual VDMA Transfer Byte Count Register (VDMA_BCR) Register Offset Description Reset Value VDMA_BCR 0x00C VDMA Transfer Byte Count Register. 0x0000_0000 Reserved VDMA_BCR [23:16] VDMA_BCR [15:8] VDMA_BCR [7:0] Bits Descriptions [31:24] Reserved Reserved VDMA Transfer Byte Count Register This field indicates a 24-bit transfer byte count of VDMA.
Page 716 N9H26 Technical Reference Manual VDMA Scatter Gather Table Start Address Register (VDMA_SCAR) Register Offset Description Reset Value VDMA_SGAR 0x010 VDMA Scatter Gather Table Start Address Register. 0x0000_0000 VDMA_SGAR [31:24] VDMA_SGAR [23:16] VDMA_SGAR [15:8] VDMA_SGAR [7:0] Bits Descriptions VDMA Scatter Gather Table Start Address Register This field indicates a 32-bit Scatter Gather Table Start address of VDMA.
Page 717 N9H26 Technical Reference Manual VDMA Current Source Address Register (VDMA_CSAR) Register Address Description Reset Value VDMA_CSAR4 0x014 VDMA Current Source Address Register. 0x0000_0000 VDMA_CSAR [31:24] VDMA_CSAR [23:16] VDMA_CSAR [15:8] VDMA_CSAR [7:0] Bits Descriptions VDMA Current Source Address Register (Read Only) VDMA_CSAR [31:0] This field indicates the source address where the VDMA transfer is just occurring.
Page 718 N9H26 Technical Reference Manual EDMA Current Destination Address Register (VDMA_CDAR) Register Offset Description Reset Value VDMA_CDAR 0x018 VDMA Current Destination Address Register 0x0000_0000 VDMA_CDAR [31:24] VDMA_CDAR [23:16] VDMA_CDAR [15:8] VDMA_CDAR [7:0] Bits Descriptions VDMA Current Destination Address Register (Read Only) [31:0] VDMA_CDAR This field indicates the destination address where the VDMA transfer is just occurring.
Page 719 N9H26 Technical Reference Manual VDMA Current Byte Count Register (VDMA_CBCR) Register Offset Description Reset Value VDMA_CBCR 0x01C VDMA Current Byte Count Register. 0x0000_0000 Reserved VDMA_CBCR [23:16] VDMA_CBCR [15:8] VDMA_CBCR [7:0] Bits Descriptions Reserved [31:24] Reserved VDMA Current Byte Count Register (Read Only) VDMA_CBCR [23:0] This field indicates the current remained byte count of VDMA.
Page 720 N9H26 Technical Reference Manual VDMA Interrupt Enable Control Register (VDMA_IER) Register Offset Description Reset Value VDMA_IER 0x020 VDMA Interrupt Enable Control Register. 0x0000_0001 Reserved Reserved Reserved Reserved SG_IEN Reserved BLKD_IE TABORT_IE Bits Descriptions Reserved [31:4] Reserved VDMA Scatter-Gather Interrupt Enable SG_IEN 0 = Disable scatter-gather interrupt generator.
Page 721 N9H26 Technical Reference Manual VDMA Interrupt Status Register (VDMA_ISR) Register Address Description Reset Value VDMA_ISR 0x024 VDMA Interrupt Status Register. 0x0x0x_0000 INTR Reserved INTR5 INTR4 INTR3 INTR2 INTR1 INTR0 Reserved Busy Reserved Reserved SG_IF Reserved BLKD_IF TABORT_IF Bits Descriptions Interrupt Pin Status (Read Only) [31] INTR This bit is the Interrupt pin status of EDMA controller.
Page 722 N9H26 Technical Reference Manual Bits Descriptions EDMA Transfer is in Progress (Read Only) [15] Busy 0 = EDMA transfer is not in progress. 1 = EDMA transfer is in progress. [14:4] Reserved Reserved VDMA Scatter-Gather Interrupt Flag 0 = Scatter-gather descriptor table not finished transfer. SG_IF 1 = A scatter-gather descriptor table have been transfer done.
Page 723 N9H26 Technical Reference Manual VDMA Color Transform Control Register (VDMA_CTCSR) Register Offset Description Reset Value VDMA_CTCSR 0x028 VDMA Color Transform Control Register. 0x0000_0000 Reserved Sour Format Reserved Dest Format Reserved Clamping_ Reserved Col_tra_EN Stride_ Bits Descriptions [31:28] Reserved Reserved Source Address Color Format Choose 1000 = The Source format is YCbCr 422 (VYUY) packaging format 0100 = The Source format is RGB565 packaging format 0010 = The Source format is RGB555 packaging format...
Page 724 N9H26 Technical Reference Manual Bits Descriptions 0 = Disable Color transfer enable mode. 1 = Enable Color transfer mode. Stride Mode Enable Stride_EN 0 = Disable stride transfer mode. 1 = Enable stride transfer mode. Publication Release Date: Sept. 10, 2018 - 724 - Revision V1.01...
Page 725 N9H26 Technical Reference Manual VDMA Source Address Stride Offset Control Register (VDMA_SASOCR) Register Address Description Reset Value VDMA_SASOCR 0x02C VDMA Source Address Stride Offset Control Register 0x0000_0000 STBC[15:8] STBC[7:0] SASTOBL[15:8] SASTOBL[7:0] Bits Descriptions VDMA Stride Transfer Byte Count The 16 bits register define the stride transfer byte count of each row. When in scatter-gather [31:16] STBC mode, this field will be updated automatically by descriptor table, so when in scatter-gather...
Page 726 N9H26 Technical Reference Manual VDMA Stride Destination Address Offset Control Register (VDMA_DASOCR) Register Address Description Reset Value VDMA_DASOCR 0x030 VDMA Destination Address Stride Offset Control Register. 0x0000_0000 Reserved Reserved DASTOBL[15:8] DASTOBL[7:0] Bits Descriptions [31:16] Reserved Reserved VDMA Destination Address Stride Offset Byte Length The 16 bits register define the destination address stride transfer offset count or each row.
Page 727 N9H26 Technical Reference Manual VDMA Shared Buffer FIFO 0 ~ 15 (VDMA_SBUF0 ~ VDMA_SBUF15 ) Register Address Description Reset Value VDMA_SBUF0 ~ 0x080~ VDMA Shared Buffer FIFO (0 ~ 15) Register 0x0000_0000 VDMA_SBUF15 0xBC VDMA_SBUF (0~15) [31:24] VDMA_SBUF (0~15) [23:16] VDMA_SBUF (0~15) [15:8] VDMA_SBUF (0~15) [7:0] Bits...
Page 728 N9H26 Technical Reference Manual PDMA Control and Status Register (PDMA_CSR) Register Offset Description Reset Value PDMA_CSR1 0x100 PMAC Control and Status Register CH1 0x0000_0000 PDMA_CSR2 0x200 PMAC Control and Status Register CH2 0x0000_0000 PDMA_CSR3 0x300 PMAC Control and Status Register CH3 0x0000_0000 PDMA_CSR4 0x400...
Page 729 N9H26 Technical Reference Manual Bits Descriptions [11:10] Reserved Reserved PDMA Scatter-Gather Function Enable Enable PDMA scatter-gather function or not. SG_EN 0 = Normal operation. 1 = Enable scatter-gather operation. EDMA Software Reset 0 = Writing 0 to this bit has no effect. EDMA_RST 1 = Writing 1 to this bit will reset the all channels internal state machine and pointers.
Page 730 N9H26 Technical Reference Manual PDMA Transfer Source Address Register (PDMA_SAR) Register Address Description Reset Value PDMA_SAR1 0x104 PDMA Transfer Source Address Register CH1 0x0000_0000 PDMA_SAR2 0x204 PDMA Transfer Source Address Register CH2 0x0000_0000 PDMA_SAR3 0x304 PDMA Transfer Source Address Register CH3 0x0000_0000 PDMA_SAR4 0x404...
Page 731 N9H26 Technical Reference Manual PDMA Transfer Destination Address Register (PDMA_DAR) Register Offset Description Reset Value PDMA_DAR1 0x108 PDMA Transfer Destination Address Register CH1 0x0000_0000 PDMA_DAR2 0x208 PDMA Transfer Destination Address Register CH2 0x0000_0000 PDMA_DAR3 0x308 PDMA Transfer Destination Address Register CH3 0x0000_0000 PDMA_DAR4 0x408...
Page 732 N9H26 Technical Reference Manual PDMA Transfer Byte Count Register (PDMA_BCR) Register Offset Description Reset Value PDMA_BCR1 0x10C PDMA Transfer Byte Count Register CH1 0x0000_0000 PDMA_BCR2 0x20C PDMA Transfer Byte Count Register CH2 0x0000_0000 PDMA_BCR3 0x30C PDMA Transfer Byte Count Register CH3 0x0000_0000 PDMA_BCR4 0x40C...
Page 733 N9H26 Technical Reference Manual PDMA Scatter Gather Table Start Address Register (PDMA_SGAR) Register Offset Description Reset Value PDMA_SGAR1 0x110 PDMA Scatter Gather Table Start Address Register CH1. 0x0000_0000 PDMA_SGAR2 0x210 PDMA Scatter Gather Table Start Address Register CH2. 0x0000_0000 PDMA_SGAR3 0x310 PDMA Scatter Gather Table Start Address Register CH3.
Page 734 N9H26 Technical Reference Manual PDMA Current Source Address Register (PDMA_CSAR) Register Offset Description Reset Value PDMA_CSAR1 0x114 PDMA Current Source Address Register CH1 0x0000_0000 PDMA_CSAR2 0x214 PDMA Current Source Address Register CH2 0x0000_0000 PDMA_CSAR3 0x314 PDMA Current Source Address Register CH3 0x0000_0000 PDMA_CSAR4 0x414...
Page 735 N9H26 Technical Reference Manual EDMA Current Destination Address Register (PDMA_CDAR) Register Offset Description Reset Value PDMA_CDAR1 0x118 PDMA Current Destination Address Register CH1 0x0000_0000 PDMA_CDAR2 0x218 PDMA Current Destination Address Register CH2 0x0000_0000 PDMA_CDAR3 0x318 PDMA Current Destination Address Register CH3 0x0000_0000 PDMA_CDAR4 0x418...
Page 736 N9H26 Technical Reference Manual PDMA Current Byte Count Register (PDMA_CBCR) Register Offset Description Reset Value PDMA_CBCR1 0x11C PDMA Current Byte Count Register CH1 0x0000_0000 PDMA_CBCR2 0x21C PDMA Current Byte Count Register CH2 0x0000_0000 PDMA_CBCR3 0x31C PDMA Current Byte Count Register CH3 0x0000_0000 PDMA_CBCR4 0x41C...
Page 737 N9H26 Technical Reference Manual PDMA Interrupt Enable Control Register (PDMA_IER) Register Offset Description Reset Value PDMA_IER1 0x120 PDMA Interrupt Enable Control Register CH1 0x0000_0001 PDMA_IER2 0x220 PDMA Interrupt Enable Control Register CH2 0x0000_0001 PDMA_IER3 0x320 PDMA Interrupt Enable Control Register CH3 0x0000_0001 PDMA_IER4 0x420...
Page 738 N9H26 Technical Reference Manual PDMA Interrupt Status Register (PDMA_ISR) Register Offset Description Reset Value PDMA_ISR1 0x124 PDMA Interrupt Status Register CH1 0x0x0x_0000 PDMA_ISR2 0x224 PDMA Interrupt Status Register CH2 0x0x0x_0000 PDMA_ISR3 0x324 PDMA Interrupt Status Register CH3 0x0x0x_0000 PDMA_ISR4 0x424 PDMA Interrupt Status Register CH4 0x0x0x_0000 INTR...
Page 739 N9H26 Technical Reference Manual Bits Descriptions PDMA Transfer is in Progress (Read Only) [15] Busy 0 = PDMA transfer is not in progress. 1 = PDMA transfer is in progress. [14:12] Reserved Reserved Wrap around transfer byte count interrupt flag (Read Only) 0001 = PDMA_CBCR equal 0 flag (Read Only).
Page 740 N9H26 Technical Reference Manual PDMA Internal Buffer Pointer Register (PDMA_POINT) Register Offset Description Reset Value PDMA_POINT1 0x13C PDMA Internal Buffer Pointer Register CH1 0xXXXX_0000 PDMA_POINT2 0x23C PDMA Internal Buffer Pointer Register CH2 0xXXXX_0000 PDMA_POINT3 0x33C PDMA Internal Buffer Pointer Register CH3 0xXXXX_0000 PDMA_POINT4 0x43C...
Page 741 N9H26 Technical Reference Manual PDMA Shared Buffer FIFO 0 ~ 3 (PDMA_SBUF0_Ch1 and PDMA_SBUF0_Ch4) Register Address Description Reset Value PDMA_SBUF0_c1 0x180 PDMA Shared Buffer FIFO 0 Register CH1 0x0000_0000 PDMA_SBUF0_c4 0x480 PDMA Shared Buffer FIFO 0 Register CH4 0x0000_0000 PDMA_SBUF0 ~ 3 [31:24] PDMA_SBUF0 ~3 [23:16] PDMA_SBUF0~3 [15:8] PDMA_SBUF0~3 [7:0]...
Page 742 N9H26 Technical Reference Manual PDMA Shared Buffer FIFO 0 ~ 7 (PDMA_SBUF0_Ch2 and PDMA_SBUF0_Ch3) Register Offset Description Reset Value PDMA_SBUF0_c2 0x280 PDMA Shared Buffer FIFO 0 Register CH2 0x0000_0000 PDMA_SBUF0_c3 0x380 PDMA Shared Buffer FIFO 0 Register CH3 0x0000_0000 PDMA_SBUF0 ~ 7 [31:24] PDMA_SBUF0 ~7 [23:16] PDMA_SBUF0~7 [15:8] PDMA_SBUF0~7 [7:0]...
Page 743: Advanced Interrupt Controller
IRQ by setting the F-bit and I-bit in the current program status register (CPSR). The N9H26 series incorporates the advanced interrupt controller (AIC) that is capable of dealing with the interrupt requests from different sources. Each interrupt source is uniquely assigned to an interrupt channel.
Page 744 N9H26 Technical Reference Manual Channel Name Mode Source WDT_INT Positive Level Watch Dog Timer Interrupt GPIO_INT0 Positive Level GPIO Interrupt 0 GPIO_INT1 Positive Level GPIO Interrupt 1 GPIO_INT2 Positive Level GPIO Interrupt 2 GPIO_INT3 Positive Level GPIO Interrupt 3 Reserved Positive Level Reserved SPU_INT...
Page 745: Aic Block Diagram
N9H26 Technical Reference Manual Channel Name Mode Source VEN_INT Positive Level H264 Encode Interrupt SDIC_INT Positive Level SDIC Interrupt EMCTX_INT Positive Level EMC TX Interrupt EMCRX_INT Positive Level EMC RX Interrupt I2C_INT Positive Level I2C Interrupt KPI_INT Positive Level Keypad Interrupt RSC_INT Positive Level RS Codec Interrupt...
Page 746: Aic Functional Descriptions
N9H26 Technical Reference Manual 5.17.5 AIC Functional Descriptions Hardware Interrupt Vectoring The hardware interrupt vectoring can be used to shorten the interrupt latency. If not used, priority determination must be carried out by software. When the Interrupt Priority Encoding Register (AIC_IPER) is read, it will return an integer representing the channel that is active and having the highest priority.
Page 747 N9H26 Technical Reference Manual When the AIC asserts the nIRQ line, the processor enters interrupt mode and the interrupt handler reads the AIC_IPER, it may happen that interrupt sources de-assert IRQ lines after the processor has taken into account the nIRQ assertion and before the read of the AIC_IPER. This behavior is called a fake interrupt.
Page 748: Aic Registers Map
N9H26 Technical Reference Manual 5.17.6 AIC Registers Map Register Address Description Reset Value AIC_SCR1 AIC_BA+000 Source Control Register 1 0x4747_4747 AIC_SCR2 AIC_BA+004 Source Control Register 2 0x4747_4747 AIC_SCR3 AIC_BA+008 Source Control Register 3 0x4747_4747 AIC_SCR4 AIC_BA+00C Source Control Register 4 0x4747_4747 AIC_SCR5 AIC_BA+010...
Page 749 N9H26 Technical Reference Manual Register Address Description Reset Value AIC_EOSCR AIC_BA+150 End of Service Command Register Undefined AIC_TEST AIC_BA+160 ICE/Debug mode Register Undefined Publication Release Date: Sept. 10, 2018 - 749 - Revision V1.01...
Page 750: Aic Control Registers
N9H26 Technical Reference Manual 5.17.7 AIC Control Registers Publication Release Date: Sept. 10, 2018 - 750 - Revision V1.01...
Page 751 N9H26 Technical Reference Manual AIC Source Control Registers (AIC_SCR1 ~ AIC_SCR12) Register Address R/W/C Description Reset Value AIC_SCR1 ~ AIC_BA+000 ~ Source Control Register 1 ~ 0x4747_4747 AIC_SCR12 AIC_BA+02C Source Control Register 12 TYPE (Channel 3) Reserved PRIORITY (Channel 3) TYPE (Channel 2) Reserved PRIORITY (Channel 2)
Page 752 N9H26 Technical Reference Manual AIC Interrupt Raw Status Register (AIC_IRSR, AIC_IRSRH) Register Address Description Reset Value AIC_IRSR AIC_BA+100 Interrupt Raw Status Register 0x0000_0000 AIC_IRSRH AIC_BA+104 Interrupt Raw Status Register (High) 0x0000_0000 IRS[31:24] Reserved, IRS[23:16] Reserved, IRS[15:8] IRS[47:40], IRS[7:0] IRS[39:32], This register records the intrinsic state within each interrupt channel. Bits Descriptions Interrupt Status...
Page 753 N9H26 Technical Reference Manual AIC Interrupt Active Status Register (AIC_IASR, AIC_IASRH) Register Address Description Reset Value AIC_IASR AIC_BA+108 Interrupt Active Status Register 0x0000_0000 AIC_IASRH AIC_BA+10C Interrupt Active Status Register (High) 0x0000_0000 IAS[31:24] Reserved IAS[23:16] Reserved IAS[15:8] IAS[47:40] IAS[7:0] IAS[39:32] This register indicates the status of each interrupt channel in consideration of the interrupt source type as defined in the corresponding Source Control Register, but regardless of its mask setting.
Page 754 N9H26 Technical Reference Manual AIC Interrupt Status Register (AIC_ISR, AIC_ISRH) Register Address Description Reset Value AIC_ISR AIC_BA+110 Interrupt Status Register 0x0000_0000 AIC_ISRH AIC_BA+114 Interrupt Status Register (High) 0x0000_0000 IS[31:24] Reserved IS[23:16] Reserved IS[15:8] IS[47:40] IS [7:0] IS[39:32] This register identifies those interrupt channels whose are both active and enabled. Bits Descriptions Interrupt Status...
Page 755 N9H26 Technical Reference Manual AIC IRQ Priority Encoding Register (AIC_IPER) Register Address Description Reset Value AIC_IPER AIC_BA+118 Interrupt Priority Encoding Register 0x0000_0000 Reserved Reserved Reserved VECTOR Reserved When the AIC generates the interrupt, VECTOR represents the interrupt channel number that is active, enabled, and has the highest priority. If the representing interrupt channel possesses a priority level 0, then the interrupt asserted is FIQ;...
Page 756 N9H26 Technical Reference Manual AIC Interrupt Source Number Register (AIC_ISNR) Register Address Description Reset Value AIC_ISNR AIC_BA+120 Interrupt Source Number Register 0x0000_0000 Reserved Reserved Reserved Reserved IRQID The purpose of this register is to record the interrupt channel number that is active, enabled, and has the highest priority.
Page 757 N9H26 Technical Reference Manual AIC Output Interrupt Status Register (AIC_OISR) Register Address Description Reset Value AIC_OISR AIC_BA+124 Output Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved The AIC classifies the interrupt into FIQ and IRQ. This register indicates whether the asserted interrupt is FIQ or IRQ.
Page 758 N9H26 Technical Reference Manual AIC Interrupt Mask Register (AIC_IMR) Register Address Description Reset Value AIC_IMR AIC_BA+128 Interrupt Mask Register 0x0000_0000 AIC_IMRH AIC_BA+12C Interrupt Mask Register (High) 0x0000_0000 IM[31:24] Reserved IM[23:16] Reserved IM[15:8] IM[47:40] IM [7:0] IM[39:32] Bits Descriptions Interrupt Mask This bit determines whether the corresponding interrupt channel is enabled or disabled.
Page 759 N9H26 Technical Reference Manual AIC Mask Enable Command Register (AIC_MECR) Register Address Description Reset Value AIC_MECR AIC_BA+130 Mask Enable Command Register Undefined AIC_MECRH AIC_BA+134 Mask Enable Command Register (High) Undefined MEC[31:24] Reserved MEC[23:16] Reserved MEC[15:8] MEC[47:40] MEC[7:0] MEC[39:32] Bits Descriptions Mask Enable Command [47:0] MEC x...
Page 760 N9H26 Technical Reference Manual AIC Mask Disable Command Register (AIC_MDCR) Register Address Description Reset Value AIC_MDCR AIC_BA+138 Mask Disable Command Register Undefined AIC_MDCRH AIC_BA+13C Mask Disable Command Register (High) Undefined MDC[31:24] Reserved MDC[23:16] Reserved MDC[15:8] MDC[47:40] MDC[7:0] MDC[39:32] Bits Descriptions Mask Disable Command [47:0] MDC x...
Page 761 N9H26 Technical Reference Manual AIC Source Set Command Register (AIC_SSCR) Register Address Description Reset Value AIC_SSCR AIC_BA+140 Source Set Command Register Undefined AIC_SSCRH AIC_BA+144 Source Set Command Register (High) Undefined SSC[31:24] Reserved SSC[23:16] Reserved SSC[15:8] SSC[47:40] SSC[7:0] SSC[39:32] When the N9H26 is under debugging or verification, software can activate any interrupt channel by setting the corresponding bit in this register.
Page 762 N9H26 Technical Reference Manual AIC Source Clear Command Register (AIC_SCCR) Register Address Description Reset Value AIC_SCCR AIC_BA+148 Source Clear Command Register Undefined AIC_SCCRH AIC_BA+14C Source Clear Command Register (High) Undefined SCC[31:24] Reserved SCC[23:16] Reserved SCC[15:8] SCC[47:40] SCC[7:0] SCC[39:32] When the N9H26 is under debugging or verification, software can deactivate any interrupt channel by setting the corresponding bit in this register.
Page 763 N9H26 Technical Reference Manual AIC End of Service Command Register (AIC_EOSCR) Register Address Description Reset Value AIC_EOSCR AIC_BA+150 End of Service Command Register Undefined This register is used by the interrupt service routine to indicate that it is completely served. Thus, the interrupt handler can write any value to this register to indicate the end of its interrupt service.
Page 764 N9H26 Technical Reference Manual AIC ICE/Debug Register (AIC_TEST) Register Address Description Reset Value AIC_TEST AIC_BA+160 ICE/Debug mode Register Undefined Reserved Reserved Reserved Reserved Test This register indicates whether AIC_IPER will be cleared or not after been read. If bit0 of AIC_TEST has been set, ICE or debug monitor can read AIC_IPER for verification and the AIC_IPER will not be cleared automatically.
Page 765: General Purpose I/O
N9H26 Technical Reference Manual 5.18 General Purpose I/O 5.18.1 Overview and Features  80 pins of General Purpose I/O are shared with special feature functions.  Supported Features of these I/O are: input or output facilities, pull-up resistors.  All these general purpose I/O functions are achieved by software programming setting and I/O cells selected from SMIC universal standard I/O Cell Library.
Page 766: Gpio Control Register Map
N9H26 Technical Reference Manual 5.18.2 GPIO Control Register Map R: read only, W: write only, R/W: both read and write Register Address Description Reset Value GP_BA = 0xB8001000 GPIOA_OMD GP_BA+0x00 GPIO Port A Bit Output Mode Enable 0x0000_0000 GPIOA_PUEN GP_BA+0x04 GPIO Port A Bit Pull-up Resistor Enable 0x0000_FFFF GPIOA_DOUT...
Page 767 N9H26 Technical Reference Manual Register Address Description Reset Value IRQSRCGPC GP_BA+0x88 GPIO Port C IRQ Source Grouping 0xAAAA_AAAA IRQSRCGPD GP_BA+0x8C GPIO Port D IRQ Source Grouping 0xFFFF_FFFF IRQSRCGPE GP_BA+0x90 GPIO Port E IRQ Source Grouping 0xFFFF_FFFF IRQSRCGPG GP_BA+0x94 GPIO Port G IRQ Source Grouping 0xFFFF_FFFF IRQSRCGPH GP_BA+0x98...
Page 768: Gpio Control Register Description
N9H26 Technical Reference Manual 5.18.3 GPIO Control Register Description GPIO Port [X] Bit Output Mode Enable (GPIOX_OMD) Register Address Description Reset Value GP_BA+0x00 0x0000_0000 GPIOA_OMD GPIO Port A Bit Output Mode Enable GP_BA+0x10 0x0000_0000 GPIOB_OMD GPIO Port B Bit Output Mode Enable GP_BA+0x20 0x0000_0000 GPIOC_OMD...
Page 769 N9H26 Technical Reference Manual GPIO Port [X] Bit Pull-up/Down Resistor Enable (GPIOX_PUEN) Register Address Description Reset Value GP_BA+0x04 0x0000_FFFF GPIOA_PUEN GPIO Port A Bit Pull-up/down Resistor Enable GP_BA+0x14 0x0000_FFFF GPIOB_PUEN GPIO Port B Bit Pull-up/down Resistor Enable GP_BA+0x24 0x0000_FFFF GPIOC_PUEN GPIO Port C Bit Pull-up/down Resistor Enable GP_BA+0x34 0x0000_FFFF...
Page 770 N9H26 Technical Reference Manual GPIO Port [X] Data Output Value (GPIOX_DOUT) Register Address Description Reset Value GP_BA+0x08 0x0000_0000 GPIOA_DOUT GPIO Port A Data Output Value GP_BA+0x18 0x0000_0000 GPIOB_DOUT GPIO Port B Data Output Value GP_BA+0x28 0x0000_0000 GPIOC_DOUT GPIO Port C Data Output Value GP_BA+0x38 0x0000_0000 GPIOD_DOUT...
Page 771 N9H26 Technical Reference Manual GPIO Port [X] Pin Value (GPIOX _PIN) Register Address Description Reset Value GP_BA+0x0C 0x0000_XXXX GPIOA_PIN GPIO Port A Pin Value GP_BA+0x1C 0x0000_XXXX GPIOB_PIN GPIO Port B Pin Value GP_BA+0x2C 0x0000_XXXX GPIOC_PIN GPIO Port C Pin Value GP_BA+0x3C 0x0000_XXXX GPIOD_PIN...
Page 772 N9H26 Technical Reference Manual Interrupt De-bounce Control (DBNCECON) Register Address Description Reset Value GP_BA+0x70 0x0000_0000 DBNCECON External Interrupt De-bounce Control Reserved Reserved Reserved DBCLKSEL DBEN Bits Descriptions Default Debounce sampling cycle selection DBCLKSEL Description Sample interrupt input once per 1 clocks Sample interrupt input once per 2 clocks Sample interrupt input once per 4 clocks Sample interrupt input once per 8 clocks...
Page 773 N9H26 Technical Reference Manual Bits Descriptions Default 0 = Interrupt input IRQx is input directly without de-bounce sampling Publication Release Date: Sept. 10, 2018 - 773 - Revision V1.01...
Page 774 N9H26 Technical Reference Manual IRQ Source Grouping (IRQSRCGPA) Register Address Description Reset Value IRQSRCGPA GP_BA+0x80 0x0000_0000 GPIO Port A IRQ Source Grouping GPA15SEL GPA14SEL GPA13SEL GPA12SEL GPA11SEL GPA10SEL GPA9SEL GPA8SEL GPA7SEL GPA6SEL GPA5SEL GPA4SEL GPA3SEL GPA2SEL GPA1SEL GPA0SEL Bits Descriptions Default Selection for GPAx as one of input Pins to IRQ0, IRQ1, IRQ2, or IRQ3 interrupt [2x+1:2x]...
Page 775 N9H26 Technical Reference Manual IRQ Source Grouping (IRQSRCGPB) Register Address Description Reset Value GP_BA+0x84 0x0000_0000 IRQSRCGPB GPIO Port B IRQ Source Grouping GPB15SEL GPB14SEL GPB13SEL GPB12SEL GPB11SEL GPB10SEL GPB9SEL GPB8SEL GPB7SEL GPB6SEL GPB5SEL GPB4SEL GPB3SEL GPB2SEL GPB1SEL GPB0SEL Bits Descriptions Default Selection for GPBx as one of input Pins to IRQ0, IRQ1, IRQ2, or IRQ3 interrupt [2x+1:2x]...
Page 776 N9H26 Technical Reference Manual IRQ Source Grouping (IRQSRCGPC) Register Address Description Reset Value IRQSRCGPC GP_BA+0x88 0x0000_0000 GPIO Port C IRQ Source Grouping GPC15SEL GPC14SEL GPC13SEL GPC12SEL GPC11SEL GPC10SEL GPC9SEL GPC8SEL GPC7SEL GPC6SEL GPC5SEL GPC4SEL GPC3SEL GPC2SEL GPC1SEL GPC0SEL Bits Descriptions Default Selection for GPCx as one of input Pins to IRQ0, IRQ1, IRQ2, or IRQ3 interrupt [2x+1:2x]...
Page 777 N9H26 Technical Reference Manual IRQ Source Grouping (IRQSRCGPD) Register Address Description Reset Value IRQSRCGPD GP_BA+0x8C 0x0000_0000 GPIO Port D IRQ Source Grouping GPD15SEL GPD14SEL GPD13SEL GPD12SEL GPD11SEL GPD10SEL GPD9SEL GPD8SEL GPD7SEL GPD6SEL GPD5SEL GPD4SEL GPD3SEL GPD2SEL GPD1SEL GPD0SEL Bits Descriptions Default Selection for GPDx as one of input Pins to IRQ0, IRQ1, IRQ2, or IRQ3 interrupt [2x+1:2x]...
Page 778 N9H26 Technical Reference Manual IRQ Source Grouping (IRQSRCGPE) Register Address Description Reset Value GP_BA+0x90 0x0000_0000 IRQSRCGPE GPIO Port E IRQ Source Grouping GPE15SEL GPE14SEL GPE13SEL GPE12SEL GPE11SEL GPE10SEL GPE9SEL GPE8SEL GPE7SEL GPE6SEL GPE5SEL GPE4SEL GPE3SEL GPE2SEL GPE1SEL GPE0SEL Descriptions Default Bits Selection for GPEx as one of input Pins to IRQ0, IRQ1, IRQ2, or IRQ3 interrupt [2x+1:2x]...
Page 779 N9H26 Technical Reference Manual IRQ Source Grouping (IRQSRCGPG) Register Address Description Reset Value GP_BA+0x94 0x0000_0000 IRQSRCGPG GPIO Port G IRQ Source Grouping GPG15SEL GPG14SEL GPG13SEL GPG12SEL GPG11SEL GPG10SEL GPG9SEL GPG8SEL GPG7SEL GPG6SEL GPG5SEL GPG4SEL GPG3SEL GPG2SEL GPG1SEL GPG0SEL Bits Descriptions Default Selection for GPGx as one of input Pins to IRQ0, IRQ1, IRQ2, or IRQ3 interrupt [2x+1:2x]...
Page 780 N9H26 Technical Reference Manual IRQ Source Grouping (IRQSRCGPG) Register Address Description Reset Value GP_BA+0x98 0x0000_0000 IRQSRCGPH GPIO Port H IRQ Source Grouping GPH15SEL GPH14SEL GPH13SEL GPH12SEL GPH11SEL GPH10SEL GPH9SEL GPH8SEL GPH7SEL GPH6SEL GPH5SEL GPH4SEL GPH3SEL GPH2SEL GPH1SEL GPH0SEL Bits Descriptions Default Selection for GPHx as one of input Pins to IRQ0, IRQ1, IRQ2, or IRQ3 interrupt [2x+1:2x]...
Page 781 N9H26 Technical Reference Manual GPIO A Interrupt Enable (IRQENGPA) Register Address Description Reset Value GP_BA+0xA0 0x0000_0000 IRQENGPA GPIO Port A Interrupt Enable PA15ENR PA14ENR PA13ENR PA12ENR PA11ENR PA10ENR PA9ENR PA8ENR PA7ENR PA6ENR PA5ENR PA4ENR PA3ENR PA2ENR PA1ENR PA0ENR PA15ENF PA14ENF PA13ENF PA12ENF PA11ENF...
Page 782 N9H26 Technical Reference Manual GPIO B Interrupt Enable (IRQENGPB) Register Address Description Reset Value GP_BA+0xA4 0x0000_0000 IRQENGPB GPIO Port B Interrupt Enable PB15ENR PB14ENR PB13ENR PB12ENR PB11ENR PB10ENR PB9ENR PB8ENR PB7ENR PB6ENR PB5ENR PB4ENR PB3ENR PB2ENR PB1ENR PB0ENR PB15ENF PB14ENF PB13ENF PB12ENF PB11ENF...
Page 783 N9H26 Technical Reference Manual GPIO C Interrupt Enable (IRQENGPC) Register Address Description Reset Value GP_BA+0xA8 0x0000_0000 IRQENGPC GPIO Port C Interrupt Enable PC15ENR PC14ENR PC13ENR PC12ENR PC11ENR PC10ENR PC9ENR PC8ENR PC7ENR PC6ENR PC5ENR PC4ENR PC3ENR PC2ENR PC1ENR PC0ENR PC15ENF PC14ENF PC13ENF PC12ENF PC11ENF...
Page 784 N9H26 Technical Reference Manual GPIO D Interrupt Enable (IRQENGPD) Register Address Description Reset Value GP_BA+0xAC 0x0000_0000 IRQENGPD GPIO Port D Interrupt Enable PD15ENR PD14ENR PD13ENR PD12ENR PD11ENR PD10ENR PD9ENR PD8ENR PD7ENR PD6ENR PD5ENR PD4ENR PD3ENR PD2ENR PD1ENR PD0ENR PD15ENF PD14ENF PD13ENF PD12ENF PD11ENF...
Page 785 N9H26 Technical Reference Manual GPIO E Interrupt Enable (IRQENGPE) Register Address Description Reset Value GP_BA+0xB0 0x0000_0000 IRQENGPE GPIO Port E Interrupt Enable PE15ENR PE14ENR PE13ENR PE12ENR PE11ENR PE10ENR PE9ENR PE8ENR PE7ENR PE6ENR PE5ENR PE4ENR PE3ENR PE2ENR PE1ENR PE0ENR PE15ENF PE14ENF PE13ENF PE12ENF PE11ENF...
Page 786 N9H26 Technical Reference Manual GPIO G Interrupt Enable (IRQENGPE) Register Address Description Reset Value GP_BA+0xB4 0x0000_0000 IRQENGPG GPIO Port G Interrupt Enable PG15ENR PG14ENR PG13ENR PG12ENR PG11ENR PG10ENR PG9ENR PG8ENR PG7ENR PG6ENR PG5ENR PG4ENR PG3ENR PG2ENR PG1ENR PG0ENR PG15ENF PG14ENF PG13ENF PG12ENF PG11ENF...
Page 787 N9H26 Technical Reference Manual GPIO H Interrupt Enable (IRQENGPE) Register Address Description Reset Value GP_BA+0xB4 0x0000_0000 IRQENGPH GPIO Port H Interrupt Enable PH15ENR PH14ENR PH13ENR PH12ENR PH11ENR PH10ENR PH9ENR PH8ENR PH7ENR PH6ENR PH5ENR PH4ENR PH3ENR PH2ENR PH1ENR PH0ENR PH15ENF PH14ENF PH13ENF PH12ENF PH11ENF...
Page 788 N9H26 Technical Reference Manual Interrupt Latch Trigger Selection (IRQLHSEL) Register Address Description Reset Value GP_BA+0xC0 0x0000_0000 IRQLHSEL Interrupt Latch Trigger Selection Register Reserved Reserved Reserved IRQ3Wake IRQ2Wake IRQ1Wake IRQ0Wake IRQ3LHE IRQ2LHE IRQ1LHE IRQ0LHE Bits Descriptions Default GPIO interrupt wake up system enable [7:4] IRQxWake While IRQxWake is “1”, enable the GPIO IRQx wake up the chip from power down...
Page 789 N9H26 Technical Reference Manual GPIO X Interrupt Latch (IRQLHGPX) Register Address Description Reset Value GP_BA+0xD0 0x0000_0000 IRQLHGPA GPIO Port A Interrupt Latch Value GP_BA+0xD4 0x0000_0000 IRQLHGPB GPIO Port B Interrupt Latch Value GP_BA+0xD8 0x0000_0000 IRQLHGPC GPIO Port C Interrupt Latch Value GP_BA+0xDC 0x0000_0000 IRQLHGPD...
Page 790 N9H26 Technical Reference Manual IRQ Interrupt Trigger Source 0 (IRQTGSRC0) Register Address Description Reset Value IRQ0~3 Interrupt Trigger Source Indicator from GP_BA+0xF0 0x0000_0000 IRQTGSRC0 GPIO Port A and GPIO Port B PB15TG PB14TG PB13TG PB12TG PB11TG PB10TG PB9TG PB8TG PB7TG PB6TG PB5TG PB4TG...
Page 791 N9H26 Technical Reference Manual IRQ Interrupt Trigger Source 1 (IRQTGSRC1) Register Address Description Reset Value IRQ0~3 Interrupt Trigger Source Indicator from GPIO Port GP_BA+0xF4 0x0000_0000 IRQTGSRC1 C and GPIO Port D PD15TG PD14TG PD13TG PD12TG PD11TG PD10TG PD9TG PD8TG PD7TG PD6TG PD5TG PD4TG...
Page 792 N9H26 Technical Reference Manual IRQ Interrupt Trigger Source 2 (IRQTGSRC2) Register Address Description Reset Value IRQ0~3 Interrupt Trigger Source Indicator from GPIO Port GP_BA+0xF8 0x0000_0000 IRQTGSRC2 and GPIO Port G PG15TG PG14TG PG13TG PG12TG PG11TG PG10TG PG9TG PG8TG PG7TG PG6TG PG5TG PG4TG PG3TG...
Page 793 N9H26 Technical Reference Manual IRQ Interrupt Trigger Source 3 (IRQTGSRC3) Register Address Description Reset Value IRQ0~3 Interrupt Trigger Source Indicator from GPIO Port GP_BA+0xFC 0x0000_0000 IRQTGSRC3 Reserved Reserved PH15TG PH14TG PH13TG PH12TG PH11TG PH10TG PH9TG PH8TG PH7TG PH6TG PH5TG PH4TG PH3TG PH2TG PH1TG...
Page 794: Timer Controller
N9H26 Technical Reference Manual 5.19 TIMER Controller 5.19.1 Overview The timer module includes four channels, TIMER0~TIMER3, which allow you to easily implement a counting scheme for use. The timer can perform functions like frequency measurement, event counting, interval measurement, clock generation, delay timing, and so on. The timer possesses features such as adjustable resolution, programmable counting period, and detailed information.
Page 795: Figure 5.19-2 Watchdog Timer Block Diagram
N9H26 Technical Reference Manual generated. If the Watchdog Timer reset function is enabled and the Watchdog Timer is not being reset before timing out, then the Watchdog Timer reset is activated after 1024 WDT clock cycles (Interrupt timeout). Setting WTE in the register WTCR enables the Watchdog Timer. The WTR should be set before making use of Watchdog Timer.
Page 796: Figure 5.19-3 Watchdog Timer Timing Diagram
N9H26 Technical Reference Manual Figure 5.19-3 Watchdog Timer Timing Diagram Publication Release Date: Sept. 10, 2018 - 796 - Revision V1.01...
Page 797: Timer Control Registers Map
N9H26 Technical Reference Manual 5.19.4 Timer Control Registers Map R: read only, W: write only, R/W: both read and write TMR_BA = 0xB800_2000 Register Address R/W/C Description Reset Value TMR_BA = 0xB8002000 TCSR0 TMR_BA+00 Timer Control and Status Register 0 0x0000_0005 TCSR1 TMR_BA+04...
Page 798 N9H26 Technical Reference Manual Timer Control Register 0~3 (TCSR0~TCSR3) Register Address Description Reset Value TCSR0 TMR_BA+000 Timer Control and Status Register 0 0x0000_0005 TCSR1 TMR_BA+004 Timer Control and Status Register 1 0x0000_0005 TCSR2 TMR2_BA+000 Timer2 Control and Status Register 0 0x0000_0005 TCSR3 TMR2_BA+004...
Page 799 N9H26 Technical Reference Manual Bits Descriptions The timer is operating in the uninterrupted mode. The associated interrupt signal is generated when TDR = TICR (if IE is enabled) . Counter Reset Set this bit will reset the TIMER counter, and also force CEN to 0. [26] CRST 0 = No effect.
Page 800 N9H26 Technical Reference Manual Timer Initial Count Register 0~3 (TICR0~TICR3) Register Address Description Reset Value TICR0 TMR_BA+008 Timer Initial Control Register 0 0x0000_0000 TICR1 TMR_BA+00C Timer Initial Control Register 1 0x0000_0000 TICR2 TMR2_BA+008 Timer2 Initial Control Register 0 0x0000_0000 TICR3 TMR2_BA+00C Timer2 Initial Control Register 1 0x0000_0000...
Page 801 N9H26 Technical Reference Manual Timer Data Register 0~3 (TDR0~TDR3) Register Address Description Reset Value TDR0 TMR_BA+10 Timer Data Register 0 0x0000_0000 TDR1 TMR_BA+14 Timer Data Register 1 0x0000_0000 TDR2 TMR2_BA+10 Timer2 Data Register 0 0x0000_0000 TDR3 TMR2_BA+14 Timer2 Data Register 1 0x0000_0000 TDR[31:24] TDR [23:16]...
Page 802 N9H26 Technical Reference Manual Timer Interrupt Status Register (TISR) Register Address Description Reset Value TISR TMR_BA+18 Timer Interrupt Status Register 0x0000_0000 TISR2 TMR2_BA+18 Timer2 Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved TIF1 TIF0 Bits Descriptions Timer Interrupt Flag 1 This bit indicates the interrupt status of Timer channel 1.
Page 803 N9H26 Technical Reference Manual Watchdog Timer Control Register (WTCR) Register Address Description Reset Value WTCR TMR_BA+01C Watchdog Timer Control Register 0x0000_0400 Reserved Reserved Reserved WTCLK nDBGACK_EN WTTME WTIE WTIS WTIF WTRF WTRE Bits Descriptions [31:11] Reserved Reserved Watchdog Timer Clock This bit is used for deciding whether the Watchdog timer clock input is divided by 256 or not.
Page 804 N9H26 Technical Reference Manual Bits Descriptions WTIS Timeout Interrupt Timeout Real Time Interval (CLK=15MHz/256) clocks + 1024 clocks 0.28 sec. clocks + 1024 clocks 1.12 sec. clocks + 1024 clocks 4.47 sec. clocks + 1024 clocks 17.9 sec. Note : Reference the Figure3 Watchdog Timer Timing Diagram Watchdog Timer Interrupt Flag If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred.
Page 805: Real Time Clock (Rtc)
N9H26 Technical Reference Manual 5.20 Real Time Clock (RTC) 5.20.1 Overview Real Time Clock (RTC) block can be operated by independent power supply while the system power is off. The RTC uses a 32.768 KHz external crystal or internal oscillator. It can transmit data to CPU with BCD values.
Page 806: Rtc Block Diagram
N9H26 Technical Reference Manual 5.20.3 RTC Block Diagram The block diagram of Real Time Clock is depicted as following: Interrupt A IC Wakeup Clock Contro WAKEUPN PWRSWN VBAT RTC_TOP Note: PWRSWN = 1, all system turn on. Note: WAKEUPN pin, this pin is within RTC parts. 5.20.4 RTC Function Description 5.20.4.1 RTC Initiation When RTC block is power on, programmer has to write a number (0xa5eb1357) to INIR to reset all...
Page 807 N9H26 Technical Reference Manual 5.20.4.6 Day of the week counter Count from Sunday to Saturday. 5.20.4.7 Time tick interrupt RTC block use a counter to calibrate the time tick count value. When the value in counter reaches zero, RTC will issue an interrupt. 5.20.4.8 RTC register property When system power is off but RTC power is on, data stored in RTC registers will not lost except RIER and RIIR.
Page 808: System Power Control Flow
N9H26 Technical Reference Manual FCR_Frac = 0.5505*60-1=32 2. In TLR and TAR, only 2 BCD digits are used to express “year”. We assume 2 BCD digits of xY denote 20xY, but not 19xY or 21xY. 5.20.5 System Power Control Flow 5.20.5.1 Normal system Power Control Flow The state machine of power On/Off Control Publication Release Date: Sept.
Page 809 N9H26 Technical Reference Manual Power_Key_Deglitch Glitch Valid key State Power_Off released Key pressed Key_Duration_Check Key is pressed during Alarm_Off and Key is pressed during released Power_Off and released Key is preesing Alarm counter matched Key length Counter not expired Key length Counter expired and Level trigger Key length Counter expired and edge trigger...
Page 810 N9H26 Technical Reference Manual 5.20.5.2 Force system Power Off Control Flow The RTC supports a hardware automatic power off function and a software power off function like Notebook. For hardware power off function, it can be enable and disable in HW_PCLR_EN bit and the user presses the power button for a few seconds to power off system.
Page 811 N9H26 Technical Reference Manual Enable SW Power Off Power Off Press PWRKey Release PWRKey Time 86.8 µ s 116 µ s PWCE PWR_ON SW_PCLR Publication Release Date: Sept. 10, 2018 - 811 - Revision V1.01...
Page 812: Rtc Register Mapping
N9H26 Technical Reference Manual 5.20.6 RTC Register Mapping Register Address Description Reset Value RTC_BA = 0xB800_3000 INIR RTC_BA+0x000 RTC Initiation Register 0x0000_0000 RTC_BA+0x004 RTC Access Enable Register 0x0000_0000 RTC_BA+0x008 RTC Frequency Compensation Register 0x007F_FF00 RTC_BA+0x00C Time Loading Register 0x0000_0000 RTC_BA+0x010 Calendar Loading Register 0x0005_0101 TSSR...
Page 813: Register Descriptions
N9H26 Technical Reference Manual 5.20.7 Register Descriptions RTC Initiation Register (INIR) Register Address R/W/C Description Reset Value INIR RTC_BA+0x000 RTC Initiation Register 0x0000_0000 INIR/RTC_Internal_Status INIR INIR INIR INIR/Active Bits Descriptions RTC Initiation (While Writing) [31:0] INIR When RTC block is power on, RTC is at reset state; programmer has to write a number (0x a5eb1357) to INIR to release all of logic and counters.
Page 814 N9H26 Technical Reference Manual RTC Access Enable Register (AER) Register Address R/W/C Description Reset Value RTC_BA+0x004 RTC Access Enable Register 0x0000_0000 Reserved Reserved Bits Descriptions RTC Register Access Enable Flag (Read only) 1: RTC register read/write enable [16] 0: RTC register read/write disable This bit will be set after AER[15:0] register is load a 0xA965, and be clear in AER[15:0] is not 0xA965.
Page 815 N9H26 Technical Reference Manual RTC Frequency Compensation Register (FCR) Register Address R/W/C Description Reset Value RTC_BA+0x008 Frequency Compensation Register 0x007F_FF00 FC_EN Reserved Reserved Reserved POWER_KEY_DURATION INTEGER[15:8] INTEGER[7:0] Reserved FRACTION Bits Descriptions 1: Trigger RTC clock calibration mechanism 0: Clock calibration mechanism is off This bit will be kept at “high”...
Page 816 N9H26 Technical Reference Manual RTC Time Loading Register (TLR) Register Address R/W/C Description Reset Value RTC_BA+0x00C Time Loading Register 0x0000_0000 Reserved Reserved 10HR Reserved 10MIN 1MIN Reserved 10SEC 1SEC Bits Descriptions [21:20] 10HR 10 Hour Time Digit [19:16] 1 Hour Time Digit [14:12] 10MIN 10 Min Time Digit...
Page 817 N9H26 Technical Reference Manual RTC Calendar Loading Register (CLR) Register Address R/W/C Description Reset Value RTC_BA+0x010 Calendar Loading Register 0x0005_0101 Reserved 10YEAR 1YEAR Reserved 10MON 1MON Reserved 10DAY 1DAY Bits Descriptions [23:20] 10YEAR 10-Year Calendar Digit [19:16] 1YEAR 1-Year Calendar Digit [12] 10MON 10-Month Calendar Digit...
Page 818 N9H26 Technical Reference Manual RTC Time Scale Selection Register (TSSR) Register Address R/W/C Description Reset Value TSSR RTC_BA+0x014 Time Scale Selection Register 0x0000_0001 Reserved Reserved Reserved Reserved 24hr/12hr Bits Descriptions 24-Hour / 12-Hour Mode Selection It indicate that TLR and TAR are in 24-hour mode or 12-hour mode 1: select 24-hour time scale 0: select 12-hour time scale with AM and PM indication 24-hour time scale...
Page 819 N9H26 Technical Reference Manual RTC Day of the Week Register (DWR) Register Address R/W/C Description Reset Value RTC_BA+0x018 Day of the Week Register 0x0000_0006 Reserved Reserved Reserved Reserved Bits Descriptions Day of the Week Register Sunday Monday Tuesday [2:0] Wednesday Thursday Friday Saturday...
Page 820 N9H26 Technical Reference Manual RTC Time Alarm Register (TAR) Register Address R/W/C Description Reset Value RTC_BA+0x01C Time Alarm Register 0x0000_0000 Reserved RTC_Mask_HR_Alarm 10HR Mask_Min_Ala 10MIN 1MIN Mask_Sec_Ala 10SEC 1SEC Bits Descriptions Mask alarm by hour [23] Mask_HR_Alarm 1: Mask 0: Activate [21:20] 10HR 10 Hour Time Digit...
Page 821 N9H26 Technical Reference Manual RTC Calendar Alarm Register (CAR) Register Address R/W/C Description Reset Value RTC_BA+0x020 Calendar Alarm Register 0x0000_0000 30:28 27:25 Mask_WD_Alarm Week Day Reserved Mask_Yr_Alarm 10YEAR 1YEAR Mask_Mon_Alarm 10MON 1MON Mask_Day_Alarm 10DAY 1DAY Bits Descriptions Mask alarm by week day [31] Mask_WD_Alarm_ 1:Mask...
Page 822 N9H26 Technical Reference Manual 1. CAR is a BCD digit counter and RTC will not check loaded data. 2. This register can be read back after the RTC access enable (AER) is active 3. Alarm will be disabled automatically while all alarm bits of CAR and TAR are masked Publication Release Date: Sept.
Page 823 N9H26 Technical Reference Manual RTC Leap Year Indication Register (LIR) Register Address R/W/C Description Reset Value RTC_BA+0x024 RTC Leap year Indication Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Descriptions Leap Year Indication REGISTER (Real only). 1 : It indicate that this year is leap year 0 : It indicate that this year is not a leap year Publication Release Date: Sept.
Page 824 N9H26 Technical Reference Manual RTC Interrupt Enable Register (RIER) Register Address R/W/C Description Reset Value RIER RTC_BA+0x028 RTC Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved RAIER PSWIER TIER AIER Bits Descriptions Relative Alarm Interrupt Enable RAIER 1 => RTC Relative Alarm Interrupt enable 0 =>...
Page 825 N9H26 Technical Reference Manual RTC Interrupt Indication Register (RIIR) Register Address R/W/C Description Reset Value RIIR RTC_BA+0x02C RTC Interrupt Indication Register 0x0000_0000 Reserved Reserved Reserved Reserved PSWI Bits Descriptions RTC Relative Alarm Interrupt Indication 1: It indicates that Relative time counter and calendar counter have counted to a specified time recorded in TAR and CAR.
Page 826 N9H26 Technical Reference Manual RTC Time Tick Register (TTR) Register Address R/W/C Description Reset Value RTC_BA+0x030 RTC Time Tick Register 0x0000_0000 Reserved Reserved Reserved Reserved TTR[2:0] Bits Descriptions Time Tick Register The RTC time tick is used for interrupt request. TTR[2:0] Time tick (second) [2:0]...
Page 827 N9H26 Technical Reference Manual RTC Power Time Out Register (PWRON) Register Address R/W/C Description Reset Value PWRON RTC_BA+0x034 RTC Power Time On Register 0x0005_0000 RELATIVE_TIME[11:0] RELATIVE_TIME[11:0] PCLR_TIME[3:0] SW_STATUS[7:0] PWR_KEY Reserved EDGE_TRIG REL_ALARM_ ALARM_EN HW_PCLR_E SW_PCLR PWR_ON Bits Descriptions Relative Time alarm period (second unit) The PCLR_TIME indicate the period of the relative time alarm, its maximum values [31:20] RELATIVE_TIME...
Page 828 N9H26 Technical Reference Manual Bits Descriptions Hardware Power Clear Enable 1: If this bit is set to 1, the RPWR pin will clear to low when the power key is pressed over HW_PCLR_EN the PCLR_TIME second 0: If this bit is set to 0, the RPWR pin won’t be influenced by the pressed time of power key. Software Core Power Disable If the power key is pressed, the RPWR pin can be clear by setting this bit and this can be cleared to 0 when the pressed power key, RPWR is released.
Page 829 N9H26 Technical Reference Manual RTC Setting Register (RTC_SET) Register Address R/W/C Description Reset Value RTC_SET RTC_BA+0x038 RTC Setting Register 0x0000_0000 Reserved Reserved Reserved Reserved XOUT_XC XIN_XC RTC_AEN RTC_EN RTC_WEAK Bits Descriptions [31:5] Reserved Reserved XOUT_XC XIN IO PAD input data(It is read only) XIN_XC XIN IO PAD input data (It is read only) RTC_AEN...
Page 830 N9H26 Technical Reference Manual RC Oscillator Setting Register (OSC_32K) Register Address R/W/C Description Reset Value OSC_32K RTC_BA+0x03C RC oscillator setting Register 0x0000_0000 Reserved Reserved Reserved Reserved OSC_32K_EN Bits Descriptions [31:1] Reserved Reserved OSC_32K_EN OSC_32K_EN 1: If this bit is set to 1, enable internal RC oscillator 0: If this bit is set to 0, disable internal RC oscillator Publication Release Date: Sept.
Page 831 N9H26 Technical Reference Manual RTC 1Hz Counter Register (RTC_1Hz_CNT) Register Address R/W/C Description Reset Value RTC_1Hz_CNT RTC_BA+0x040 RTC clock calibration counter register 0x0000_0000 RTC_1Hz_CNT[31:24] RTC_1Hz_CNT[23:16] RTC_1Hz_CNT[15:8] RTC_1Hz_CNT[7:0] Bits Descriptions The cycle number of PCLK during 1Hz period that is generated by dividing RTC clock by [31:0] RTC_1Hz_CNT 32768.
Page 832 N9H26 Technical Reference Manual RTC Register Complete Register (REG_FLAG) Register Address R/W/C Description Reset Value REG_FLAG RTC_BA+0x044 RTC Register write complete 0x0000_0000 Reserved Reserved Reserved Reserved REG_FLAG Bits Descriptions [31:1] Reserved Reserved Polling the flag to detect RTC register write complete REG_FLAG 0: cannot write 1: write complete...
Page 833 N9H26 Technical Reference Manual RTC Register Complete Register (RTC) Register Address R/W/C Description Reset Value PORCTRL RTC_BA+0x050 RTC POR Control Register 0x0028_8001 [30:16] POR_Auto_CTRL_En POR_Sample_CNT [14:0] POR_EN_Manual POR_Active_Cnt Bits Descriptions 1: Automatic control of POR is enabled [31] POR_Auto_CTRL_En 0: POR control was controlled by CPU Sampling period of POR On/Off Control [30:16] POR_Sample_Cnt...
Page 834 N9H26 Technical Reference Manual RTC DUMMY Register 0 Register Address R/W/C Description Reset Value DUMMY0 RTC_BA+0x054 RTC Dummy Register 0 Publication Release Date: Sept. 10, 2018 - 834 - Revision V1.01...
Page 835 N9H26 Technical Reference Manual RTC DUMMY Register 1 Register Address R/W/C Description Reset Value DUMMY1 RTC_BA+0x058 RTC Dummy Register 1 Publication Release Date: Sept. 10, 2018 - 835 - Revision V1.01...
Page 836: I2C Synchronous Serial Interface Controller
N9H26 Technical Reference Manual 5.21 I2C Synchronous Serial Interface Controller 5.21.1 Overview C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The I C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously.
Page 837: I2C Serial Interface Block Diagram
N9H26 Technical Reference Manual 5.21.3 I2C Serial Interface Block Diagram The block diagram of I C Serial Interface controller is shown as following. Clock Control Interrupt scl_padoen_o sda_padoen_o sdo_padoen_o Clock I/O Decoder Core scl_pad_i Pre-scale Registers Logic sda_pad_i sdo_pad_i Figure 5.21-1 I C Block Diagram NOTE1: scl_pad_o, sda_pad_o and sdo_pad_o are always tied to 1’b0.
Page 838: I2C Protocol
N9H26 Technical Reference Manual 5.21.4 I2C Protocol Normally, a standard communication consists of four parts:  START or Repeated START signal generation  Slave address transfer  Data transfer  STOP signal generation 3 - 7 NACK A4 - A1 D5 - D1 Figure 5.21-2 Data transfer on the I C-bus...
Page 839: Stop Signal
N9H26 Technical Reference Manual or Repeated START is generated. 5.21.5 STOP signal The master can terminate the communication by generating a STOP signal. A STOP signal, usually referred to as the P-bit, is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH.
Page 840: I2C Programming Examples
N9H26 Technical Reference Manual I2C_TIP flag is cleared. data line change stable; of data data valid allowed Figure 5.21-6 Bit transfer on the I C-bus clock pulse for acknowledgement SCL FROM MASTER DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge START...
Page 841 N9H26 Technical Reference Manual 4. write data 5. receive acknowledge from slave 6. generate stop command 7. Commands: 8. Write a value into DIVIDER to determine the frequency of serial clock. 9. Set Tx_NUM = 0x1 and set I2C_EN = 1 to enable I C core.
Page 842: Software I2C Operation
N9H26 Technical Reference Manual 3. Write 0x9C (address + write bit) to TxR[7:0], set START bit and WRITE bit. –– Wait for interrupt or I2C_TIP flag to negate –– 4. Read I2C_RxACK bit from CSR Register, it should be ‘0’. 5.
Page 843 N9H26 Technical Reference Manual The other three registers – SCR, SDR and SER just represent the status of input port - scl_pad_i, sda_pad_i and sdo_pad_i. Software can read/write this register at any time, but the output enable – scl_padoen_o and sda_padoen_o are controlled by software only when I2C_EN = 0.
Page 844: I2C Serial Interface Control Registers Map
N9H26 Technical Reference Manual 5.21.8 I2C Serial Interface Control Registers Map R: read only, W: write only, R/W: both read and write Register Offset R/W/C Description Reset Value I2C_BA = 0xB800_4000 I2C_BA+0x00 Control and Status Register 0x0000_0000 DIVIDER I2C_BA+0x04 Clock Prescale Register 0x0000_0000 CMDR I2C_BA+0x08...
Page 845: Control And Status Register (Csr)
N9H26 Technical Reference Manual Control and Status Register (CSR) Register Offset R/W/C Description Reset Value 0x00 Control and Status Register 0x0000_0000 Reserved Reserved Reserved I2C_RxACK I2C_BUSY I2C_AL I2C_TIP Reserved TX_NUM SGMST_EN I2C_EN Bits Descriptions [31:12] Reserved Reserved Received Acknowledge From Slave (Read only) This flag represents acknowledge from the addressed slave.
Page 846 N9H26 Technical Reference Manual Bits Descriptions 0x3 = Four bytes are left for transmission. NOTE: When NACK received, TX_NUM will not decrease. Single master mode enable SGMST_EN 0 = Multiple master mode. (using Sync. and Async. logic to detect START and STOP) 1 = Single master mode.
Page 847 N9H26 Technical Reference Manual Prescale Register (DIVIDER) Register Offset R/W/C Description Reset Value DIVIDER 0x04 Clock Prescale Register 0x0000_0000 Reserved Reserved DIVIDER[15:8] DIVIDER[7:0] Bits Descriptions Clock Prescale Register It is used to prescale the SCL clock line. Due to the structure of the I C interface, the core uses a 5*SCL clock internally.
Page 848 N9H26 Technical Reference Manual Command Register (CMDR) Register Offset R/W/C Description Reset Value CMDR 0x08 Command Register 0x0000_000x Reserved Reserved Reserved Reserved Reserved Reserved START STOP READ WRITE NOTE: Software can write this register only when I2C_EN = 1. Bits Descriptions [31:5] Reserved...
Page 849 N9H26 Technical Reference Manual Software Mode Register (SWR) Register Offset R/W/C Description Reset Value 0x0C Software Mode Control Register 0x0000_003F Reserved Reserved Reserved Reserved NOTE: This register is used as software mode of I C. Software can read/write this register no matter I2C_EN is 0 or 1. But SCL and SDA are controlled by software only when I2C_EN = 0.
Page 850 N9H26 Technical Reference Manual Data Receive Register (RXR) Register Offset R/W/C Description Reset Value 0x10 Data Receive Register 0x0000_0000 Reserved Reserved Reserved RX [7:0] Bits Descriptions [31:8] Reserved Reserved Data Receive Register [7:0] The last byte received via I C bus will put on this register. The I C core only used 8-bit receive buffer.
Page 851 N9H26 Technical Reference Manual Data Transmit Register (TXR) Register Offset R/W/C Description Reset Value 0x14 Data Transmit Register 0x0000_0000 TX [31:24] TX [23:16] TX [15:8] TX [7:0] Bits Descriptions Data Transmit Register The I C core used 32-bit transmit buffer and provide multi-byte transmit function. Set CSR[Tx_NUM] to a value that you want to transmit.
Page 852: Pwm-Timer
N9H26 Technical Reference Manual 5.22 PWM-Timer 5.22.1 Introduction There are 4 PWM-Timers. The 4 PWM-Timers has 2 Pre-scale, 2 clock divider, 4 clock selectors, 4 16-bit counters, 4 16-bit comparators, 2 Dead-Zone generators. They are all driven by Crystal or system clock.
Page 853: Pwm Architecture
N9H26 Technical Reference Manual 5.22.2.1 PWM Timer Start Procedure 1. Setup clock selector (CSR) 2. Setup pre-scale & dead zone interval (PPR) 3. Setup inverter on/off, dead zone generator on/off, toggle mode /one-shot mode, and PWM timer off. (PCR) 4. Setup comparator register (CMR) 5.
Page 854: Basic Timer Operation
N9H26 Technical Reference Manual DZI1 Dead Zone Generator pwm_clk1 Dead Zone CNR2 CMR2 PWM2 Control Logic 8-bit ½ Dead Zone Pre-scale ¼ CNR3 CMR3 PWM3 1/16 Control Logic 5.22.4 Basic Timer Operation Basic Timer operation Counter Timer output CMP : 1 CMP : 0 CNR : 3 CNR : 3...
Page 855: Pwm Double Buffering And Automatic Reload
N9H26 Technical Reference Manual 5.22.5 PWM Double Buffering and Automatic Reload PWM-Timers have a double buffering function, enabling the reload value changed for next timer operation without stopping current timer operation. Although new timer value is set, current timer operation still operate successfully. The counter value can be written into CNR0~3 and current counter value can be read from PDR0~3.
Page 856: Modulate Duty Ratio
N9H26 Technical Reference Manual 5.22.6 Modulate Duty Ratio The double buffering function allows CMR written at any point in current cycle. The loaded value will take effect from next cycle. Modulate PWM controller ouput duty ratio(CNR = 150) Write Write Write CMR=100 CMR=50...
Page 857: Dead-Zone Generator
N9H26 Technical Reference Manual 5.22.7 Dead-Zone Generator PWM is implemented with Dead Zone generator. They are built for power device protection. This function enables generation of a programmable time gap at the rising of PWM output waveform. User can program PPR [31:24] and PPR [23:16] to determine the two Dead Zone interval respectively. Dead zone generator operation PWM_out1 PWM_out1_n...
Page 858: Pwm Timer Stop Procedure
N9H26 Technical Reference Manual 5.22.9 PWM Timer Stop Procedure Method 1: Set 16-bit down counter (CNR) as 0, and monitor PDR. When PDR reaches to 0, disable PWM timer (PCR). (Recommended) Method 2: Set 16-bit down counter (CNR) as 0. When interrupt request happen, disable PWM timer (PCR). (Recommended) Method 3: Disable PWM timer directly (PCR).
Page 859: Register Map
N9H26 Technical Reference Manual 5.22.10 Register Map R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written Register Address Description Reset Value PWM_BA = 0xB800_7000 PWM_BA+0x000 PWM Pre-scale Register 0x0000_0000 PWM_BA+0x004 PWM Clock Select Register 0x0000_0000 PWM_BA+0x008 PWM Control Register...
Page 860: Register Description
N9H26 Technical Reference Manual 5.22.11 Register Description PWM Pre-scale Register (PPR) Register Offset Description Reset Value PWM_BA+0x000 0x0000_0000 PWM Pre-scale Register DZI1 DZI0 Bits Descriptions Dead zone interval register 1 [31:24] DZI11 These 8-bit determine dead zone length. The 1 unit time of dead zone length is received from clock selector 1. Dead zone interval register 0 [23:16] DZI0...
Page 861 N9H26 Technical Reference Manual PWM Clock Selector Register (CSR) Register Offset Description Reset Value PWM_BA+0x004 0x0000_0000 PWM Clock Selector Register (CSR) Reserved Reserved Reserved CSR3 Reserved CSR2 Reserved CSR1 Reserved CSR0 Bits Descriptions [31:15] Reserved Reserved Timer 3 Clock Source Selection Select clock input for timer 3.
Page 862 N9H26 Technical Reference Manual PWM Control Register (PCR) Register Offset Description Reset Value PWM_BA+0x008 0x0000_0000 PWM Control Register (PCR) Reserved CH3MOD CH3INV Reserved CH3EN Reserved CH2MOD CH2INV Reserved CH2EN Reserved CH1MOD CH1INV Reserved CH1EN Reserved DZEN1 DZEN0 CH0MOD CH0INV Reserved CH0EN Bits Descriptions...
Page 863 N9H26 Technical Reference Manual Bits Descriptions 1: Enable 0: Disable [15:12] Reserved Reserved Timer 1 Toggle/One-Shot Mode 1: Toggle Mode [11] CH1MOD 0: One-Shot Mode NOTE: If there is a rising transition at this bit, it will cause CNR1 and CMR1 be clear. Timer 1 Inverter ON/OFF [10] CH1INV...
Page 864 N9H26 Technical Reference Manual PWM Counter Register 3-0 (CNR3-0) Register Offset Description Reset Value CNR0 PWM_BA+0x00C 0x0000_0000 PWM Counter Register 0 CNR1 PWM_BA+0x018 0x0000_0000 PWM Counter Register 1 CNR2 PWM_BA+0x024 0x0000_0000 PWM Counter Register 2 CNR3 PWM_BA+0x030 0x0000_0000 PWM Counter Register 3 Reserved Reserved CNR [15:8]...
Page 865 N9H26 Technical Reference Manual PWM Comparator Register 3-0 (CMR3-0) Register Offset Description Reset Value CMR0 PWM_BA+0x010 0x0000_0000 PWM Comparator Register 0 CMR1 PWM_BA+0x01C 0x0000_0000 PWM Comparator Register 1 CMR2 PWM_BA+0x028 0x0000_0000 PWM Comparator Register 2 CMR3 PWM_BA+0x034 0x0000_0000 PWM Comparator Register 3 Reserved Reserved CMR [15:8]...
Page 866 N9H26 Technical Reference Manual PWM Data Register 3-0 (PDR 3-0) Register Offset Description Reset Value PDR0 PWM_BA+0x014 0x0000_0000 PWM Data Register 0 PDR1 PWM_BA+0x020 0x0000_0000 PWM Data Register 1 PDR2 PWM_BA+0x02C 0x0000_0000 PWM Data Register 1 PDR3 PWM_BA+0x038 0x0000_0000 PWM Data Register 1 Reserved Reserved PDR [15:8]...
Page 867 N9H26 Technical Reference Manual PWM Interrupt Enable Register (PIER) Register Offset Description Reset Value PIER PWM_BA+0x040 0x0000_0000 PWM Interrupt Enable Register Reserved Reserved Reserved Reserved PIER3 PIER2 PIER1 PIER0 Bits Descriptions [31:4] Reserved Reserved PWM Timer 3 Interrupt Enable PIER3 1: Enable 0: Disable PWM Timer 2 Interrupt Enable...
Page 868 N9H26 Technical Reference Manual PWM Interrupt Indication Register (PIIR) Register Offset Description Reset Value PIIR PWM_BA+0x044 0x0000_0000 PWM Interrupt Indication Register Reserved Reserved Reserved Reserved PIIR3 PIIR2 PIIR1 PIIR0 Bits Descriptions [31:4] Reserved Reserved PWM Timer 3 Interrupt Flag PIIR3 1: Interrupt Flag ON 0: Interrupt Flag OFF PWM Timer 2 Interrupt Flag...
Page 869 N9H26 Technical Reference Manual Capture Control Register (CCR0) Register Offset Description Reset Value CCR0 PWM_BA+0x050 0x0000_0000 Capture Control Register Reserved CFLRD1 CRLRD1 Reserved CIIR1 CAPCH1EN FL&IE1 RL&IE1 INV1 Reserved CFLRD0 CRLRD0 Reserved CIIR0 CAPCH0EN FL&IE0 RL&IE0 INV0 Bits Descriptions [31:24] Reserved Reserved CFLR1 dirty bit...
Page 870 N9H26 Technical Reference Manual Bits Descriptions Interrupt. Channel 1 Rising Interrupt Enable ON/OFF 1: Enable [17] RL&IE1 0: Disable When Enable, if Capture detects Channel 1 has rising transition, Capture issues an Interrupt. Channel 1 Inverter ON/OFF [16] INV1 1: Inverter ON 0: Inverter OFF [15:8] Reserved...
Page 871 N9H26 Technical Reference Manual Publication Release Date: Sept. 10, 2018 - 871 - Revision V1.01...
Page 872 N9H26 Technical Reference Manual Capture Control Register (CCR1) Register Offset Description Reset Value CCR1 PWM_BA+0x054 0x0000_0000 Capture Control Register Reserved CFLRD3 CRLRD3 Reserved CIIR3 CAPCH3EN FL&IE3 RL&IE3 INV3 Reserved CFLRD2 CRLRD2 Reserved CIIR2 CAPCH2EN FL&IE2 RL&IE2 INV2 Bits Descriptions [31:23] Reserved Reserved CFLR3 dirty bit...
Page 873 N9H26 Technical Reference Manual Bits Descriptions Interrupt. Channel 3 Rising Interrupt Enable ON/OFF 1: Enable [17] RL&IE3 0: Disable When Enable, if Capture detects Channel 3 has rising transition, Capture issues an Interrupt. Channel 3 Inverter ON/OFF [16] INV3 1: Inverter ON 0: Inverter OFF [15:8] Reserved...
Page 874 N9H26 Technical Reference Manual Capture Rising Latch Register3-0 (CRLR3-0) Register Offset Reset Value Description CRLR0 PWM_BA+0x058 0x0000_0000 Capture Rising Latch Register (channel 0) CRLR1 PWM_BA+0x060 0x0000_0000 Capture Rising Latch Register (channel 1) CRLR2 PWM_BA+0x068 0x0000_0000 Capture Rising Latch Register (channel 2) CRLR3 PWM_BA+0x070 0x0000_0000...
Page 875 N9H26 Technical Reference Manual Capture Falling Latch Register3-0 (CFLR3-0) Register Offset Reset Value Description CFLR0 PWM_BA+0x05C 0x0000_0000 Capture Falling Latch Register (channel 0) CFLR1 PWM_BA+0x064 0x0000_0000 Capture Falling Latch Register (channel 1) CFLR2 PWM_BA+0x06C 0x0000_0000 Capture Falling Latch Register (channel 2) CFLR3 PWM_BA+0x074 0x0000_0000...
Page 876 N9H26 Technical Reference Manual Capture Input Enable Register (CAPENR) Register Offset Reset Value Description CAPENR PWM_BA+0x078 0x0000_0000 Capture Input Enable Register Reserved Reserved Reserved Reserved CAPENR[3:0] Bits Descriptions [31:4] Reserved Reserved Capture Input Enable Register There are eight capture inputs from pad. Bit0~Bit3 are used to control each inputs ON or OFF.
Page 877 N9H26 Technical Reference Manual PWM Output Enable Register (PWM) Register Offset Reset Value Description PWM_BA+0x07C 0x0000_0000 PWM Output Enable Register Reserved Reserved Reserved Reserved PWM3 PWM2 PWM1 PWM0 Bits Descriptions [31:4] Reserved Reserved PWM timer 3 Output Enable Setup. PWM3 1 : Enable 0 : Disable PWM timer 2 Output Enable Setup.
Page 878: Uart Interface Controller
N9H26 Technical Reference Manual 5.23 UART Interface Controller 5.23.1 Overview The N9H26 provides two channels of Universal Asynchronous Receiver/Transmitters (UART). UART0 supports High Speed UART and UART1 perform Normal Speed UART, besides, only UART0 support flow control function. The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel conversion on data characters received from the peripheral, and a parallel-to-serial conversion on data characters received from the CPU.
Page 879: Block Diagram
N9H26 Technical Reference Manual False start bit detection. – Loop back mode for internal diagnostic testing – 5.23.3 Block Diagram APB BUS Status & control Status & control Control and TX_FIFO(64/16)* RX_FIFO(64/16)* Status registers TX shift register RX shift register Baud Rate Generator Baud out...
Page 880: Figure 5.23-2 Auto Flow Control Block Diagram
N9H26 Technical Reference Manual 5.23.4.6 Modem Status Register This register provides the current status of the control lines from the MODEM and cause the MODEM status interrupt (CTS# or DSR# or RI# or DCD#) Note: Only CTS#/RTS# can be used in this version, and normal speed not support. 5.23.4.7 Baud Rate Generator Dividing the external clock by the divider to get the desired internal clock 5.23.4.8 Control and Status Register...
Page 881: Finite State Machine
N9H26 Technical Reference Manual 5.23.5 Finite State Machine 5.23.5.1 Transmitter THRE IDLE ! THRE WAIT count 7 START count F !TXDATA_END &count F PARITY & TXDATA_END PARITY !PARITY & TXDATA_END count F !THRE THRE STOP State Definition IDLE The transmitter has no data to transmit. WAIT The transmitter’s FIFO is not empty.
Page 882 N9H26 Technical Reference Manual THRE Te transmitter holding register is empty. Count7 The counter of clock equals to 7. CountF The counter of clock equals to 15. TXDATA_END The data part transfer is finished. PARITY The transfer includes the parity bit. NOTE: The format of the transfer is as following: One transfer = Start + Data + Parity bit (if dedicated) + Stop bit...
Page 883 N9H26 Technical Reference Manual IDLE The receiver has no data to receive. START The receiver receives the start bit. The receiver receives the desired data. PARITY The receiver receives the parity bit. STOP The receiver receives the parity bit. Signal Description Start_detect To detect the start of the transfer SIN_syn2...
Page 884: Uart Interface Control Registers Map
N9H26 Technical Reference Manual 5.23.6 UART Interface Control Registers Map R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written First set of the UART Interface register Map Channel0: UART_Base0 (High Speed) = 0xB800_8000 Channel1: UART_Base1 (Normal Speed) = 0xB800_8100 Register...
Page 885 N9H26 Technical Reference Manual Receive Buffer Register (UA_RBR) Register Address Description Reset Value UA_RBR UA_BA + 0x00 Receive Buffer Register. Undefined Reserved Reserved Reserved 8-bit Received Data Bits Descriptions Receive Buffer Register 8-bit Received [7:0] Data By reading this register, the UART will return an 8-bit data received from SIN pin (LSB first). Publication Release Date: Sept.
Page 886 N9H26 Technical Reference Manual Transmit Holding Register (UA_THR) Register Address Description Reset Value UA_THR UA_BA + 0x00 Transmit Holding Register. Undefined Reserved Reserved Reserved 8-bit Transmitted Data Bits Descriptions Transmit Holding Register [7:0] 8-bit Transmitted Data By writing to this register, the UART will send out an 8-bit data through the SOUT pin (LSB first).
Page 887 N9H26 Technical Reference Manual Interrupt Enable Register (UA_IER) Register Address Description Reset Value UA_IER UA_BA + 0x04 Interrupt Enable Register. 0x0000_0000 nDBGACK_EN Reserved Reserved DMA_Rx DMA_Tx Auto_CTS Auto_RTS Time_out Reserved Reserved Wake_IEN BUF_ERR RTO_IEN MS_IEN RLS_IEN THRE_IEN RDA_IEN _IEN Bits Descriptions ICE debug mode acknowledge enable 0 = When DBGACK is high, the UART receiver time-out clock will be held...
Page 888 N9H26 Technical Reference Manual Bits Descriptions [10:7] Reserved Reserved Wake up interrupt enable for INTR[wakeup] 0 = Mask off INTR_Wakeup Wake_IEN 1 = Enable INTR_Wakeup function, when the system is in deep sleep mode, an external /CTS change will wake up CPU from deep sleep mode. Buffer Error interrupt enable BUF_ERR_IEN 0 = Mask off INTR_Buf_err...
Page 889 N9H26 Technical Reference Manual FIFO Control Register (UA_FCR) Register Address Description Reset Value UA_FCR UA_BA + 0x08 FIFO Control Register 0x0000_0001 Reserved RTS_ctrl_n Reserved RTS_Tri_lev Reserved RFITL Reserved Reserved Bits Descriptions [31:24] Reserved Reserved RTS Control FIFO Enable (Active-low) [23] RTS_ctrl_n 0 : RxFIFO is controlled by RTS, it can not be written when RTS is active.
Page 890 N9H26 Technical Reference Manual Bits Descriptions 0000 0001 0010 0011 0100 30/14 (High Speed/Normal Speed) 0101 46/14 (High Speed/Normal Speed) 0110 62/14 (High Speed/Normal Speed) others 62/14 (High Speed/Normal Speed) Reserved Reserved Tx Software Reset When Tx_RST is set, all the bytes in the transmit FIFO and Tx internal state machine are cleared.
Page 891 N9H26 Technical Reference Manual Line Control Register (UA_LCR) Register Address Description Reset Value UA_LCR UA_BA + 0x0C Line Control Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Descriptions [31:7] Reserved Reserved Break Control Bit When this bit is set to logic 1, the serial data output (SOUT) is forced to the Spacing State (logic 0). This bit acts only on SOUT and has no effect on the transmitter logic.
Page 892 N9H26 Technical Reference Manual Bits Descriptions 6 bits 7 bits 8 bits Publication Release Date: Sept. 10, 2018 - 892 - Revision V1.01...
Page 893 N9H26 Technical Reference Manual MODEM Control Register (UA_MCR) Register Address Description Reset Value UA_MCR UA_BA + 0x10 MODEM Control Register 0x0000_2000 Reserved Reserved Reserved RTS_st Reserved Lev_RTS Reserved Reserved LBME Reserved RTS# Reserved Bits Descriptions [31:14] Reserved Reserved RTS Pin State (not available in UART1 channel) [13] RTS_st This bit is the pin status of RTS.
Page 894 N9H26 Technical Reference Manual Modem Status Register (UA_MSR) Register Address Description Reset Value UA_MSR UA_BA + 0x14 Modem Status Register 0x0000_00XX Reserved Reserved Reserved Lev_CTS Reserved CTS_st Reserved DCTS Bits Descriptions [31:9] Reserved Reserved CTS Trigger Level (not available in UART1 channel) This bit can change the CTS trigger level.
Page 895 N9H26 Technical Reference Manual FIFO Status Register (UA_FSR) Register Address Description Reset Value UA_FSR UA_BA + 0x18 FIFO Status Register 0x1040_4000 Reserved TE_Flag Reserved Tx_Over_IF Tx_Full Tx_Empty Tx_Pointer Rx_Full Rx_Empty Rx_Pointer Reserved Reserved Rx_Over_IF Bits Descriptions [31:29] Reserved Reserved Transmitter Empty Flag (Read Only) 0 = Bit is cleared automatically when Tx FIFO is not empty or the last byte transmission has not completed.
Page 896 N9H26 Technical Reference Manual Bits Descriptions TX FIFO Pointer (Read Only) This field indicates the Tx FIFO Buffer Pointer. When CPU writes one byte into UA_THR, [21:16] Tx_Pointer Tx_Pointer increases one. When one byte of Tx FIFO is transferred to Transmitter Shift Register, Tx_Pointer decreases one.
Page 897 N9H26 Technical Reference Manual Interrupt Status Control Register (UA_ISR) Register Address Description Reset Value UA_ISR UA_BA + 0x1C Interrupt Status Register. 0x0000_80XX DMA_Rx HW_Buf_ Reserved _Flag Wake_INT Err_INT Tout_INT Modem_INT RLS_INT DMA_Tx HW_Buf_ Reserved _Flag Wake_IF Err_IF Tout_IF Modem_IF RLS_IF Soft_Rx Wake_INT Buf_Err...
Page 898 N9H26 Technical Reference Manual Bits Descriptions Hardware DMA Tx Mode Flag (Read Only) DMA_Tx [23] 0 = The UART is not work in DMA TX mode _Flag 1 = The UART is work in DMA TX mode Hardware Wake Up Flag (Read Only) [22] 0 = None.
Page 899 N9H26 Technical Reference Manual Bits Descriptions 0 = None. 1 = Buffer Error interrupt occur when in Software mode. Time Out Interrupt Pin Status (INTR_Tout) Tout An AND output with inputs of RTO_IEN and Tout_IF [12] _INT 0 = None. 1 = Time out interrupt occur when in Software mode.
Page 900 N9H26 Technical Reference Manual Bits Descriptions MODEM Status Flag (Read Only) (not available in UART1 channel) This bit is set when the CTS pin has state change(DCTSF=1). if IER[Modem_IEN] is enabled, the Modem interrupt will be generated. Modem 0 = None. 1 = Modem status flag occur when in Software mode.
Page 901: Uart Interrupt Sources And Flags Table In Dma Mode
N9H26 Technical Reference Manual 5.24 UART Interrupt Sources and Flags Table In DMA Mode Interrupt Enable Bit Interrupt Indicator To UART Interrupt Source Interrupt Flag Flag Clear By Interrupt Controller Write ‘1’ to LIN RX Break Field LIN_RX_BRK_IEN HW_LIN_Rx_Break_INT HW_LIN_Rx_Break_IF Detected interrupt LIN_Rx_Break_IF Write ‘1’...
Page 902 N9H26 Technical Reference Manual Time Out Register (UA_TOR) Register Address Description Reset Value UA_TOR UA_BA + 0x20 Time Out Register 0x0000_0000 Reserved Reserved Reserved TOIC Bits Descriptions [31:8] Reserved Reserved Time Out Interrupt Comparator The time out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word.
Page 903 N9H26 Technical Reference Manual Baud Rate Divider Register Register Address Description Reset Value UA_BAUD UA_BA + 0x24 Baud Rate Divider Register 0x0F00_0000 Reserved DIV_X_EN DIV_X_ONE Divider X Reserved Baud Rate Divider DLM (High Byte) Baud Rate Divider DLL (Low Byte) Bits Descriptions [31:30]...
Page 904 N9H26 Technical Reference Manual Publication Release Date: Sept. 10, 2018 - 904 - Revision V1.01...
Page 905: Spi0 Serial Interface Controller (Master/Slave)
N9H26 Technical Reference Manual 5.25 SPI0 Serial Interface Controller (Master/Slave) 5.25.1 Overview The MICROWIRE/SPI Synchronous Serial Interface performs a serial-to-parallel conversion on data characters received from the peripheral, and a parallel-to-serial conversion on data characters received from CPU. This interface can drive up to 2 external peripherals and is seen as the master or can be driven as the slave.
Page 906: Figure 5.25-1 Microwire/Spi Block Diagram (Master/Slave)
N9H26 Technical Reference Manual SPI_CLK spi_sclk_o spi_sclk_i SPI_SIO[3:0] spi_sio_o[3:0] GPIO SPI_SS0 spi_sio_i[3:0] Master / Slave spi_ss_o[1:0] SPI_SS1 spi_ss_i pclk spi_int_o CLKGEN Figure 5.25-1 MICROWIRE/SPI Block Diagram (Master/Slave) Publication Release Date: Sept. 10, 2018 - 906 - Revision V1.01...
Page 907 N9H26 Technical Reference Manual Pin Name Pin Description spi_sclk_o MICROWIRE/SPI master serial clock output. spi_sclk_i MICROWIRE/SPI slave serial clock input. spi_sio_o[3:0] MICROWIRE/SPI serial data output to slave device in master mode or to master device in slave mode. spi_sio_i[3:0] MICROWIRE/SPI serial data input from slave device in master mode or from master device in slave mode.
Page 908: Spi (Microwire) Timing Diagram (Master/Slave)
N9H26 Technical Reference Manual 5.25.4 SPI (MICROWIRE) Timing Diagram (Master/Slave) Figure 5.25-2 MICROWIRE/SPI Timing (Master) Figure 5.25-3 Alternate Phase SCLK Clock Timing (Master) Publication Release Date: Sept. 10, 2018 - 908 - Revision V1.01...
Page 909: Figure 5.25-4 Microwire/Spi Timing (Slave)
N9H26 Technical Reference Manual Figure 5.25-4 MICROWIRE/SPI Timing (Slave) Figure 5.25-5 Alternate Phase SCLK Clock Timing (Slave) Publication Release Date: Sept. 10, 2018 - 909 - Revision V1.01...
Page 910: Spi (Microwire) Programming Example
N9H26 Technical Reference Manual 5.25.5 SPI (MICROWIRE) Programming Example When using this SPI controller as a master to access a slave device (as slave device) with following specifications:  Data bit latches on positive edge of serial clock  Data bit drives on negative edge of serial clock ...
Page 911 N9H26 Technical Reference Manual Basically, the following actions should be done (also, the specification of the connected master device should be referred to when consider the following steps in detail): 1. Write in SSR, set SS_LVL = 1. When transmit (write) data to device: 2.
Page 912: Wireless Joystick Spi Programming Example
N9H26 Technical Reference Manual 5.25.6 Wireless Joystick SPI Programming Example While connecting to wireless joystick, SPI should be set to slave mode and SPI0_JS[0] should be set to 1. Others setting required for this mode: 1. It use rising edge to transmit data and falling edge to receive data. SPI_CNTRL[Tx_NEG]=1 and SPI_CNTRL[Rx_NEG]=0 2.
Page 913 N9H26 Technical Reference Manual (6) After CS is pulled high, the transmission is finished. Slave should drive SDO low for a specified period. User can set SPI_DIVIDER to control the period. (7) After the counter in (6) reaches 0, slave will set SDO as input mode again. Description: (1) When CS is high, slave will keep SDO as input mode.
Page 914: Spi0 (Microwire) Serial Interface Control Register Map
N9H26 Technical Reference Manual 5.25.7 SPI0 (MICROWIRE) Serial Interface Control Register Map R: read only, W: write only, R/W: both read and write NOTE 1: When software programs CNTRL, the GO_BUSY bit should be written last. Register Offset Description Reset Value SPIMS0_BA = 0xB800_C000 SPI0_CNTRL SPIMS0_BA + 0x00...
Page 915: Spi 0 (Microwire) Control Register Description
N9H26 Technical Reference Manual 5.25.8 SPI 0 (MICROWIRE) Control Register Description Control and Status Register (CNTRL) Register Offset Description Reset Value SPI0_CNTRL SPIMS0_BA + 0x00 0x0000_0004 Control and Status Register Reserved SIO_DIR Tx_NUM BYTE_ENDIN Reserved SLAVE SLEEP CLKP BIT_MODE Tx_BIT_LEN Tx_NEG Rx_NEG GO_BUSY...
Page 916 N9H26 Technical Reference Manual Bits Descriptions When the transmission is set as MSB first and the BYTE ENDIN bit is set high, the data store in the TX buffer will be arranged in order as [BYTE0, BYTE1, BYTE2, BYTE3] in TX_BIT_LEN = 32 bit mode, and the sequence of transmitted data will be BYTE0, BYTE1, BYTE2, and BYTE3.
Page 917 N9H26 Technical Reference Manual Bits Descriptions Tx_BIT_LEN = 0x01 … 1 bit Tx_BIT_LEN = 0x02 … 2 bits …… Tx_BIT_LEN = 0x1f … 31 bits Tx_BIT_LEN = 0x00 … 32 bits Transmit On Negative Edge 0 = The spi_so_o signal is changed on the rising edge of spi_sclk_o in master mode or Tx_NEG spi_sclk_i in slave mode.
Page 918 N9H26 Technical Reference Manual Divider Register (DIVIDER) Register Offset Description Reset Value SPI0_DIVIDER SPIMS0_BA + 0x04 R/W 0x0000_0000 Clock Divider Register Reserved Reserved DIVIDER[15:8] DIVIDER[7:0] Bits Descriptions Clock Divider Register The value in this field is the frequency divider of the system clock pclk to generate the serial clock on the output spi_sclk_o.
Page 919 N9H26 Technical Reference Manual Slave Select Register (SSR) Register Offset Description Reset Value SPI0_SSR SPIMS0_BA + 0x08 0x0000_0000 Slave Select Register Reserved Reserved Reserved Reserved LTRIG_FLAG SS_LTRIG SS_LVL SSR[1:0] Bits Descriptions Level Trigger Flag When the SS_LTRIG bit is set in slave mode, this bit can be read to indicate the received bit number is met the requirement or not.
Page 920 N9H26 Technical Reference Manual Bits Descriptions NOTE: This interface can only drive one device/slave at a given time. Therefore, the slave select of the selected device must be set to its active level before starting any read or write transfer. NOTE: spi_ss_o[0] is also defined as device/slave select input spi_ss_i signal in slave mode.
Page 921 N9H26 Technical Reference Manual Dongle Joystick Control Register (JS) Register Offset Description Reset Value SPI0_JS SPIMS0_BA + 0x10 0x0000_0100 Dongle joystick control register Reserved Reserved Reserved READY JS_INT_FLAG JS_RW Reserved Bits Descriptions Slave is ready to transmit/receive data In Dongle Joystick mode, SDO will be set to input mode when CS (chip select) is high. READYB When the outside master is pull CS low, slave should set SDO as output mode.
Page 922 N9H26 Technical Reference Manual EDMA Control Register (EDMACTL) Register Offset Description Reset Value SPI0_EDMA SPIMS0_BA + 0x18 0x0000_0000 EDMA mode control register Reserved Reserved Reserved Reserved EDMA_RW EDMA_GO Bits Descriptions EDMA Read or EDMA Write EDMA_RW 0: EDMA write to SPI module 1: EDMA read from SPI module EDMA start Set this bit to 1 will start the EDMA process.
Page 923 N9H26 Technical Reference Manual Data Receive Register (RX) Register Offset Description Reset Value SPI0_Rx0 SPIMS0_BA + 0x20 0x0000_0000 Data Receive Register 0 SPI0_Rx1 SPIMS0_BA + 0x24 0x0000_0000 Data Receive Register 1 SPI0_Rx2 SPIMS0_BA + 0x28 0x0000_0000 Data Receive Register 2 SPI0_Rx3 SPIMS0_BA + 0x2C 0x0000_0000...
Page 924 N9H26 Technical Reference Manual Data Transmit Register (TX) Register Offset Description Reset Value SPI0_Tx0 SPIMS0_BA + 0x20 0x0000_0000 Data Transmit Register 0 SPI0_Tx1 SPIMS0_BA + 0x24 0x0000_0000 Data Transmit Register 1 SPI0_Tx2 SPIMS0_BA + 0x28 0x0000_0000 Data Transmit Register 2 SPI0_Tx3 SPIMS0_BA + 0x2C 0x0000_0000...
Page 925: Analog Digital Converter
N9H26 Technical Reference Manual 5.26 Analog Digital Converter 5.26.1 Analog Digital Converter Description Touch Panel Unit Touch Panel Control 12Bits 8 Input SAR-ADC 4-Wire Touch Screen Figure 5.26-1Touch Panel Control Block Diagram Figure 6.25-1 is the whole Analog-Digital-Converter block diagram. It includes two block, one is digital block (touch panel control), and the other is SAR-ADC block (12-bits 8-input SAR-ADC).
Page 926: Figure 5.26-2 12-Bit 8-Input Sar-Adc Block Diagram
N9H26 Technical Reference Manual PULLUP XP_EN INT_TC VREF AVDD33 2.5V Bandgap YP_EN 4-1 MUX XM_EN Internal 8-1 MUX SAR ADC YM_EN 4-1 MUX A_3, A_2, VHS AGND33 AGND33 Resistor Divider KEYPAD & INT_KP switch Figure 5.26-2 12-Bit 8-Input SAR-ADC Block Diagram Publication Release Date: Sept.
Page 927: Figure 5.26-3 Touch Screen Connection Diagram
N9H26 Technical Reference Manual 12-Bits 8-Input SAR-ADC Figure 5.26-3 Touch Screen Connection Diagram XP_EN = 1 XM_EN = 1 AVDD33 YP_EN = 0 YM_EN = 0 Touch XP_EN PULLUP = 0 Screen IN_SEL[2:0] = 101 REF_SEL[1:0] = 10 Internal SAR ADC XM_EN AGND33 Figure 5.26-4 Simplified Diagram of X Axis Conversion...
Page 928: Figure 5.26-5 Simplified Diagram Of Y Axis Conversion
N9H26 Technical Reference Manual XP_EN = 0 XM_EN = 0 AVDD33 YP_EN = 1 YM_EN = 1 Touch YP_EN PULLUP = 0 Screen IN_SEL[2:0] = 111 REF_SEL[1:0] = 01 Internal SAR ADC YM_EN AGND33 Figure 5.26-5 Simplified Diagram of Y Axis Conversion AVDD33 XP_EN = 0 PULLUP...
Page 929: Touch Panel Register
N9H26 Technical Reference Manual 5.26.2 Touch Panel Register 5.26.2.1 Touch Panel Register Map R: read only, W: write only, R/W: both read and write Register Address Description Reset Value TP_BA = 0xB800_F000 TP_CTL1 TP_BA+0x00 0x0000_E000 Touch Panel control register TP_CTL2 TP_BA+0x04 0x0000_0404 Touch Panel control register...
Page 930 N9H26 Technical Reference Manual 5.26.2.2 Touch Panel Register Description Touch Panel Control Register 1 (TP_CTL1) Register Address Description Reset Value TP_CTL1 ADC_BA+0x00 0x0000_E000 Touch Panel control register 1 Reserved XP_EN XM_EN YP_EN YM_EN PLLUP IN_SEL[2:0] PD_KEYPAD PD_BUF SLEEP LOW_SPEED REF_SEL[1:0] SLOW_CMP Reserved TSMODE...
Page 931 N9H26 Technical Reference Manual Bits Descriptions 101 = YP 110 = XM 111 = XP Power Down the Keypad Detection [15] PD_KEYPAD 1 = Power Down Enabled 0 = Power Down Disabled Power Down the Internal Reference Buffer When REF_SEL[1:0] is not 00, internal buffer should be turned off. [14] PD_BUF 1 = Power Down Enabled...
Page 932 N9H26 Technical Reference Manual Bits Descriptions following Equation to calculate the touch resistance:    Touch plate 4096 Therefore, setting this bit to “1” will automatically get three results, X-plate resistance, Z1 and Z2. 1 = Start to get the pressure information 0 = Finish the process Note: This bit will be cleared to ‘0’...
Page 933 N9H26 Technical Reference Manual Touch Panel Control Register 2 (TP_CTL2) Register Register Address Description Reset Value TP_CTL2 ADC_BA+0x04 0x0000_0404 Touch Panel control register 2 Reserved Reserved Reserved SPL_CHK_TIME[7:0] Bits Descriptions [31:8] RESERVED RESERVED Sample & Check Time [7:0] SPL_CHK_TIME The sample / hold and check period time. The unit is SAR-ADC clock. Publication Release Date: Sept.
Page 934 N9H26 Technical Reference Manual Touch Panel Interrupt State (TP_INTST) Register Register Address Description Reset Value TP_INTST ADC_BA+0x08 Touch Panel interrupt state 0x0000_0000 Reserved Reserved Reserved Reserved INT_MASK INT_TC_MAS INT_KEY_MA Reserved INT_TC INT_KEY Bits Descriptions [31:7] RESERVED RESERVED Interrupt Mask INT_MASK 1 = Mask Enabled 0 = Mask Disabled Pen Down Interrupt Mask...
Page 935 N9H26 Technical Reference Manual Bits Descriptions Interrupt State When finishing the sample process, the INT will be set. And if the INT_MASK is high, the interrupt will be transferred to AIC. 1 = Interrupt state Enabled 0 = Interrupt state Disabled Pen Down Interrupt State When in the process of checking pen down, the INT_TC show the state.
Page 936 N9H26 Technical Reference Manual XY Data Buffer (XY_DATA) Register Register Address Description Reset Value XY_DATA TP_BA+0x10 0x0000_0000 Touch Panel X data Register PenX Reserved X_DATA[11:8] X_DATA[7:0] PenY Reserved Y_DATA[11:8] Y_DATA[7:0] Bits Descriptions Pen Down Information for X_DATA This bit shows the X_DATA is valid or not. Only when in pen down period, the X_DATA is valid.
Page 937 N9H26 Technical Reference Manual Z Data Buffer (Z_DATA) Register Register Address Description Reset Value Z_DATA TP_BA+0x14 0x0000_0000 Touch Panel Z data Register PenZ1 Reserved Z1_DATA[11:8] Z1_DATA[7:0] PenZ2 Reserved Z2_DATA[11:8] Z2_DATA[7:0] Bits Descriptions Pen Down Information for Z1_DATA This bit shows the Z1_DATA is valid or not. Only when in pen down period, the Z1_DATA [31] PenZ1 is valid.
Page 938 N9H26 Technical Reference Manual Normal Data Buffer (NORM_DATA) Register Register Address Description Reset Value NORM_DATA TP_BA+0x14 Normal process data register 0x0000_0000 Reserved Reserved Reserved NORM_DATA[11:8] NORM_DATA[7:0] Bits Descriptions [31:12] RESERVED RESERVED Normal Process Data Register [11:0] NORM_DATA When Software trigger to get the ADC result, the data will be saved in NORM_DATA. Publication Release Date: Sept.
Page 939: Keypad Interface (Kpi)
N9H26 Technical Reference Manual 5.27 Keypad Interface (KPI) 5.27.1 Overview The Keypad Interface (KPI) is an APB slave with configurable minimum 2-row up to 16-row scan output and minimum 1-column up to 4-column scan input. Any keys in the array pressed or released are de-bounced and generate an interrupt.
Page 940: Kpi Block Diagram
N9H26 Technical Reference Manual 5.27.3 KPI Block Diagram WAKEUP 16'hFFFF KPI_ROW Clock Row scan XCLOCK Prescalar Row counter Divider Generation precounter hit Column sample sample_en (From HSYNC) DBT[7:0] & KPI_INT comparator Debounce counter pin_keep KPI_COL STATUS register & sus_flag Three Key &...
Page 941: Keypad Interface Register Map
N9H26 Technical Reference Manual 5.27.4 Keypad Interface Register Map Register Address Description Reset Value KPI_BA = 0xB800_5000 KPICONF KPI_BA+0x000 Keypad configuration Register 0x0000_0000 KPI3KCONF KPI_BA+0x004 Keypad 3-keys configuration register 0x0000_0000 KPISTATUS KPI_BA+0x008 Keypad status register 0x0000_0000 KPIRSTC KPI_BA+0x00C Keypad reset period controller register 0x0000_0000 KPIKEST0 KPI_BA+0x010...
Page 942 N9H26 Technical Reference Manual Keypad Controller Configuration Register (KPI_CONF) Register Address Description Reset Value KPICONF KPI_BA+0x000 Keypad configuration register 0x0000_0000 KROW[3:0] Reserved KCOL[1:0] DB_EN Reserved DBCLKSEL PRESCALE[7:0] Reserved INPU WAKEUP ODEN INTEN RKINTEN PKINTEN ENKP Bits Descriptions [31:28] KROW Keypad Matrix ROW number The keypad matrix is set by ROW x COL.
Page 943 N9H26 Technical Reference Manual KCOL[25:24] Keypad maxtrix COLUMN number [21] DB_EN Scan In Signal De-bounce Enable 0 = The de-bounce function is disabled 1 = The de-bounce function is enabled [20] Reserved Reserved [19:16] DBCLKSEL Scan In De-bounce sampling cycle selection DBCLKSEL Description Sample interrupt input once per 1 clocks...
Page 944 N9H26 Technical Reference Manual [15:8] PRESCALE Row Scan Cycle Pre-scale Value This value is used to pre-scale row scan cycle. The pre-scale counter is clocked by the divided crystal clock, xCLOCK. The divided number is from 1 to 256. Eg.If the crystal clock is 1Mhz then the xCLOCK period is 1us. If the keypad matric is 3x3 then Each row scan time = xCLOCK x PRESCALE x PrescaleDivider Key array scan time = Each row scan time x ROWS Example scan time for PRESCALE = 0x41,and PrescaleDivider = 0x1F...
Page 945 N9H26 Technical Reference Manual Publication Release Date: Sept. 10, 2018 - 945 - Revision V1.01...
Page 946 N9H26 Technical Reference Manual Keypad Controller 3-keys Configuration Register (KPI3KCONF) Register Address Description Reset Value KPI3KCONF KPI_BA+0x004 Keypad 3-keys configuration register 0x0000_0000 Reserved EN3KYRST Reserved K32R K32C Reserved K31R K31C Reserved K30R K30C Bits Descriptions [31:25] Reserved Reserved Enable Three-key Reset Setting this bit enable hardware reset when three-key is detected [24] EN3KYRST...
Page 947 N9H26 Technical Reference Manual Key Pad Interface Status Register (KPISTATUS) Register Address Description Reset Value KPISTATUS KPI_BA+0x008 Keypad status register 0x0000_0000 Reserved Reserved Reserved Reserved PKEY_INT RKEY_INT KEY_INT RST_3KEY PDWAKE Bits Descriptions [31:5] Reserved Reserved Press key interrupt This bit indicates that some keys (one or multiple key) were pressed Read 1 : At least one key press 0 = no key press...
Page 948 N9H26 Technical Reference Manual Bits Descriptions key reset or wakeup Read 1 = key press/release/3-key reset/wakeup interrupt occur 0 = Not reset 3-Keys Reset Flag This bit will be set after 3-keys reset occur. Read 1 = 3 keys reset interrupt occur RST_3KEY 0 = Not reset Write...
Page 949 N9H26 Technical Reference Manual Keypad Reset Period Controller Register (KPIRSTC) Register Address Description Reset Value KPIRSTC KPI_BA+0x00C Keypad Reset Period Control register 0x0000_0000 Reserved Reserved Reserved RSTC Bits Descriptions [31:8] Reserved Reserved 3-key Reset Period Count The keypad controller generates a reset signal when it detects 3-key match condition, if [7:0] RSTC the ENRST is set.
Page 950 N9H26 Technical Reference Manual Keypad KEY STATE 0 (KPIKEST0) Register Address Description Reset Value KPIKEST0 KPI_BA+0x010 Key state register 0 0x0000_0000 KEST73 KEST72 KEST71 KEST70 KEST63 KEST62 KEST61 KEST60 KEST53 KEST52 KEST51 KEST50 KEST43 KEST42 KEST41 KEST40 KEST33 KEST32 KEST31 KEST30 KEST23 KEST22...
Page 951 N9H26 Technical Reference Manual Keypad KEY STATE 1 (KPIKEST1) Register Address Description Reset Value KPIKEST1 KPI_BA+0x014 Key state register 1 0x0000_0000 KESTF3 KESTF2 KESTF1 KESTF0 KESTE3 KESTE2 KESTE1 KEST3E0 KESTD3 KESTD2 KESTD1 KESTD0 KESTC3 KESTC2 KESTC1 KESTC0 KESTB3 KESTB2 KESTB1 KESTB0 KESTA3 KESTA2...
Page 952 N9H26 Technical Reference Manual KPIKPE0 (KPIKPE0) Register Address Description Reset Value KPIKPE0 KPI_BA+0x018 Lower 32 Key press event indicator 0x0000_0000 KPE73 KPE72 KPE71 KPE70 KPE63 KPE62 KPE61 KPE60 KPE53 KPE52 KPE51 KPE50 KPE43 KPE42 KPE41 KPE40 KPE33 KPE32 KPE31 KPE30 KPE23 KPE22 KPE21...
Page 953 N9H26 Technical Reference Manual KPIKPE1 (KPIKPE1) Register Address Description Reset Value KPIKPE1 KPI_BA+0x01C Upper 32 Key press event indicator 0x0000_0000 KPEF3 KPEF2 KPEF1 KPEF0 KPEE3 KPEE2 KPEE1 KPEE0 KPED3 KPED2 KPED1 KPED0 KPEC3 KPEC2 KPEC1 KPEC0 KPEB3 KPEB2 KPEB1 KPEB0 KPEA3 KPEA2 KPEA1...
Page 954 N9H26 Technical Reference Manual KPIKRE0 (KPIKRE0) Register Address Description Reset Value KPIKRE0 KPI_BA+0x020 Lower 32 Key release event indicator 0x0000_0000 KRE73 KRE72 KRE71 KRE70 KRE63 KRE62 KRE61 KRE60 KRE53 KRE52 KRE51 KRE50 KRE43 KRE42 KRE41 KRE40 KRE33 KRE32 KRE31 KRE30 KRE23 KRE22 KRE21...
Page 955 N9H26 Technical Reference Manual KPIKRE1 (KPIKRE1) Register Address Description Reset Value KPIKRE1 KPI_BA+0x024 Upper 32 Key release indicator 0x0000_0000 KREF3 KREF2 KREF1 KREF0 KREE3 KREE2 KREE1 KREE0 KRED3 KRED2 KRED1 KRED0 KREC3 KREC2 KREC1 KREC0 KREB3 KREB2 KREB1 KREB0 KREA3 KREA2 KREA1 KREA0...
Page 956 N9H26 Technical Reference Manual PrescaleDivider (PrescaleDivider) Register Address Description Reset Value PrescaleDivider KPI_BA+0x028 Prescale divider 0x0000_0000 Reserved Reserved Reserved Prescale divider[7:0] Bits Descriptions Divide Prescaler This value is used to divide RESCALE that is set in KPI_CONF[15:8]. The Prescale divider counter is clocked by the divided crystal clock, xCLOCK. The number is from 1 to 256.
Page 957 N9H26 Technical Reference Manual KPILCM Register Address Description Reset Value KPILCM KPI_BA+0x02C Keypad and LCM Bus Share Setting 0x0000_0100 LCMMODE Reserved Reserved Reserved HSDBROW HSDBNUM Bits Descriptions LCM Mode Enable [31] LCMMODE 0: LVDATA[15:0] are always LCD output. 1: KPI Scan-out output from LVDATA[15:0], share with LCD bus. KPI 8Bit mode [30] KPI_8BIT...
Page 958 N9H26 Technical Reference Manual KPISUS Register Address Description Reset Value KPISUS KPI_BA+0x030 Keypad Suspend Mode Setting 0x000F_FFFF SUSFORCE Reserved Reserved SUSCNUM[19:16] SUSCNUM[15:8] SUSCNUM[7:0] Bits Descriptions 0: Normal detection mode (decide by SUSCNUM) [31] SUSFORCE 1: Force KPI into suspend mode. [30:20] Reserved Reserved...
Page 959: Audio Record Control
N9H26 Technical Reference Manual 5.28 Audio Record Control 5.28.1 Overview Audio Record Block AudioRecord Wrapper Register Signa-Delta AGC & NG Figure 5.28-1 Audio Record Block Diagram The Audio Record control block has two parts. One is the analog IP (sigma-delta ADC), and the other is digital audio record control.
Page 960: Noise Gate Detection Block
N9H26 Technical Reference Manual AuidoData Moving Target Level Output Gain Control Average Compare State Machine PostGain Output Lookup Table NG Gain IN_NG_TIME Enter NG Strength Noise Level NG Level Lookup Table Compare Leave NG OUT_NG_TIME Strength Figure 5.28-2 Auto Gain Control Block Diagram The algorithm is to count the time which the input data power is lower than the noise threshold, when in the Enter NG Strength Block.
Page 961 N9H26 Technical Reference Manual Power Threshold Time NG_FLAG Publication Release Date: Sept. 10, 2018 - 961 - Revision V1.01...
Page 962: Audio Record Control Register
N9H26 Technical Reference Manual 5.28.4 Audio Record Control Register Audio Record Control Register Map R: read only, W: write only, R/W: both read and write Register Address Description Reset Value AR_BA = 0xB800_E000 AR_CTL AR_BA+0x00 Audio Record control register 0x8000_000C AR_AGC1 AR_BA+0x04 Audio Record AGC control register 1...
Page 963: Audio Record Control Register Description
N9H26 Technical Reference Manual 5.28.5 Audio Record Control Register Description Audio Record Control Register (AR_CTL) Register Address Description Reset Value AR_CTL AR_BA+0x00 0x8000_000C Audio Record control register AR_RST TCONFIG TSLAVE TPLLBY Reserved Reserved Reserved Reserved EDMA_EN INT_MOD[1:0] INT_EN Bits Descriptions ADC Analog IP Reset [31] AR_RST...
Page 964 N9H26 Technical Reference Manual Bits Descriptions Interrupt Mask INT_EN 1 = Mask Enabled 0 = Mask Disabled Interrupt The interrupt will happen when recording the desired number samples. And the number depends on INT_MOD[1:0]. But if in EDMA mode, the interrupt is useless. Note: Write 1 to Clear Publication Release Date: Sept.
Page 965 N9H26 Technical Reference Manual Audio Record AGC Register 1 (AR_AGC1) Register Address Description Reset Value AR_AGC1 AR_BA+0x04 Audio Record AGC control register 0x00E0_0050 AGC_EN Reserved GSTEP Reserved Reserved Reserved RECOVERY [11:8] RECOVERY [7:0] Bits Descriptions Auto Gain Control If opening this function, the gain will be changed by the OTP automatically. And the changing frequency is depended on the ATTACH, RECOVERY, and HOLD registers.
Page 966 N9H26 Technical Reference Manual Audio Record AGC Register 2 (AR_AGC2) Register Address Description Reset Value AR_AGC2 AR_BA+0x08 Audio Record AGC control register 2 0x0050_0050 Reserved ATTACK[11:8] ATTACK[7:0] Reserved HOLD[11:8] HOLD[7:0] Bits Descriptions [31:28] RESERVED RESERVED AGC Attack (gain ramp-down) Time [27:16] ATTACK It is based on 64 samples.
Page 967 N9H26 Technical Reference Manual Audio Record Noise Gate Control Register (AR_NG) Register Address Description Reset Value AR_NG AR_BA+0x0C Audio Record noise gate control register 0x0500_0000 NG_EN Reserved DLYTIME IN_NG_TIME OUT_NG_TIME Reserved NG_GAIN Reserved NG_LEVEL Bits Descriptions Noise Gate Enable 1 = NG Enabled [31] NG_EN 0 = NG Disabled...
Page 968 N9H26 Technical Reference Manual Bits Descriptions [7:5] RESERVED RESERVED Noise Gate Threshold Level This is defined in the input sample power -79.6dB ~ -30dB @ 1.6dB Step 11111 = -30dB [4:0] NG_LEVEL 11110 = -31.6dB 11101 = -33.2dB …….. 00001 = -78dB 00000 = -79.6dB Publication Release Date: Sept.
Page 969 N9H26 Technical Reference Manual Audio Record Buffer Register 1 (AudioData1) Register Address Description Reset Value AudioData1 AR_BA+0x10 Audio data register 1 0x0000_0000 AudioDataL1[31:24] AudioDataL1[23:16] AudioDataL1[15:8] AudioDataL1[7:0] Bits Descriptions Converted Audio Data1 [31:0] AudioDataL1 32-bit digital audio data in 2’s compliment format. And the format can check the register SampleMode.
Page 970 N9H26 Technical Reference Manual Audio Record Buffer Register 2 (AudioData2) Register Address Description Reset Value AudioData2 AR_BA+0x14 Audio data register 2 0x0000_0000 AudioDataL2[31:24] AudioDataL2[23:16] AudioDataL2[15:8] AudioDataL2[7:0] Bits Descriptions Converted Audio Data2 [31:0] AudioDataL2 32-bit digital audio data in 2’s compliment format. And the format can check the register SampleMode.
Page 971 N9H26 Technical Reference Manual Audio Record Buffer Register 3 (AudioData3) Register Address Description Reset Value AudioData3 AR_BA+0x18 Audio data register 3 0x0000_0000 AudioDataL3[31:24] AudioDataL3[23:16] AudioDataL3[15:8] AudioDataL3[7:0] Bits Descriptions Converted Audio Data3 [31:0] AudioDataL3 32-bit digital audio data in 2’s compliment format. And the format can check the register SampleMode.
Page 972 N9H26 Technical Reference Manual Audio Record Buffer Register 4 (AudioData4) Register Address Description Reset Value AudioData4 AR_BA+0x1C Audio data register 4 0x0000_0000 AudioDataL4[31:24] AudioDataL4[23:16] AudioDataL4[15:8] AudioDataL4[7:0] Bits Descriptions Converted Audio Data4 [31:0] AudioDataL4 32-bit digital audio data in 2’s compliment format. And the format can check the register SampleMode.
Page 973 N9H26 Technical Reference Manual Audio Record Buffer Register 5 (AudioData5) Register Address Description Reset Value AudioData5 AR_BA+0x20 Audio data register 5 0x0000_0000 AudioDataL5[31:24] AudioDataL5[23:16] AudioDataL5[15:8] AudioDataL5[7:0] Bits Descriptions Converted Audio Data5 [31:0] AudioDataL5 32-bit digital audio data in 2’s compliment format. And the format can check the register SampleMode.
Page 974 N9H26 Technical Reference Manual Audio Record Buffer Register 6 (AudioData6) Register Address Description Reset Value AudioData6 AR_BA+0x24 Audio data register 6 0x0000_0000 AudioDataL6[31:24] AudioDataL6[23:16] AudioDataL6[15:8] AudioDataL6[7:0] Bits Descriptions Converted Audio Data6 [31:0] AudioDataL6 32-bit digital audio data in 2’s compliment format. And the format can check the register SampleMode.
Page 975 N9H26 Technical Reference Manual Audio Record Buffer Register 7 (AudioData7) Register Address Description Reset Value AudioData7 AR_BA+0x28 Audio data register 7 0x0000_0000 AudioDataL7[31:24] AudioDataL7[23:16] AudioDataL7[15:8] AudioDataL7[7:0] Bits Descriptions Converted Audio Data7 [31:0] AudioDataL7 32-bit digital audio data in 2’s compliment format. And the format can check the register SampleMode.
Page 976 N9H26 Technical Reference Manual Audio Record Buffer Register 8 (AudioData8) Register Address Description Reset Value AudioData8 AR_BA+0x2C Audio data register 8 0x0000_0000 AudioDataL8[31:24] AudioDataL8[23:16] AudioDataL8[15:8] AudioDataL8[7:0] Bits Descriptions Converted Audio Data8 [31:0] AudioDataL8 32-bit digital audio data in 2’s compliment format. And the format can check the register SampleMode.
Page 977 N9H26 Technical Reference Manual Sigma-delta ADC Control Register (SDADC_CTL) Register Address Description Reset Value SDADC_CTL AR_BA+0x30 Sigma-Delta ADC control register 0x0000_0000 BUSY SCK_DIV DEVICE_ID ADDR[7:0] DATA[7:0] Bits Descriptions I2C Command State If this address register has been written, the hardware would transfer the command to sigma-delta ADC by I2C interface.
Page 978 N9H26 Technical Reference Manual Sigma-delta ADC AGBIT Register (SDADC_AGBIT) Register Address Description Reset Value SDADC_AGBIT AR_BA+0x34 Sigma-Delta Auto Gain Temp Bits register 0x0000_0000 Reserved Reserved Reserved AGBIT_L AGBIT_R Bits Descriptions [31:8] Reserved Reserved Sigma-Delta ADC Auto Gain Temp Bits for Left Channel [7:4] AGBIT_L It should be set the higher 4 bits about the ADC IP address 22H...
Page 979 N9H26 Technical Reference Manual Digital Microphone Gain Register (AR_DIGIM) Register Address Description Reset Value AR_DIGIM AR_BA+0x38 Digital Microphone Gain Register 0x0000_0000 Reserved Reserved SampleMode DIGIM_EN Reserved DIGIM_LV Bits Descriptions [31:8] Reserved Reserved Audio Sample Mode 00 = AudioData1 = {AudioDataL1[23:0], 8’h00} AudioData2 = {AudioDataL2[23:0], 8’h00} AudioData3 = {AudioDataL3[23:0], 8’h00} AudioData4 = {AudioDataL4[23:0], 8’h00}...
Page 980 N9H26 Technical Reference Manual Bits Descriptions 11 = Reserved Digital Microphone Gain Control Enable DIGIM_EN 1 = Gain Control Enabled 0 = Gain Control Disabled [6:4] Reserved Reserved Digital Microphone Gain Level 0000 = 0dB 0001 = 1.6dB [3:0] DIGIM_LV 0010 = 3.2dB ….
Page 981 N9H26 Technical Reference Manual Sigma-delta ADC InfAGC Register (SDADC_InfAGC) Register Address Description Reset Value SDADC_InfAGC AR_BA+0x40 Information about AGC function register 0x0000_0000 Inf_Gain[7:0] Reserved Inf_Pwr[15:8] Inf_Pwr[7:0] Bits Descriptions Information about AGC Gain [31:24] Inf_Gain It shows the gain of ADC function [23:16] Reserved Reserved...
Page 982 N9H26 Technical Reference Manual Sigma-delta ADC Register Address ADC Output Control Register (Address: 20H; Default: 34H; Access: R/W) Bits Descriptions [7:4] RESERVED RESERVED High Pass Filter Enable or Disable HPF_EN 1 = HPF Enabled 0 = HPF Disabled Stereo or Mono STEREO_ADC 1 = Stereo mode (Default) 0 = L Mono mode;...
Page 983 N9H26 Technical Reference Manual ADC Power-down Control Register (Address: 21H; Default: 7CH; Access: R/W) Bits Descriptions RESERVED RESERVED VBIAS and IBIAS Power Down PDBIAS_L 1 = Power Down (Default) 0 = Power On Left Channel PGA Power Down PDPGAL_L 1 = Power Down (Default) 0 = Power On Right Channel PGA Power Down PDPGAR_L...
Page 984 N9H26 Technical Reference Manual ADC Left Channel Volume Control Register (Address: 22H; Default: 00H; Access: R/W) Bits Descriptions [7:5] RESERVED RESERVED Microphone Input Gain Boost ADC_VOLL[4] 1 = 20dB 0 = 0dB (Default) Left ADC input PGA gain control, 1.6dB step 0000 = 0dB (Default) 0001 = 1.6dB [3:0]...
Page 985 N9H26 Technical Reference Manual ADC Right Channel Volume Control Register (Address: 23H; Default: 00H; Access: R/W) Bits Descriptions [7:5] RESERVED RESERVED ADC_VOLR[4] Overflow Detection Control 1 = Detect and Suppress 0 = Do not detect (Default) [3:0] ADC_VOLR[3:0] Right ADC input PGA gain control, 1.6dB step 0000 = 0dB (Default) 0001 = 1.6dB ……..
Page 986 N9H26 Technical Reference Manual ADC Power Consumption Control Register (Address: 24H; Default: 1AH; Access: R/W) Bits Descriptions [7:3] RESERVED RESERVED Current Biasing Resistor Selection 000 = Smallest Biasing Resistor 100 = Medium Low Biasing Resistor [2:0] RESADJ 010 = Medium High Biasing Resistor 001 = Biggest Biasing Resistor Other = Reserved Publication Release Date: Sept.
Page 987 N9H26 Technical Reference Manual PLL Output Frequency Control Register (Address: 25H; Default: C0H; Access: R/W) Bits Descriptions Bypass Mode Control BYPASSPLL 1 = Bypass mode, PLL input goes to the PLL output frequency divider, then to the output. 0 = Normal mode for PLL PLL Power Down Control PDPLL 1 = Power Down...
Page 988 N9H26 Technical Reference Manual I2S Interface Control Register (Address: 26H; Default: 02H; Access: R/W) Bits Descriptions [7:2] RESERVED RESERVED Soft Reset Control SRESET 1 = Normal Operation 0 = Reset AD Filter and I2S parts except I2C block RESERVED RESERVED Publication Release Date: Sept.
Page 989 N9H26 Technical Reference Manual MIC Control Register (Address: 29H; Default: 0FH; Access: R/W) Bits Descriptions Microphone Selection MICIN_SEL 1 = Analog Microphone 0 = Digital Microphone [6:0] RESERVED RESERVED Publication Release Date: Sept. 10, 2018 - 989 - Revision V1.01...
Page 990: Aac Imdct/Mdct Engine
N9H26 Technical Reference Manual 5.29 AAC IMDCT/MDCT Engine 5.29.1 Overview AAC IMDCT/MDCT engine is designed to calculate the data for the AAC decoder or encoder. 5.29.2 Functional Block Diagram Figure 5.29-1Functional Block Diagram 5.29.3 Feature  Support AAC encode and decoder ...
Page 991: Control Register Map
N9H26 Technical Reference Manual 5.29.4 Control Register Map R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written Register Address Description Reset Value MDCT_BA = 0xB100_4000 MDCTPAR MDCT_BA+0x00 0x0000_0001 MDCT Parameter Register MDCTCTL MDCT_BA+0x04 0x0000_0000...
Page 992: Register Description
N9H26 Technical Reference Manual 5.29.5 Register Description MDCT Parameter Register Register Address Description Reset Value MDCTPAR MDCT_BA+0x00 0x0000_0001 MDCT Parameter Register Reserved Reserved Window mode Reserved Reserved DecoderEN Bits Descriptions [31:19] Reserved Reserved Window mode [18:16] Window mode 2 = window 2048 5 = window 256 [15:1] Reserved...
Page 993 N9H26 Technical Reference Manual MDCT Control Register Register Address Description Reset Value MDCTCTL MDCT_BA+0x04 0x0000_0000 MDCT Control Register Reserved Reserved Reserved Reserved MDCTEN Bits Descriptions [31:1] Reserved Reserved MDCT Enable MDCTEN 0 = MDCT IDLE 1 = MDCT Enable Publication Release Date: Sept. 10, 2018 - 993 - Revision V1.01...
Page 994 N9H26 Technical Reference Manual MDCT STATES Register Register Address Description Reset Value MDCTSTATE MDCT_BA+0x08 0x0000_0000 MDCT STATES Register Reserved Reserved Reserved Reserved Reorder_busy Post_busy FFT_busy Pre_busy Bits Descriptions [31:4] Reserved Reserved Reorder state Reorder_busy 0 = Reorder IDLE 1 = Reorder Busy Post twiddle state Post_busy 0 = Post Twiddle IDLE...
Page 995 N9H26 Technical Reference Manual MDCT Interrupt Register Register Address Description Reset Value MDCTINT MDCT_BA+0x0C 0x0000_0000 MDCT Interrupt Register Reserved Reserved DMA OUT INT DMA IN INT MDCT INT ENABLE ENABLE ENABLE Reserved Reserved DMA OUT INT DMA IN INT MDCT INT Bits Descriptions [31:19]...
Page 996 N9H26 Technical Reference Manual DMA Read Start Address Register Register Address Description Reset Value DMA_RADDR MDCT_BA+0x10 0x0000_0000 DMA Read Start Address Register DMA Read Start Address DMA Read Start Address DMA Read Start Address DMA Read Start Address Bits Descriptions [31:0] DMA_RADDR DMA Read Start Address...
Page 997 N9H26 Technical Reference Manual DMA Write Start Address Register Register Address Description Reset Value DMA_RADDR MDCT_BA+0x14 0x0000_0000 DMA Write Start Address Register DMA Write Start Address DMA Write Start Address DMA Write Start Address DMA Write Start Address Bits Descriptions [31:0] DMA_WADDR DMA Write Start Address (word alignment)
Page 998 N9H26 Technical Reference Manual DMA Direction Register Register Address Description Reset Value DMA_DIRECTION MDCT_BA+00x18 0x0000_0000 DMA Direction Register Reserved Reserved Reserved Reserved DMA_DIRECT Bits Descriptions [31:1] Reserved Reserved DMA DIRECTION DMA_DIRECT 0 = Read data in 1 = Write data out Publication Release Date: Sept.
Page 999 N9H26 Technical Reference Manual DMA STATES Register Register Address Description Reset Value DMA_STATE MDCT_BA+0x1C 0x0000_0000 MDCT Control Register Reserved Reserved Reserved Reserved DMA_STATE Bits Descriptions [31:1] Reserved Reserved DMA STATE DMA_STATE 0 = DMA IDLE 1 = DMA Enable Publication Release Date: Sept. 10, 2018 - 999 - Revision V1.01...
Page 1000 N9H26 Technical Reference Manual DMA DATA LENGTH Register Address Description Reset Value DMA_LENGTH MDCT_BA+0x20 0x0000_0000 DMA DATA LENGTH Reserved Reserved Reserved DMA_LENGTH DMA_LENGTH Bits Descriptions [31:12] Reserved Reserved [11:0] DMA_LENGTH DMA DATA LENGTH DATA FLOW Program DMA_RADDR , DMA_DIRECTION, DMA_LENGTH, ENABLE DMA_STATE (move data from SDRAM) Check DMA IN INT , if DMA IN INT = 1 , DMA_done, write 1 to clear Program Window mode, MDCT mode (encoder/decoder)

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