IBM 4840-563 System Reference Manual page 44

1. Determine the PM (Power management) Base IO address. This is done by reading the PCI configuration
register 40h-43h of the LPC Interface PCI device. The LPC device is on PCI bus 0, device 1Fh, function
0.
2. 2. Perform logical AND of the lowest word of what is read above with FFFEh. In other words, make the
lowest bit = 0 (it always reads a 1 for some reason.)
3. Add 2Bh to the PM Base IO address.
4. Do an IO read of this address and check bit 4 for the Presence Sensor status. A '1' means the sensor is
detecting, and a '0' means the sensor is not detecting.
Function 0 Interrupt Status Register (Read/Write) Register offset 01h
Bit 0: Status of Presence Sensor detection interrupt (0: No Interrupt, 1: Interrupt Asserted)
An interrupt will be generated (if the presence function is enabled) if the pin E_DETECT# goes low ("0").
Software has to clear the interrupt status register by writing a 0 to bit 0 after the interrupt service is done. This
register is a direct mapped register to the Function 0 PCI configuration space at offset 41h. The power-up
default value of this register is 00h.
EEPROM Control Registers (Read/Write) Register offset 02h
D7 D6 D5 D4 D3 D2 D1 D0 Function
x x x x x x x Y 1: Read EEPROM contents into ASIC memory.
x x x x x x Y x 1: Write ASIC memory contents into EEPROM.
Note that all EEPROM is automatically loaded into ASIC RAM upon power-on reset
(through PCI reset signal)
By writing a "1" to bit 0 of EEPROM Control Register, the ASIC will transfer (read) the contents (128 bytes) of
EEPROM from the physical chip (through pins E_SCL and E_SDA) to the internal RAM in the ASIC. The bit 0
will remain read as "1" until the read operation (i.e. shifting of EEPROM data to RAM) is completed, this bit 0
will be cleared (i.e. set to "0"). So, software should monitor this bit 0, as RAM data only valid when it is "0". By
writing a "1" to bit 1 of EEPROM Control Register, the ASIC will transfer (write) the contents in the internal
RAM (128 bytes) to the external EEPROM (through pins E_SCL and
E_SDA). The bit 1 will remain as "1", but once the write operation (i.e. shifting of RAM data to EEPROM 0) is
completed, this bit 1 will be cleared (i.e. set to "0"). So, software should monitor this bit 1 as write operation
only complete when this bit is "0".
UART Control Registers (Read/Write) Register offset 03h
Default Value Of UART Control Register (before EEPROM is loaded): F0h
(The above default value above is the value of UART Control Register in the case when Configuration
EEPROM is not loaded or can not be loaded for any reason).
Bit Function Default (Before EEPROM loaded)
7 UART 0: 1- Enabled, 0 – Disable 1
6 UART 1: 1- Enabled, 0 – Disable 1
5 UART 2: 1- Enabled, 0 – Disable 1
4 UART 3: 1- Enabled, 0 – Disable 1
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