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Teledyne Lecroy QPHY-DP2-SOURCE Instruction Manual

Displayport 2.1/1.4 source compliance test software
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QPHY-DP2-SOURCE
DisplayPort 2.1/1.4 SOURCE Compliance Test Software
Instruction Manual
and
Method of Implementation (MOI)
Relating to:
MAUI
v.10.9.x.x and later
®
QualiPHY
v.10.9.x.x and later
®

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Summary of Contents for Teledyne Lecroy QPHY-DP2-SOURCE

  • Page 1 QPHY-DP2-SOURCE DisplayPort 2.1/1.4 SOURCE Compliance Test Software Instruction Manual Method of Implementation (MOI) Relating to: MAUI v.10.9.x.x and later ® QualiPHY v.10.9.x.x and later ®...
  • Page 2 Customers are permitted to duplicate and distribute Teledyne LeCroy documentation for internal training purposes. Unauthorized duplication is strictly prohibited. Teledyne LeCroy and other product or brand names are trademarks or requested trademarks of their respective holders. Information in this publication supersedes all earlier versions. Specifications are subject to change without notice.

  • Page 3: Table Of Contents

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI Table of Contents Introduction Software Installation and Setup Installing QualiPHY Application ............................... 2 Activate Components in MAUI ................................ 2 Install Third-party Software ................................2 Set Up Secondary Display (optional) .............................. 3 Set Up the QualiPHY Application ..............................
  • Page 4 QPHY-DP2-SOURCE Table of Figures Figure 1. Test Point definition................................9 Figure 2. DP2.1/1.4 SOURCE test connection diagram......................11 Figure 3. Connection diagram for four-lane testing using the RC-8SPDT-A18 RF Switch..........13 Figure 4. 4-Port S-parameter indicators for TX testing......................17 Figure 5.

  • Page 5: About This Manual

    This manual also serves as Teledyne LeCroy’s electrical physical layer Method of Implementation (MOI) for the DisplayPort 2.0 compliance test program. Official MOI approval for these standards is governed by VESA (Video...
  • Page 6 QPHY-DP2-SOURCE...

  • Page 7: Introduction

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI Introduction QualiPHY is highly automated compliance test software meant to help you develop and validate the PHY (physical- electrical) layer of a device, in accordance with the official documents published by the applicable standards organizations and special interest groups (SIGs).

  • Page 8: Software Installation And Setup

    QPHY-DP2-SOURCE Software Installation and Setup QualiPHY is a Windows-based application that can be configured with one or more serial data compliance components. Each compliance component is purchased as a software option. The software is supported on most WaveMaster 8 Zi-B, WaveMaster 8000HD and LabMaster oscilloscopes with: 25 GHz or greater bandwidth for DP 2.1 128b/132b testing...

  • Page 9: Set Up Secondary Display (Optional)

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI Set Up Secondary Display (optional) Teledyne LeCroy recommends running QualiPHY on an oscilloscope with a secondary display attached. This allows the waveform and measurements to be shown on the oscilloscope LCD display while the QualiPHY application and test results are displayed on a second monitor.

  • Page 10: Connection Tab

    QPHY-DP2-SOURCE Connection Tab The Connection tab shows the Address of the oscilloscope is local host 127.0.0.1 when QualiPHY is run from the oscilloscope. If you are running QualiPHY from a remote computer, this will show the network IP address of the oscilloscope to which QualiPHY is currently connected.
  • Page 11 DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI Report Tab The Report tab contains settings related to report generation. Choose a Reporting behavior of: “Ask to generate a report after tests”—you’ll be prompted to create a new file for each set of test results. •...

  • Page 12: Set Up Remote Control (Optional)

    QPHY-DP2-SOURCE Set Up Remote Control (optional) Usually, the oscilloscope is the host computer for the QualiPHY software, and all models that meet the acquisition requirements will also meet the host system requirements. However, the QualiPHY software can be executed from a remote host computer.

  • Page 13: Displayport 2.1/1.4 Source (Tx) Test Moi Required Equipment

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI DisplayPort 2.1/1.4 SOURCE (Tx) Test MOI Required Equipment Test Instruments Real-time oscilloscope, one of the following: SDA/WaveMaster 8250HD for all data rates • SDA/WaveMaster 8160HD for data rates: • DP 2.1 UHBR10 DP 2.1/1.4 HBR3, HBR2, HBR, RBR SDA/WaveMaster 8130HD for data rates DP 2.1/1.4 HBR2, HBR, RBR •...

  • Page 14: Required Software

    Installed on oscilloscope: Latest version QualiPHY compliance software • Latest MAUI® firmware (must match QualiPHY to second decimal) • QPHY-DP2-SOURCE option key • DP-AUX TDMP option key, required for AUX Eye compliance test • Recommended Software The following are helpful for DP and USB-C debug but not required for compliance testing.

  • Page 15: Displayport 2.1/1.4 Source (Tx) Measurements

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI DisplayPort 2.1/1.4 SOURCE (Tx) Measurements Test Point Definition Figure 1. Test Point definition. Test Point 2 (TP2) is defined as the connector of an upstream port and is accessed using a USB-C, full-size DP, or mDP plug test point adapter (TPA-P) Test Point 3 (TP3) is defined as the test point at the connector interface on the downstream side of a USB-C, full- size DP, or mDP cable.
  • Page 16 QPHY-DP2-SOURCE DisplayPort 2.1/1.4 SOURCE 8b/10b Measurements (CTS Section 3) CTS Measurement Test Point Test Pattern 3.1 EYE Diagram Test (Normative) TPS4/CP2520 (HBR3) TP3_EQ PRBS7 (HBR2/HBR/RBR) 3.2 HBR/RBR Non-PE Level Verification Test (Normative) PRBS7 3.3 HBR/RBR PE Level and Max Differential Pk-Pk Voltage Test...

  • Page 17: Displayport 2.1/1.4 Multi-Lane Test Setup

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI DisplayPort 2.1/1.4 Multi-lane Test Setup Note: All example tests are shown using ML0/ML1 testing with results from both lanes. If only one lane is being tested, then only one lane at a time will be displayed on the oscilloscope. DisplayPort Source devices can support one, two or four transmitter lanes.
  • Page 18 QPHY-DP2-SOURCE 128/132b UHBR Data Rates These rates are tested using the DisplayPort 2.0 script. Using WaveMaster 8000HD/LabMaster 10 Zi-A Oscilloscopes For WaveMaster/SDA 8000HD and LabMaster 10 Zi-A Oscilloscopes running at full sample rate on all channels: When only one lane (Lane0, Lane1, Lane2, or Lane3) is selected from the Setup Tab, the lane under test •...

  • Page 19: Figure 3. Connection Diagram For Four-Lane Testing Using The Rc-8Spdt-A18 Rf Switch

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI Four-lane Testing with RC-8SPDT-A18 RF Switch (8b/10b only) QualiPHY can perform testing of all four lanes on a four-channel oscilloscope by using the Mini-Circuits RC-8SPDT-A18 RF Switch. To configure four-lane testing, set the “Number of Lanes” variable to 4. This variable setting signals to QualiPHY to use the switch matrix.

  • Page 20: Automated Device Control

    QPHY-DP2-SOURCE Automated Device Control DisplayPort Configuration Data (DPCD) Automation Requests The DisplayPort CTS mandates that a Source’s firmware supports test automation by writing requests to a reference Sink’s DPCD registers as defined in Table 2-232 of the DisplayPort 2.1 specification. The reference Sink is represented by the AUX Controller in Figure 2.
  • Page 21 DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI Write Request Sequence Write to Sink DPCD register address …with data value: Set Training 0010Bh When 00108h is 8b/10b (01h): Pattern LINK_QUAL_LANE0_SET 03h – PRBS7 • 01h – D10.2/TPS1 • 0010Ch 04h –...

  • Page 22: Tpa And Test Cable De-Embedding (Optional)

    QPHY-DP2-SOURCE Automating Testing with the Unigraf DPR-100 (8b/10b only) QualiPHY includes the capability of automating the configuration of the DUT by using a Unigraf DPR-100 Reference Sink in an “AUX Controller” mode. In order to use the automation feature: The DPR-100 must be licensed to operate in this mode by purchasing the SW option model 065047 from •...

  • Page 23: Figure 4. 4-Port S-Parameter Indicators For Tx Testing

    Also indicated is the .s4p file from the TPA being used (referred to as Test Fixture). S-parameters for both the Test Cables and the TPA are imported into QPHY-DP2-SOURCE as variables. Figure 4. 4-Port S-parameter indicators for TX testing.

  • Page 24: Initiating Displayport 2.1/1.4 Source Test Sessions

    “Host Program”). In this mode of operation, QualiPHY uses a simple handshaking protocol to send messages to the host program. This is implemented using a synchronization file. Note that when in HPC mode, QualiPHY will halt execution while waiting for the sync file to be deleted. Contact Teledyne LeCroy technical support for more information about implementing HPC.
  • Page 25 DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI 4. On the Wizard, click the Configuration button and select the test configuration you wish to run. Different configurations are designed to set key variables as required for testing different types of DUTs. Note: Standard configurations are locked and cannot be changed.

  • Page 26: Displayport 2.1 Source 128B/132B Tests

    QPHY-DP2-SOURCE DisplayPort 2.1 SOURCE 128b/132b Tests 128b/132b tests are executed by choosing the DisplayPort 2.0 Source script in QualiPHY. 4.2 Source Preset and CTLE-DFE Compliance Declaration (Normative) It is mandated by the VESA DP2.1 compliance program that the following parameters be included with the Source’s CDF (Compliance Declaration Form) that is submitted to Authorized Test Centers (ATCs) for testing.
  • Page 27 DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI Run TP3 tests with the ‘CTLEDFE_presets To Test’ variable is set to TP2BEST. TP3_EQ measurements will be made with the TP2_Best preset and CTLE values are scanned for best Eye Area based on CTLE/DFE calibration. The range of CTLEs to use for the test is set by the variable CTLE Values for CTLE/DFE Calibration.

  • Page 28: Figure 5. Screen And Report For 4.2 128B/132B Presetbest, And Ctle/Dfebest Test

    QPHY-DP2-SOURCE This will result in a report with the best Eye Area and the CTLE and Preset used for each Lane and Data rate that can be reported in the CDF. The following example reports P7 as the best TP2 preset when testing Preset 1, 4, and 7. The best TP3 CTLE/DFE occurs with a CTLE value of -3dB, and the CTLE/DFE scan also reveals that the best eye at TP3 is also P7.

  • Page 29: Figure 6. Screen And Report For 4.3 128B/132B Transmitter Equalization Test

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI 4.3 UHBR Source Transmitter Equalization (Normative) Performs the Transmitter Equalization tests over a user-selectable set of presets. For each preset, measurements are taken with preshoot and deemphasis on and off, and the preshoot and deemphasis values for the preset are measured and determined as per the test specification.

  • Page 30: Figure 7. Screen And Report For 4.4 128B/132B Ssc Unit Interval Min/Max Test

    QPHY-DP2-SOURCE 4.4 UHBR Bit Rate (Normative) and Unit Interval (Informative) Bit Rate MinMax (Normative) The UI Minima test confirms that the minimum of the set of local minima in the waveform of boxcar-averaged UI times is no more than a lower limit, and that the maximum of the set of local minima is no more than an upper limit.

  • Page 31: Figure 8. Screen And Report For 4.5 128B/132B Ssc Down Spread Range Test

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI 4.5 UHBR SSC Down Spread Range, Rate, Phase Deviation and Slew Rate (Normative) Performs the SSC tests, including SSC Downspread Range, SSC Downspread Rate, SSC Phase Deviation and SSC Slew Rate. These measurements are performed on the same acquisition as for the UI Minimum test. A 27 Mpt PRBS31 waveform is used for this test.

  • Page 32: Figure 9. Report For Ssc Down Spread Rate Test

    QPHY-DP2-SOURCE SSC Down Spread Rate Measurement As in the SSC down spread range measurement, the SSC down spread rate is calculated dynamically using a uniform moving average filter procedure with a window size of 3000 symbols. Figure 9. Report for SSC Down Spread Rate test.

  • Page 33: Figure 11. Screen And Report For 4.5 128B/132B Ssc Slew Rate Test

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI SSC Slew Rate The SSC slew rate is extracted from the transmitted signal over measurement intervals of 0.5 us and extracted from the signal phase after applying a 2nd order Low-Pass-Filter (LPF) with the 3 dB point at 5 MHz. Figure 11.

  • Page 34: Figure 12. Test Setup For 4.6 128B/132B Retimer Frequency Variation Test

    QPHY-DP2-SOURCE 4.6 TX Frequency Variation Training Performs Transmitter Frequency Variation Training test, which measures the SSC variation during clock-switch. Tx Frequency Variation Training Setup Figure 12. Test setup for 4.6 128b/132b retimer Frequency Variation test. LTTPR Clock Switch Sequence UHBR Tx Frequency Variation Training requires the LTTPR Re-timer Clock Switch Compliance Test Sequence defined in section 3.6.10 of the DisplayPort 2.1 specification:...
  • Page 35 DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI Sequence DPCD register address …with data value: 1. Source Writes 0010Bh to 0010Eh When 00108h is 128b/132b (02h): Initiate Clock LINK_QUAL_LANEx_SET [7] LTTPR CLOCK SWITCH link qual test SET =1 Switch tests [6:0] 08h - TPS1 with TPS1 Patter...

  • Page 36: Figure 13. Screen And Report For 4.6 128B/132B Tx Frequency Variation Test

    QPHY-DP2-SOURCE Figure 13. Screen and report for 4.6 128b/132b TX Frequency Variation test.

  • Page 37: Figure 14. Screen And Report For 4.7 128B/132B Tp2 Eye Test

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI 4.7 UHBR TP2 EYE at 1E-6 BER (Normative) Performs the Eye Diagram Mask test at TP2 on a PRBS31 waveform with ~1 million UI. Figure 14. Screen and report for 4.7 128b/132b TP2 Eye test.

  • Page 38: Figure 15. Screen And Report For 4.8 128B/132B Tp2 Jitter Tests

    QPHY-DP2-SOURCE 4.8 UHBR TP2 Jitter at 1E-9 BER (Normative/Informative) This selection performs the jitter tests at the test point TP2 on a 40 Mpt PRBS15 waveform, including TJ, UJ, UDJ, and UDJ_LF (Normative) and RJ and DDJ (Informative). Jitter methodologies for DisplayPort 2.0 are adopted from the USB4 specification. However, they are run with a BER (Bit Error Rate) of e-9.

  • Page 39: Figure 16. Screen And Report For 4.9 128B/132B Ac Common Mode Test

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI 4.9 UHBR AC Common Mode Noise (Informative) Performs the AC Common Mode test, which compares the pk-pk of the common-mode signal to the limit in the specification. Figure 16. Screen and report for 4.9 128b/132b AC Common Mode test.

  • Page 40: Figure 17. Screens And Report For 4.10 128B/132 Tp3_Eq Eye Mask Test

    QPHY-DP2-SOURCE 4.10 UHBR TP3_EQ EYE at 1E-6 BER (Normative) Performs the Eye Diagram Mask test at TP3 on a PRBS31 waveform with ~1 million UI. Note: To run this test, the CTLE/DFE calibration must be performed first. Figure 17. Screens and report for 4.10 128b/132 TP3_EQ Eye Mask test.

  • Page 41: Figure 18. Screen And Report For 4.11 128B/132B Jitter Tests

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI 4.11 UHBR TP3_CTLE Jitter at 1E-9 (Informative) Jitter methodologies for DisplayPort 2.0 are adopted from the USB4 specification. However, they are run with a BER (Bit Error Rate) of e-9. Figure 18. Screen and report for 4.11 128b/132b Jitter tests.

  • Page 42: Displayport 2.1 Source 128B/132B Test Variables

    QPHY-DP2-SOURCE DisplayPort 2.1 SOURCE 128b/132b Test Variables Basic Group DUT Type Select the DUT type. Note that the limits used can depend on the DUT type selected. Connector Type Select the connector type of the source under test. Lane Flip Lane flip setting for Type-C.
  • Page 43 DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI Analysis Method Select the software used for waveform analysis. Currently only LeCroy is available. Is SSC on or off? Select “On” if the source under test supports SSC. Bitrate Setup Group Enable testing at 10 GB/s? Set this variable to “Yes”...
  • Page 44 "Single-ended" if using normally formatted single-ended S-parameters "Mixed-mode" if using S-parameters with mixed-mode ports. Note: Teledyne LeCroy strongly recommends using single-ended S-parameters to avoid confusion. LN Cable (+) De-embedding File Path and LN Cable (-) De-embedding File Path Path to the S2P Touchstone file used for de-embedding the respective Lane 0 to 3 (+) or (-) cable.
  • Page 45 DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI Debugging Options Group User CTLE Value Select a value to use when running jitter and eye tests for "debug" purposes. If a value other than "CTLE/DFE Calibrated Value" is selected, this value will be used instead of the value found in the CTLE/DFE calibration, and the requirement in the Eye and Jitter tests to run the CTLE/DFE calibration is not enforced.
  • Page 46 QPHY-DP2-SOURCE Acquire SQ2 waveforms? Select "Yes" to acquire an SQ2 waveform. This might be needed for the jitter test if TJ fails. Acquire waveforms for TXEQ test? Select "Yes" to acquire the SQ128 waveforms at all presets with preshoot and deemphasis on/off for the Transmitter Equalization tests.
  • Page 47 DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI CTLE/DFE Presets to Test Enter a comma-delimited list of the preset numbers to test, or enter the word “All” to test all presets. For example: “1,2,3” tests presets 1, 2 and 3 in that order. Enter the word “TP2BEST”...

  • Page 48: Displayport 2.1 Source 128B/132B Test Limits

    Set the time in S to wait for the AUX trigger before issuing a timeout error. DisplayPort 2.1 SOURCE 128b/132b Test Limits The default installation of QPHY-DP2-SOURCE contains only one limit set, called “Default”, containing the limits specified by the VESA DisplayPort PHY Compliance Test, Specification Version 2.0. The limits for each value tested are encoded in or computed by the script and cannot be changed.

  • Page 49: Displayport 2.1/1.4 Source 8B/10B Tests

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI DisplayPort 2.1/1.4 SOURCE 8b/10b Tests 8b/10b tests are executed by choosing the DisplayPort 1.4 Source script in QualiPHY. 3.1 Eye Diagram at TP2 and TP3 (Normative) This test verifies that the eye diagram is within the conformance limits as defined in section 3.1 EYE Diagram Test of the VESA DisplayPort 2.1 PHY CTS.

  • Page 50: Figure 20. Screens For 3.1 8B/10B Eye Diagram Test

    QPHY-DP2-SOURCE TP3_EQ EYE (using VESA DFE) TP2_CTLE EYE Figure 20. Screens for 3.1 8b/10b Eye Diagram test.

  • Page 51: Figure 21. Screen For 3.2 8B/10B Hbr/Rbr Non-Pe Level Test

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI HBR/RBR Non-PE Level Verification (Normative) The purpose of this test is to verify that the non pre-emphasis level is within the conformance limits as specified in section 3.2 Non Pre-emphasis Level Test of the VESA DisplayPort 1.4a PHY CTS. The test uses the PRBS7 pattern. Figure 21.

  • Page 52: Figure 22. Screen For 3.3 8B/10B Hbr/Rbr Pe Level Test

    QPHY-DP2-SOURCE HBR/RBR PE Level Verification and Maximum Differential Peak-to-Peak Voltage (Normative) The purpose of this test is to verify the accuracy of the pre-emphasis settings, the non-transition voltage levels, and the maximum peak-to-peak differential voltage. Figure 22. Screen for 3.3 8b/10b HBR/RBR PE Level test.

  • Page 53: Figure 23. Screen For 3.4 8B/10B Hbr3/Hbr2 Pe Level And Equalization Test

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI HBR3/HBR2 PE Level and Equalization Verification (Normative) This test utilizes FFT to make spectral measurements that are used to calculate ratios of voltage swings and deltas of transmit emphasis. These are used to verify the monotonicity of the output settings and to verify that they meet the requirements specified in section 3.4 of the VESA DisplayPort 2.1/1.4 PHY CTS.

  • Page 54: Figure 25. Screen For 3.6 8B/10B Inter-Pair Skew Test

    QPHY-DP2-SOURCE Inter-pair Skew, Highest Supported Bit Rate (Informative) The purpose of this test is to verify that worst inter-pair skew is within the conformance limits as defined in section 3.6 Inter-Pair Skew Test of the VESA DisplayPort 2.1/1.4 PHY CTS.

  • Page 55: Figure 26. Screen For 3.7 8B/10B Intra-Pair Skew Test

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI Intra-pair Skew, Highest Supported Bit Rate (Informative) This is an informative test to verify that Intra-pair skew is within the conformance limits as specified in section 3.7 Intra-Pair Skew Test (Informative) of the VESA DisplayPort 2.1/1.4 PHY CTS. Figure 26.

  • Page 56: Figure 27. Screen For 3.8 8B/10B Ac Common Mode Test

    QPHY-DP2-SOURCE AC Common Mode Noise (Informative) 3.8.1 HBR3 3.8.2 HBR2, HBR, RBR This informative test evaluates the AC common mode noise on each differential pair (lane) of the DisplayPort main link and allows the user to evaluate this parameter per recommendation in the VESA DisplayPort 2.1/1.4 PHY CTS.

  • Page 57: Figure 28. Screen For 3.9 8B/10B Non-Isi Jitter Test

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI Non-ISI Jitter Measurement (Normative) This test measures the DisplayPort main link non-ISI jitter for all lanes at HBR and RBR. The measurements are evaluated per the criteria specified in the VESA DisplayPort 1.4a PHY CTS. Figure 28.

  • Page 58: Figure 29. Screen For 3.11.1 8B/10B Jitter Test

    QPHY-DP2-SOURCE 3.11.1 TJ/RJ/DJ Measurements HBR3 TP3_CTLE (Normative), HBR2 TP3_EQ (Normative), HBR, RBR TP2 (Normative) HBR TP3_EQ (Informative) This test evaluates Total Jitter (Tj) and Deterministic Jitter (Dj) present on all differential pairs of the main link. The measurements are evaluated per the criteria specified in the VESA DisplayPort 1.4a PHY CTS.

  • Page 59: Figure 30. Screen For 3.11.2 8B/10B Jitter

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI 3.11.2 Jitter Measurements: HBR3 Tj/Non-ISI Jitter (Normative) This test evaluates the Tj and non-ISI jitter on the main link at HBR3 bit rate. The measurements are evaluated per the criteria referenced in the VESA DisplayPort 1.4a PHY CTS. Figure 30.

  • Page 60: Figure 31. Screen For 3.11.3 8B/10B Jitter Test

    QPHY-DP2-SOURCE 3.11.3 Jitter Measurements: HBR2 D10.2 Tj/Rj/Dj (Normative) This test evaluates the Tj and non-ISI jitter on the main link at HBR2 bit rate, using the D10.2-bit pattern. The measurements are evaluated per the criteria specified in the VESA DisplayPort 1.4a PHY CTS as revised by DP 1.4a PHY CTS rev 1.0 SCR d5.

  • Page 61: Figure 33. 3.12 8B/10B Ssc Modulation Frequency Test

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI 3.13 Spread-Spectrum Modulation Frequency, Highest Supported Bit Rate (Normative) This test verifies that the SSC modulation frequency is with the limits specified in the VESA DisplayPort 1.4a PHY CTS section 3.13. Figure 33.

  • Page 62: Displayport 2.1/1.4 Source 8B/10B Test Variables

    QPHY-DP2-SOURCE DisplayPort 2.1/1.4 SOURCE 8b/10b Test Variables Bitrate Setup Group For users who wish to only test a subset of the DisplayPort 1.4 bit rates, this group includes variables to facilitate choosing the specific rates to test and to define the highest supported rate. Intra-pair and Inter-pair skew are to be tested at the highest supported rate.
  • Page 63 DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI Save Waveform Setup Group Variables in this group control QualiPHY behavior for saving and recalling waveforms. QPHY-DisplayPort 1.4 tests can run on a set of stored waveforms or on live waveforms. Demo Mode Runs the tests as a demonstration using saved waveforms.
  • Page 64 QPHY-DP2-SOURCE HBR3 DFE, Worst Case/Zero Length Scenarios Setup Group Setup for the optional VESA DFE Tool for test 3.1. Also, test IDs 3.1 and 3.11.1 can be performed in two scenarios: with and without a worst-case cable being emulated. The CTS stipulates that the test can pass if one passing combination of swing and pre-emphasis meets the mask/limit test.
  • Page 65 DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI DPR-100 COM Port When using a DPR-100, Windows will assign a COM port for the DPR-100. The port assigned can be identified by opening up the Windows Device Manager. Multiple ports might be shown; in such cases, use the port that does not display a yellow exclamation mark.

  • Page 66: Appendix A: Using Host Program

    QPHY-DP2-SOURCE Host Program Control Group Variables used when running tests in Host Program Control (HPC) mode. See Appendix A: Using Host Program Control Mode for implementing HPC and the Sync file. Host Program Control Sync File Name Full path to the HPC Sync file (e.g., C:\DisplayPort_sync_file.xml).
  • Page 67 DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI Swing and Pre-emphasis Specific to Individual Tests The configuration of Swing (level) and Pre-emphasis variables is handled globally for the HBR2 tests, but needs to be specified for most other tests. Variables in this group are for tests that require user input for level and/or pre- emphasis value.

  • Page 68: Displayport 2.1/1.4 Source 8B/10B Test Limits

    QPHY-DP2-SOURCE AUX Index Index (number) of AUX transaction to be tested, corresponding to the row number of the Manchester Serial Decode table. AUX Tests Input Channel Type Inputs used for AUX signal tests, high-bandwidth (InputB) or low-bandwidth (InputA). This should correspond to the setting on the oscilloscope Channel dialog.

  • Page 69: Dp-Aux Aux Tx Test Moi

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI DP-AUX AUX Tx Test MOI DP-AUX AUX Tx tests can be run using either the DisplayPort 1.4 Source or the DisplayPort 2.0 Source script. AUX Channel Tx Measurements 11.5 AUX_CH Slew Rate Test (Normative) 16 SYNC pulses 11.3 AUX_CH (Manchester-II) EYE Test (Normative) 16 SYNC pulses...

  • Page 70: Figure 36. Screen For 11.1 Aux Eye Test

    QPHY-DP2-SOURCE 11.1 AUX_CH (Manchester-II) EYE Test (Normative) The purpose of this test is to verify that AUX channel amplitude and timing variables are within the conformance limits as defined in section 11.1 AUX Channel Eye Test of DisplayPort 2.1 C...

  • Page 71: Figure 37. Screen For 11.5 Aux Channel Slew Rate Test

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI 11.5 Aux Channel Slew Rate Test Aux Channel (Normative) This test measures the Aux Channel signal rise and fall times, and verifies that these transitions do not exceed the maximum slew rate referenced in the VESA DisplayPort 2.1 PHY CTS. Figure 37.

  • Page 72: Using Qualiphy

    QPHY-DP2-SOURCE Using QualiPHY This section provides an overview of the QualiPHY user interface and general procedures. QualiPHY Test Process 1. Before beginning any test or data acquisition, warm the oscilloscope for at least 20 minutes. Oscilloscope calibration is automatically performed by the oscilloscope software; no manual calibration is required.

  • Page 73: Generating Reports

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI Generating Reports The QualiPHY software automates report generation. On the wizard dialog, go to General Setup > Report to pre- configure reporting behavior. You can also manually launch the Report Generator from the wizard dialog after a test is completed.

  • Page 74: Customizing Qualiphy

    QPHY-DP2-SOURCE Customizing QualiPHY The pre-loaded configurations cannot be modified. However, you can create your own test configurations by copying one of the pre-loaded configurations and modifying it. Note: This may also be required when you need to modify a variable from one of the standard configurations.

  • Page 75: Select Tests

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI Select Tests On the Test Selector tab, check the tests that make up the configuration. Each test is defined by the VESA DisplayPort standard. A description of each test is displayed when it is selected. Edit Variables The Setup tab contains the most commonly modified variables.
  • Page 76 QPHY-DP2-SOURCE The Variable Setup tab contains a full list of test variables. To modify a variable here: 1. Select the variable on the Variable Setup tab, then click Edit Variable. (You can also choose to Reset to Default at any time.)
  • Page 77 DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI Edit Test Limits The Limits Manager shows the settings for every test limit in a limit set. Those in the default set are the limits defined by the standard. To create a custom limit set: 1.

  • Page 78: X-Replay Mode

    QPHY-DP2-SOURCE X-Replay Mode The X-Replay mode window is an advanced (“developer”) view of QualiPHY. The tree in the upper-left frame enables you to navigate to processes in the test script, in case you need to review the code, which appears in the upper-right frame.

  • Page 79: Using Host Program Control Mode

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI Using Host Program Control Mode Host Program Control Mode (HPC) is a new feature that allows QualiPHY to be started by a user’s host program with a number of arguments. Once running, a simple “Sync File” protocol is used by QualiPHY to signal the host program.

  • Page 80: Host Program Elements Needed To Control The Qualiphy Script

    QPHY-DP2-SOURCE Host Program Elements Needed to Control the QualiPHY Script Launching QualiPHY (XReplay.exe) The Host program needs to launch the QualiPHY application (the actual program is named XReplay.exe) with the following command line, including arguments for DP: C:\Program Files(x86)\LeCroy\XReplay\XReplay.exe –A –R –E –WIZARD –TECH:tecDPORT\DPORT2TX –CONFIG:HostControlTest –N:IP Address...
  • Page 81 DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI Sample Host Program This sample VBS host program performs all the essential tasks involved in launching and synchronizing with the QualiPHY DP test script. It is shown below and referred to in the text following it. ‘DP example Host Program Control Script no actions Set shell = CreateObject("Wscript.Shell") Set fso = CreateObject("Scripting.FileSystemObject")
  • Page 82 QPHY-DP2-SOURCE detail = Node.text Set Node = xmlDoc.documentElement.selectSingleNode("mode") mode = Node.text Set Node = xmlDoc.documentElement.selectSingleNode("TestPattern") TestPattern = Node.text Set Node = xmlDoc.documentElement.selectSingleNode("BitRate") BitRate = Node.text Set Node = xmlDoc.documentElement.selectSingleNode("SSC") SSC = Node.text Set Node = xmlDoc.documentElement.selectSingleNode("Pre-emphasis") Pre-emphasis = Node.text Set Node = xmlDoc.documentElement.selectSingleNode("Swing") Swing = Node.text...

  • Page 83: Hpc Sync File

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI HPC Sync File Sync File Tags The Host Program Control synchronization file includes the following tags: connectionsReq: describes the connections that should be made. • When instructed to, connect 2 lanes connect /route the lanes to the oscilloscope such that (+) lines are to channels C1 and C3, and (-) lines to C2 and C4.
  • Page 84 QPHY-DP2-SOURCE Sample XML Sync Files Request to change the connections <TestConfig> <Pre-emphasis/> <Number_of_Lane>4</Number_of_Lane> <Swing/> <detail>Change connections</detail> <mode/> <error>0</error> <TestPattern/> <connectionsReq>Lane1,Lane2,</connectionsReq> <BitRate/> <SSC/> </TestConfig> Request to change signal characteristics <TestConfig> <Pre-emphasis>Pre-emphasis0</Pre-emphasis> <Number_of_Lane>1</Number_of_Lane> <Swing>Swing0</Swing> <detail>Signal Attribute Change</detail> <Pre-emphasis0_Value>0.0</Pre-emphasis0_Value> <mode>eDP</mode> <error>0</error> <Swing0_Value>200</Swing0_Value> <TestPattern>PLTPAT</TestPattern>...

  • Page 85: Appendix A: Testing Displayport 2.1 Source Return Loss (Informative)

    Tx Return Loss (RL) and Integrated Return Loss are required for DP Source testing. DisplayPort Return Loss measurements are not automated by QPHY-DP2-Source, however Return Loss measurements can be made using the WavePulser 40iX High-speed Interconnect Analyzer. Contact your Teledyne LeCroy representative for information about the latest developments.
  • Page 86 QPHY-DP2-SOURCE 3. On the WavePulser, in ‘single ended’ mode, capture S12.s2p and S34.s2p S-parameter files. 4. Save the .s2p S-parameter files. 5. Repeat above to test Lane2/Lane3...

  • Page 87: Appendix B: Using Dp-Aux Tdmp To Verify/Debug Dpcd Register Settings

    Appendix B: Using DP-AUX TDMP to Verify/Debug DPCD Register Settings QPHY-DP2-SOURCE automates the setup through supported AUX controllers (or reference Sink device). Often device firmware is written to support link training, which may link up when operating in a system, but the proper Write requests are not programmed to ensure proper operation for PHY testing.
  • Page 88 QPHY-DP2-SOURCE 7) Use the software utility (provided by the AUX controller vendor) to manually configure the DUT for testing. a) Mode: Native Note: Native is used in this case because the full-size DP connector on the AUX Controller is used to configure a USB-C device using a full-size DP to Type-C connector.
  • Page 89 DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI 9) With DP-AUX TDMP Viewing mode set to Symbolic, the decode table can be related to the Symbolic register names in Table 2-232 of the DisplayPort 2.1 specification. By changing the table Viewing mode to Hex, (MAIN_LINK_CHANNEL_CODING_SET) register is confirmed to be the data field 0x08.
  • Page 90 QPHY-DP2-SOURCE The full sequence of the Link Training Request can then be analyzed. In this example, it is confirmed that: • (MAIN_LINK_CHANNEL_CODING_SET) register 0x08h which has Data of 0x02 (128B/132B) DP Link Layer then a Write to 00100 (LINK_BW_SET) with data set to 0x04 (13.5 Gb/s).

  • Page 91: Appendix C: Using Sdax-Dp To Identify Best Preset And Ctle

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI Appendix C: Using SDAX-DP to Identify Best Preset and CTLE The DP 2.1 CTS requires that the Preset at TP2 and CTLE_DFE at TP3 be used for UHBR data rate BEST BEST compliance testing.
  • Page 92 QPHY-DP2-SOURCE d) Reduce Minimum Pattern Reps to 50 on the Jitter Pattern Analysis subdialog. 4) Press Single from the Trigger Menu or front panel. 5) Measure DDJ for Preset 0. 6) Repeat steps (3) and (4) for Presets 1 to 15 to determine which Preset has the minimum DDJ for Lane0.

  • Page 93: Finding Ctle_Dfe Best At Tp3

    DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI Finding CTLE_DFE at TP3 BEST From the best Preset found above at TP2, the best CTLE can be found using the following procedure. 1) Set the PresetBEST setup above. 2) Turn off Jitter measurements. 3) On the SDAX Signal Test Point subdialog, select TP3_EQ and press Apply Test Point.
  • Page 94 QPHY-DP2-SOURCE 5) Use the CTLE adjustment to find the 3 values of CTLE+DFE training to determine a range of CTLE values to use when running QPHY. CTLE: -4 dB, DFE: 40.5 mV Eye Area: 6237 mV*ps CTLE: -5 dB, DFE: 31 mV...
  • Page 95 DisplayPort 2.1/1.4 SOURCE Compliance Test Instruction Manual and MOI...

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