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Summary of Contents for Aim ACXX1553-3U-4
- Page 1 ACXX1553-3U-4 Quad Stream MIL-STD-1553 PXI / cPCI (3U) Modules Hardware Manual V01.10 Rev. A January 2016...
- Page 3 ACXX1553-3U-4 Quad Stream MIL-STD-1553 PXI / cPCI (3U) Modules Hardware Manual V01.10 Rev. A January 2016 AIM No. 60-111FA-16-0110-A ACXX1553-3U-4 Hardware Manual...
- Page 4 Notice: The information that is provided in this document is believed to be accurate. No responsibility is assumed by AIM GmbH for its use. No license or rights are granted by implication in connection therewith. Specifications are subject to change without notice.
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Page 5: Document History
The following table defines the history of this document. Version Cover Date Created by Description 01.00 Rev. A 14.04.2015 E. Carraro First Released Version New layout, corrections on the discrete V01.10 Rev. A 19.01.2016 E. Carraro section (CDR5898) ACXX1553-3U-4 Hardware Manual... - Page 6 THIS PAGE IS INTENTIONALLY LEFT BLANK ACXX1553-3U-4Hardware Manual...
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Page 7: Table Of Contents
MIL-STD-1553-A/B Dual Channel Interface Connector ......... 11 2.3.2 General Purpose I/O Connections ..............11 Front Panel LEDs ....................12 STRUCTURE OF THE ACXX1553-3U-4 ............... 13 PCI-Express bus and BIU-I/O FPGA ..............14 3.1.1 Global RAM Interface and Arbitration ............14 3.1.2... - Page 8 Figure 2.2: Pinout of the 15 Pin HD-DSUB connector ............11 Figure 2.3: Status LED view ....................12 Figure 3.1: Block Diagram of ACXX1553-3U-4 ..............13 Figure 3.2: GPI/O ACXX-1553-3U-x circuitry ................ 16 Figure 3.3: GPIO Protection with external resistor ..............17 Figure 3.4: MILBus Amplitude vs.
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Page 9: Introduction
For programming information please refer to the documents listed in the “Applicable Documents” section. The ACXX1553 modules are members of AIM's new family of advanced PXI cards compliant to PCI communication standard. The PCI Interface is capable of 32 bit data transfer with a maximum clock speed of 66MHz. -
Page 10: How This Manual Is Organized
MIL-STD-1553 Bus, IRIG-B, and triggers. Section 3 - STRUCTURE OF THE ACXX1553-3U-4 - describes the physical hardware interfaces on the ACXX1553 using a block diagram and a description of each main component Section 4 - TECHNICAL DATA - describes the technical specification of the ACXX1553. -
Page 11: Installation
9. Secure the card to the PXI/cPCI chassis tightening the two bracket-retaining screws on the top and bottom of the front panel 10. Connect the system to the power source. Turn on the power of your system. ACXX1553-3U-4 Hardware Manual... -
Page 12: Connecting To Other Devices
Terminals, as well as the IRIG IN/OUT interface for multi-channel time tag synchronization. Figure 2.1: Front Panel View The ACXX1553-3U-4 interface comprises two female DSUB15 connector for providing the MILBus signals for Trigger IN/OUT, GPIOs and the IRIG IN/OUT signals. -
Page 13: Mil-Std-1553-A/B Dual Channel Interface Connector
Avionic Level inputs and outputs. The GPIO’s can be used as simple discrete inputs or outputs, for example to generate strobes (i.e. to another AIM board) or to sample a digital input signal generated by an external system (or AIM board). -
Page 14: Front Panel Leds
2.4 Front Panel LEDs Two subminiature LEDs for each channel, located at the front panel, indicate the module status. The LEDs are located in two quadruple LED-Arrays on the physical interface daughterboard. Figure 2.3: Status LED view LED Name Colour Description FAIL (CH1) LED illuminates if an Error during the MILBus Channel1 self-test... -
Page 15: Structure Of The Acxx1553-3U-4
STRUCTURE OF THE ACXX1553-3U-4 The structure of the ACXX1553-3U-4 is shown in Figure 3.1. The ACXX1553-3U-4 comprises the following main sections: PCI bus and BIU-IO FPGA Global RAM BIU Processor Section Physical I/O Interface with up to four Dual redundant MIL-STD-1553B Channels ... -
Page 16: Pci-Express Bus And Biu-I/O Fpga
3.1 PCI-Express bus and BIU-I/O FPGA The new common FPGA architecture of AIM’s PCI family includes a complete PCI-Express bus logic (which is translated to a legacy PCI interface using an external bridge component) and the BIU processor logic. This programmable device implements the following features: ... -
Page 17: Irig-B Encoder/Decoder And Timecode Processor (Tcp)
MILBus channel at the Front I/O connector. The minimum trigger pulse length must be greater than 75 nanoseconds to be detected. The trigger inputs are high active and their voltage level is of type TTL and is +5.0V tolerant. ACXX1553-3U-4 Hardware Manual... -
Page 18: User Programmable Discrete I/O (Gpio)
3.1.9 User programmable Discrete I/O (GPIO) The ACXX1553-3U-4 module provides 2 user programmable discrete I/O signals. . Discrete input signals are always active whereas the discrete output signals are per default inactive. An open collector circuitry is used for the discrete output with approximately 4V provided by default. -
Page 19: Global Ram
Up to two Bus Interface Units (BIUs) are implemented on the ACXX1553-3U module. Both BIUs implement exactly the same functionality. Each BIU handle up to two MIL-STD-1553B channels and provide the trigger signals for BC, RT and BM applications. The control logic is implemented in the common FPGA device. ACXX1553-3U-4 Hardware Manual... -
Page 20: Physical Bus Interface With Four Dual Redundant Mil-Std-1553B Channels
3.4 Physical Bus Interface with four Dual Redundant MIL-STD-1553B Channels The Physical Bus Interface (PBI) is implemented as a daughter-board and is mounted on the ACXX1553 main board. The Physical Bus Interface (PBI) contains four dual redundant MIL- STD-1553 channels, each channel comprises a dual-redundant transceiver, transmitter amplitude control circuitry, a dual bus coupling transformer and the coupling relays with the MILBus network emulation circuitry. -
Page 21: General Purpose Discrete Inputs/Outputs (Gpio)
The ACXX1553-3U-4 provides two General Purpose Discrete I/O's (GPIO’s). The GPIO’s can be used as simple discrete inputs or outputs, for example to generate strobes (i.e. to another AIM board) or to sample a digital input signal generated by an external system (or AIM board). ACXX1553-3U-4 Hardware Manual... -
Page 22: Irig- And Time Code Section
On the ACXX1553-3U-4 a new generation IRIG-B section is implemented with a free-wheeling IRIG functionality. If no external IRIG signal is detected, the TCP switches automatically to the free- wheeling mode. Also, if an external IRIG-B signal is detected in free-wheeling mode, the Time tag is automatically synchronized to this external IRIG-B signal. -
Page 23: Pxi / Cpci - Connector Pin Assignment
INTD# -12V TRST# +12V Table 3.4: cPCI J1 connector's pin-out RSV: Reserved Pin RED MARKED PINS on J1 are left unconnected, the corresponding features are not implemented. BROWN MARKED Pins are pulled-up to set specific PCI features. ACXX1553-3U-4 Hardware Manual... - Page 24 This Page Intentionally Left Blank ACXX1553-3U-4Hardware Manual...
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Page 25: Pxi-Express Instrumentation Bus
PXIe combines industry-standard PC components, such as the PCI-Express bus, with advanced triggering and synchronization extensions on the backplane, backward compatible with the PXI triggering and synchronization bus. The PXI-functions can be controlled via the API interface. ACXX1553-3U-4 Hardware Manual... -
Page 26: Backplane Trigger Lines
Finally, trigger signals can be routed into and out of the chassis with many of the newer controllers. The ACXX1553-3U-4 card can route its Trigger INPUTs and/or Trigger OUTPUTs to the PXI backplane trigger lines, letting the user to deliver /receive trigger signals to/from other PXI cards present in the system (a Trigger Controller, another AIM PXI-capable product). -
Page 27: Figure 4.2: Pxi/Front Panel-Pbi Trigger Routing Capabilities
Figure 4.2: PXI/Front Panel-PBI Trigger Routing capabilities ACXX1553-3U-4 Hardware Manual... -
Page 28: System Reference Clock (10Mhz)
Furthermore, because the clock lines are built into the backplane, the lines are better shielded than external lines. The ACXX1553-3U-4 card can be set to deliver the PXI 10 MHz System Clock to its internal TIME TAG generation circuitry. The IRIG decoder will then work in Free-Wheeling mode but synchronous to the PXI 10 Mhz clock. -
Page 29: Star Trigger
The ACXX1553-3U-4 card can use the PXI STAR input signal to perform a TTAG reset (clear) to DAY 1. This TTAG reset to DAY 1 will work if the IRIG circuitry is running in Free-Wheeling mode: ... - Page 30 This Page Intentionally Left Blank ACXX1553-3U-4Hardware Manual...
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Page 31: Technical Data
For each BIU, one Manchester Decoder with Parity checker and error detection. Single implementation with bus switching logic (not redundant). Full error detection and indication Inter-word gap and Response Time Measurement (<=100µs) with 250ns resolution. ACXX1553-3U-4 Hardware Manual... - Page 32 Lock time: < 5s Free-wheeling accuracy after 10 Minutes < 1ppm (assuming input signal accuracy better than 50ppm) Encoder: Format: AIM Standard (based on IRIG B format) Absolute Accuracy: +/-25ppm (standard Oscillator) Signal Waveform: Amplitude modulated sine wave Output Amplitude:...
- Page 33 Pulse-width multiple of 100ns IRIG-IN: AC-coupled Input resistor ~ 10K, with high speed EMV varistor. 0.5 to 5.0 Vpp input voltage IRIG-OUT: AC-coupled Output resistor ~ 51, with high speed EMV varistor. ~ 3 Vpp output voltage ACXX1553-3U-4 Hardware Manual...
- Page 34 Otherwise the transistor can be damaged. (Paragraph 3.1.9). Supply Voltage: Standard cPCI – Supply +3.3V, +5.0V, +12.0V Dimensions: PXI/PXIe slot compatible - 100 x 160 mm Power Consumption: ACXX1553-3U-4 Working idle + 3.3V 3,09 W 0,65 W + 5.0V...
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Page 35: Notes
Random Access Memory SIMM Single Inline Memory Module SRAM Static Random Access Memory SSRAM Synchronous Static Random Access Memory SDRAM Synchronous Dynamic RAM Software Test Access Port (for JTAG) Time Code Processor UART Universal Asynchronous Receiver and Transmitter ACXX1553-3U-4 Hardware Manual...
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