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Summary of Contents for Aim APE-FDX-2
- Page 1 APE-FDX-2 10/100/1000Mbit AFDX / ARINC664 Test and Simulation Card Set for PCIe Bus Hardware Manual V01.00 Rev. A June 2017...
- Page 3 APE-FDX-2 10/100/1000Mbit AFDX/ARINC664 Test and Simulation Card Set for PCIe 2.0 Hardware Manual V01.00 Rev. A June 2017 AIM No. 60-151A0-16-0100-A APE-FDX-2 Hardware Manual...
- Page 4 Notice: The information that is provided in this document is believed to be accurate. No responsibility is assumed by AIM GmbH for its use. No license or rights are granted by implication in connection therewith. Specifications are subject to change without notice.
- Page 5 DOCUMENT HISTORY The following table defines the history of this document. Version Cover Date Created by Description V01.00 A 13.06.2017 M. Maier / D. Bau First release APE-FDX-2 Hardware Manual...
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Page 7: Table Of Contents
Connecting to Other Devices ....................4 2.3.1 AFDX Connection ........................5 2.3.2 Trigger, Discrete and IRIG Connector ..................5 Structure of the APE-FDX-2 ................... 7 System on Chip (SoC) ....................... 9 3.1.1 Ethernet MAC Features ......................9 3.1.2 PCI-Express Bus and DMA Engine ..................9 3.1.3... - Page 8 LIST OF FIGURES Table Title Page Figure 2-1: Front panel View of APE-FDX-2 ..............4 Figure 2-2: Pinout DSUB ....................6 Figure 3-1: APE-FDX-2 Block Diagram ................8 Figure 3-2: GPI/O APE-FDX-2 circuitry ................. 13 Figure 3-3: Discrete Protection with external resistor ............ 14...
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Page 9: Introduction
The APE-FDX-2 module is a member of AIM's family of advanced PCIe-Bus modules for analysing, simulating, monitoring and testing of avionic Databus Systems. The APE-FDX-2 module is used to simulate, monitor and inject protocol errors of AFDX based network systems as well as common Ethernet networks with a data rate of 10/100/1000 Mbit/s. -
Page 10: How This Manual Is Organized
This APE-FDX-2 Hardware Manual is comprised of following sections. Section 1 – Introduction - contains an overview of this manual. Section 2 - Installation - describes the steps required to install the APE-FDX-2 device, and connect the device to other external interfaces including the AFDX Network, IRIG-B, and triggers. -
Page 11: Instalation
2 INSTALATION 2.1 Preparation and Precaution for Installation The APE-FDX-2 features full PCIe Plug and Play capability, therefore, there are no jumpers or switches on the board that require modification by the user in order to interface to the PCIe bus. -
Page 12: Connecting To Other Devices
2.3 Connecting to Other Devices The external interfaces of the APE-FDX-2 consist of two RJ45 Ethernet connectors, Trigger In/Out signal, Discrete IO signals, Ground as well as IRIG In/Out interface for multi-channel time tag synchronization. Discrete IO4 Ground Trigger-Out2 Trigger-Out4... -
Page 13: Afdx Connection
2.3.2 Trigger, Discrete and IRIG Connector For multi-channel time tag synchronization an input for the on-board IRIG-Decoder and an output for inter-board synchronization is available. The output format is an AIM specific IRIG coded signal. The connector also provides four Trigger input/output signals, which can be used with dedicated applications. -
Page 14: Figure 2-2: Pinout Dsub
No connection required Multiple AIM-Modules with no common synchronization requirement No connection required Single or multiple AIM-Module(s) with external IRIG-B source Connect external IRIG-B source to IRIG-IN and GND of all modules Multiple AIM-Modules with no external IRIG-B source internally synchronized. -
Page 15: Structure Of The Ape-Fdx-2
3. Structure of the APE-FDX-2 3 STRUCTURE OF THE APE-FDX-2 The structure of the APE-FDX-2 board is shown in the block diagram on the next page. The APE-FDX-2 comprises the following main sections: System on a Chip design with ... -
Page 16: Figure 3-1: Ape-Fdx-2 Block Diagram
IRIG 1 GB Data Processor Z015 Handler 2 GB PS Dual- RX RAM Core (optional) NAND / QSPI Boot Flash PCIe Endpoint IRIG NOVRAM PCIe 2.0 x1 Quartz & Clock Buffer Host Figure 3-1: APE-FDX-2 Block Diagram APE-FDX-2 Hardware Manual... -
Page 17: System On Chip (Soc)
3.1.2 PCI-Express Bus and DMA Engine The FPGA architecture of AIM´s family of PCI Express based modules includes as Host Interface a 1-lane PCIe 2.0 endpoint that provide 500 Mbyte/s upstream and downstream bandwidth, concurrently. -
Page 18: Irig- And Time Code Section
3.1.3.2 Timecode Encoder/Decoder On the APE-FDX-2 a freewheeling IRIG function is implemented. If no external IRIG signal is detected, the IRIG Decoder switches automatically to the freewheeling operation mode. If an external IRIG-B signal is detected in freewheeling mode, the Time Tag is automatically synchronized to this external IRIG-B signal. -
Page 19: Application Specific Processor
Setup Receive and Transmit DMA machines in the PL Relieve the Host system, fasten up the board and expands the capability of the APE-FDX-2 module to a high level instrument. 3.1.5 BIU Processor Core 2 of the Dual Core Processor is used as Bus Interface Processor (BIP) and handles the real time critical control of the two AFDX ports. -
Page 20: External Trigger Inputs And Outputs
(ESD sparks). 3.4 User programmable Discrete I/O The APE-FDX-2 module provides four user definable discrete I/O signals. Discrete input signals are always active whereas the discrete output signals are per default inactive. An open collector circuitry is used for the discrete output with approximately 4V provided by default. -
Page 21: Figure 3-2: Gpi/O Ape-Fdx-2 Circuitry
3. Structure of the APE-FDX-2 Discrete IO-Pin Front Connector FPGA Input Current Current Limiting Limiting Resistor Resistor (1 KΩ) (10 KΩ) FPGA Output Pulldown Resistor Discrete output circuitry Discrete input circuitry APE-FDX-2 Board Figure 3-2: GPI/O APE-FDX-2 circuitry Be aware that a series resistor must be provided when a user voltage is used (Figure 3- 3). -
Page 22: Figure 3-3: Discrete Protection With External Resistor
Off-Board User Voltage serial Customized Discrete Output Discrete IO-Pin Front Connector FPGA Output APE-FDX-2 Board Figure 3-3: Discrete Protection with external resistor APE-FDX-2 Hardware Manual... -
Page 23: Technical Data
Up to 500 Mbyte/s Bandwidth in each direction concurrently (up/downstream) Note: In some PC systems, there are PCIe Slots specially dedicated for use as graphic adapter slot. These slots are not suitable to host the APE-FDX-2. Memory: 1024 MByte DDR3-RAM (Global RAM) 2048 MByte DDR3-RAM (Dedicated RX-RAM) - Page 24 Through-Hole Micro Header for maintenance purposes Trigger In: TTL compatible Input Level and fast ESD protection diodes. Additional varistors on the Front IO nearby connector to suppress peaks of glitches. Rising Edge sensitive, Pulse width > 75 ns APE-FDX-2 Hardware Manual...
- Page 25 Otherwise the transistor can be damaged. (see chapter Discrete I/O). Dimensions: PCIe standard, 174.6mm x 106.7mm Weight: APE-FDX-2 appr. 100g Standard PC – Supply +3.3V +/- 5%, 12V +/- 5% Supply Voltage: Power Consumption: APE-FDX-2...
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Page 27: Notes
Surface Mounted Device SRAM Static Random Access Memory SSRAM Synchronous Static Random Access Memory SDRAM Synchronous Dynamic RAM Software Test Access Port (for JTAG) Time Code Processor UART Universal Asynchronous Receiver and Transmitter PCI Express Mezzanine Card APE-FDX-2 Hardware Manual... - Page 28 THIS PAGE IS INTENTIONALLY LEFT BLANK APE-FDX-2 Hardware Manual...
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Page 29: Certificate Of Volatility
Does the item contain media storage capability (i.e., removable or non-removable disk drives, tape drives, memory cards, etc.)? Description of used media storage: Type: Size: User Modifiable: Function: Process to Sanitize: -None- Additional Information: Test Engineer Name: Title: Date of Certification: Daniel Bau Hardware Engineer 24.04.2017 APE-FDX-2 Hardware Manual...
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