NEC mPD70F3732 Manuals

Manuals and User Guides for NEC mPD70F3732. We have 1 NEC mPD70F3732 manual available for free PDF download: User Manual

NEC mPD70F3732 User Manual (885 pages)

32-bit Single-Chip Microcontrollers

Brand: NEC | Category: Microcontrollers | Size: 4 MB

Notes for Cmos Devices
3
Related Documents
8
Table of Contents
9
Chapter 1 Introduction
19
V850Es/Kx2 Product Lineup
19
Features
20
Applications
22
Ordering Information
22
Pin Configuration (Top View)
23
Function Block Configuration
26
Overview of Functions
30
Chapter 2 Pin Functions
31
List of Pin Functions
31
Non-Port Pins
34
Pin Status
39
Pin I/O Circuits and Recommended Connection of Unused Pins
40
Pin I/O Circuits
42
Chapter 3 Cpu Functions
44
Features
44
CPU Register Set
45
Program Register Set
46
System Register Set
47
Program Status Word (PSW)
50
Operating Modes
53
Address Space
54
CPU Address Space
54
Wraparound of CPU Address Space
55
Memory Map
56
Areas
58
Recommended Use of Address Space
62
Peripheral I/O Registers
65
Special Registers
76
Cautions
80
Chapter 4 Port Functions
85
Features
85
Basic Port Configuration
85
Port Configuration
86
Port 0
92
Port 1
95
Port 3
97
Port 4
103
Port 5
106
Port 7
109
Port 9
110
Port CM
118
Port CS
120
Port CT
122
Port DH
124
Port DL
126
Block Diagrams
129
Port Register Setting When Alternate Function Is Used
154
Cautions
161
Cautions on Bit Manipulation Instruction for Port N Register (Pn)
161
Hysteresis Characteristics
162
Chapter 5 Bus Control Function
163
Features
163
Bus Control Pins
164
Pin Status When Internal ROM, Internal RAM, or On-Chip Peripheral I/O Is Accessed
165
Pin Status in each Operation Mode
165
Memory Block Function
166
Chip Select Control Function
167
External Bus Interface Mode Control Function
167
Bus Access
168
Number of Clocks for Access
168
Bus Size Setting Function
168
Bus Size Configuration Register (BSC)
168
Access by Bus Size
169
Wait Function
176
Programmable Wait Function
176
External Wait Function
177
Relationship between Programmable Wait and External Wait
178
Programmable Address Wait Function
179
Idle State Insertion Function
180
Bus Hold Function
181
Functional Outline
181
Bus Hold Procedure
182
Operation in Power Save Mode
182
Bus Priority
183
Bus Timing
184
Cautions
190
Chapter 6 Clock Generation Function
191
Overview
191
Configuration
192
Registers
194
Operation
198
Operation of each Clock
198
Clock Output Function
198
External Clock Input Function
198
PLL Function
199
Overview
199
Register
199
Usage
200
Chapter 7 16-Bit Timer/Event Counter P (Tmp)
201
Overview
201
Functions
201
Configuration
202
Registers
204
Operation
215
Interval Timer Mode (TP0MD2 to TP0MD0 Bits = 000)
216
External Event Count Mode (TP0MD2 to TP0MD0 Bits = 001)
226
External Trigger Pulse Output Mode (TP0MD2 to TP0MD0 Bits = 010)
234
One-Shot Pulse Output Mode (TP0MD2 to TP0MD0 Bits = 011)
246
PWM Output Mode (TP0MD2 to TP0MD0 Bits = 100)
253
Free-Running Timer Mode (TP0MD2 to TP0MD0 Bits = 101)
262
Pulse Width Measurement Mode (TP0MD2 to TP0MD0 Bits = 110)
279
Timer Output Operations
285
Eliminating Noise on Capture Trigger Input Pin (Tip0A)
286
Cautions
288
Chapter 8 16-Bit Timer/Event Counter 0
289
Functions
289
Configuration
290
Registers
295
Operation
303
Interval Timer Operation
303
Square Wave Output Operation
306
External Event Counter Operation
309
Operation in Clear & Start Mode Entered by Ti0N0 Pin Valid Edge Input
312
Free-Running Timer Operation
328
PPG Output Operation
337
One-Shot Pulse Output Operation
340
Pulse Width Measurement Operation
345
Special Use of Tm0N
353
Rewriting Cr0N1 Register During Tm0N Operation
353
Interrupt/Exception Processing
353
Setting Lvs0N and Lvr0N Bits
353
Cautions
355
Chapter 9 8-Bit Timer/Event Counter 5
362
Functions
362
Configuration
363
Registers
366
Operation
369
Operation as Interval Timer
369
Operation as External Event Counter
371
Square-Wave Output Operation
372
8-Bit PWM Output Operation
374
Operation as Interval Timer (16 Bits)
377
Operation as External Event Counter (16 Bits)
379
Square-Wave Output Operation (16-Bit Resolution)
380
Cautions
381
Chapter 10 8-Bit Timer H
382
Functions
382
Configuration
382
Registers
385
Operation
389
Operation as Interval Timer/Square Wave Output
389
PWM Output Mode Operation
392
Carrier Generator Mode Operation
398
Chapter 11 Interval Timer, Watch Timer
405
Interval Timer BRG
405
Functions
405
Configuration
405
Registers
407
Operation
409
Watch Timer
410
Functions
410
Configuration
410
Registers
411
Operation
413
Operation as Watch Timer
413
Operation as Interval Timer
413
Cautions
414
Chapter 12 Watchdog Timer Functions
416
Watchdog Timer 1
416
Functions
416
Configuration
418
Registers
418
Operation
420
Watchdog Timer 2
422
Functions
422
Configuration
423
Registers
423
Watchdog Timer Enable Register (WDTE)
424
Operation
425
Chapter 13 Real-Time Output Function (Rto)
426
Function
426
Configuration
427
Registers
428
Operation
430
Usage
431
Cautions
431
Security Function
432
Chapter 14 A/D Converter
434
Overview
434
Functions
434
Configuration
435
Registers
437
Operation
445
Basic Operation
445
Trigger Modes
446
Operation Modes
447
Power Fail Detection Function
450
Setting Method
451
Cautions
452
How to Read A/D Converter Characteristics Table
458
Chapter 15 D/A Converter
462
Functions
462
Configuration
463
Registers
464
D/A Converter Mode Register (DAM)
464
Operation
465
Operation in Normal Mode
465
Operation in Real-Time Output Mode
465
Chapter 23 Standby Function
465
Cautions
466
Chapter 16 Asynchronous Serial Interface (Uart)
467
Selecting UART2 or CSI00 Mode
467
Features
468
Configuration
469
Registers
471
Interrupt Requests
477
Operation
478
Data Format
478
Transmit Operation
479
Continuous Transmission Operation
481
Starting Procedure
483
Ending Procedure
484
Receive Operation
485
Reception Error
486
Parity Types and Corresponding Operation
488
Receive Data Noise Filter
489
Dedicated Baud Rate Generator N (Brgn)
490
Baud Rate Generator N (Brgn) Configuration
490
Serial Clock Generation
491
Baud Rate Setting Example
494
Allowable Baud Rate Range During Reception
495
Transfer Rate During Continuous Transmission
497
Cautions
497
Chapter 17 Clocked Serial Interface 0 (Csi0)
498
Features
498
Configuration
499
Registers
502
Operation
511
Transmission/Reception Completion Interrupt Request Signal (Intcsi0N)
511
Single Transfer Mode
513
Continuous Transfer Mode
516
Output Pins
524
Chapter 18 Clocked Serial Interface a (Csia) with Automatic Transmit/Receive Function
525
Functions
525
Configuration
526
Registers
528
Operation
537
3-Wire Serial I/O Mode
537
3-Wire Serial I/O Mode with Automatic Transmit/Receive Function
541
Chapter 19 I 2 C Bus
557
Features
557
Configuration
560
Registers
562
Functions
576
Pin Configuration
576
I C Bus Definitions and Control Methods
577
Start Condition
577
Addresses
578
Transfer Direction Specification
579
Ack
580
Stop Condition
581
Wait State
582
Wait State Cancellation Method
584
I C Interrupt Request Signals (INTIIC0)
585
Master Device Operation
586
Slave Device Operation (When Receiving Slave Address Data (Address Match))
589
Slave Device Operation (When Receiving Extension Code)
593
Operation Without Communication
597
Arbitration Loss Operation (Operation as Slave after Arbitration Loss)
598
Operation When Arbitration Loss Occurs (no Communication after Arbitration Loss)
600
Interrupt Request Signal (INTIIC0) Generation Timing and Wait Control
607
Address Match Detection Method
608
Error Detection
608
Extension Code
609
Arbitration
610
Wakeup Function
611
Communication Reservation
612
When Communication Reservation Function Is Enabled (IICF0.IICRSV0 Bit = 0)
612
When Communication Reservation Function Is Disabled (IICF0.IICRSV0 Bit = 1)
615
Cautions
616
Communication Operations
617
Master Operation in Single Master System
618
Master Operation in Multimaster System
619
Slave Operation
622
Timing of Data Communication
625
Chapter 20 Dma Function (Dma Controller)
632
Features
632
Configuration
633
Registers
634
DMA Transfer
634
Transfer Targets
641
Transfer Modes
641
Transfer Types
642
DMA Channel Priorities
642
Time Related to DMA Transfer
643
DMA Transfer Start Factors
644
DMA Abort Factors
645
End of DMA Transfer
645
Operation Timing
645
Cautions
650
Chapter 21 Interrupt/Exception Processing Function
655
Overview
655
Features
655
Non-Maskable Interrupts
659
Operation
662
Restore
663
NP Flag
664
Maskable Interrupts
665
Operation
665
Restore
667
Priorities of Maskable Interrupts
668
Interrupt Control Register (Xxlcn)
672
Interrupt Mask Registers 0 to 3 (IMR0 to IMR3)
674
In-Service Priority Register (ISPR)
676
ID Flag
677
Watchdog Timer Mode Register 1 (WDTM1)
678
External Interrupt Request Input Pins (NMI, INTP0 to INTP7)
679
Noise Elimination
679
Edge Detection
681
Software Exceptions
685
Operation
685
Restore
686
EP Flag
687
Exception Trap
688
Illegal Opcode
688
Debug Trap
690
Multiple Interrupt Servicing Control
692
Interrupt Response Time
694
Periods in Which Interrupts Are Not Acknowledged by CPU
695
Cautions
695
Chapter 22 Key Interrupt Function
696
Function
696
Register
697
Chapter 23 Standby Function
698
Overview
698
Chapter 6 Clock Generation Function
698
Registers
701
HALT Mode
704
Setting and Operation Status
704
Releasing HALT Mode
704
IDLE Mode
706
Setting and Operation Status
706
Releasing IDLE Mode
707
STOP Mode
709
Setting and Operation Status
709
Releasing STOP Mode
710
Securing Oscillation Stabilization Time When STOP Mode Is Released
712
Subclock Operation Mode
713
Setting and Operation Status
713
Releasing Subclock Operation Mode
713
Sub-IDLE Mode
715
Setting and Operation Status
715
Releasing Sub-IDLE Mode
716
Chapter 24 Reset Function
718
Overview
718
Configuration
718
Operation
719
Chapter 25 Regulator
723
Overview
723
Operation
723
Chapter 26 Flash Memory
725
Features
725
Memory Configuration
726
Functional Outline
727
Rewriting by Dedicated Flash Programmer
731
Programming Environment
731
Communication Mode
732
Flash Memory Control
739
Selection of Communication Mode
740
Communication Commands
741
Pin Connection
742
RESET Pin
746
Rewriting by Self Programming
747
Overview
747
Features
748
Standard Self Programming Flow
749
Flash Functions
750
Pin Processing
750
Internal Resources Used
751
Chapter 27 On-Chip Debug Function
752
Debugging Without Using DCU
753
Circuit Connection Examples
753
Maskable Functions
755
Securing of User Resources
756
Cautions
761
ROM Security Function
762
Security ID
762
Setting
763
Chapter 28 Electrical Specifications
765
Absolute Maximum Ratings
765
PLL Characteristics
767
Operating Conditions
767
Main Clock Oscillator Characteristics
769
External Clock
769
Data Retention Characteristics
775
Clock Timing
777
Timer Input Timing
801
UART Timing
802
Master Mode
803
Slave Mode
803
Chapter 29 Package Drawings
812
Chapter 30 Recommended Soldering Conditions
814
Appendix A Development Tools
815
Software Package
817
Language Processing Software
817
Control Software
817
Debugging Tools (Hardware)
818
When Using IECUBE QB-V850ESKX1H
818
When Using MINICUBE QB-V850MINI
820
When Using MINICUBE2 QB-MINI2
822
Debugging Tools (Software)
823
Embedded Software
824
Flash Memory Writing Tools
825
Appendix B Instruction Set List
826
Conventions
826
Condition Codes
828
Instruction Set (in Alphabetical Order)
829
Appendix C Register Index
836
Appendix D List of Cautions
845
Appendix E Revision History
884
Major Revisions in this Edition
884

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