Sharp TM200 Service Manual page 77

Pin Terminal Input/
No. name Output
51 VSYNC Input/
Output
52 HSYNC Input/
Output
*
53 EXCS_B3 Input/
Output
54 XIN Input
55 SUBDB6 Input/
Output
56 RESET_B Input
57 SUBDB0 Input/
Output
58 SUBDB2 Input/
Output
59 HSD5 Input/
Output
60 DB0 Input/
Output
61 HSD4 Input/
Output
*
62 EXCS_B2 Input/
Output
63 GDATA[5] (G5) Output Display panel G output signal
64 GDATA[4] (G4) Output Display panel G output signal
65 GDATA[3] (G3) Output Display panel G output signal
66 SUBDB3 Input/
Output
67 SUBDB4 Input/
Output
68 HSD7 Input/
Output
69 DB1 Input/
Output
70 DB2 Input/
Output
71 DB3 Input/
Output
72 DB4 Input/
Output
73 STKCHK Input
74 VDDCORE -
75 GND -
76 VDDIO -
77 GDATA[2] (G2) Output Display panel G output signal
78 SUBDB5 Input/
Output
79 BSCLK Input/
Output
80 SUBCK Output Clock for External display
81 DB5 Input/
Output
82 VDDIO -
83 GND -
CONFIDENTIAL
Description of terminal
Vertical synchronization signal
Horizontal synchronization signal
Chip select output 3
(internal decode output) (Not used)
Oscillation circuit input/External
clock input signal Clock input for full
scan
Data bus for External display
Master reset (All registers are
initialized when Low is activated)
Data bus for External display
Data bus for External display
Data bus for high-speed serial transfer
Data bus
Data bus for high-speed serial transfer
Chip select output 2 (internal
decode output) (Not used)
Data bus for External display
Data bus for External display
Data bus for high-speed serial transfer
Data bus
Data bus
Data bus
Data bus
Setting BS-related output terminal to
Hi-z when a stack is installed (Con-
nected to GND normally)
CORE Power supply 1.8 V (1.6 V~ 2.0 V)
Logic ground
IO Power supply 3.0 V (2.7 V~ 3.3 V)
Data bus for External display
External Bit Stream data clock
Data bus
IO Power supply 3.0 V (2.7 V~ 3.3 V)
Logic ground
Pin Terminal
No. name
84 VDDCORE
85 CAMCK
86 GDATA[1] (G1)
87 GDATA[0] (G0)
88 RDATA[5] (R5)
89 RDATA[4] (R4)
90 VDDCORE
*
91 P W M L C D /
PORT4
92 BSBLK_B
93 DB6
94 DB7
95 DB8
96 DB9
97 VDDIO
98 RDATA[3] (R3)
99 RDATA[2] (R2)
100 RDATA[1] (R1)
101 RDATA[0] (R0)
*
102 MP4_P0
*
103 EXCS_B0
104 BSPIXEL7
105 BSVS_B
106 DB10
107 DB11
108 DB12
*
109 MP4_PLLCK
110 SUBDB7
111 GND
112 DA0
113 BSPIXEL0
114 DCS_B
115 VDDIO
116 BSPIXEL6
117 SE_DO/PORT0
118 DB13
TM200 OTHERS
6 - 12
Input/
Description of terminal
Output
- CORE Power supply 1.8 V (1.6 V~ 2.0 V)
Output Clock for camera operation
Output Display panel G output signal
Output Display panel G output signal
Output Display panel R output signal
Output Display panel R output signal
- CORE Power supply 1.8 V (1.6 V~ 2.0 V)
Output PWM LCD output General-purpose
PORT output (default) (Not used)
Input/ External Bit Stream data effective
Output signal ("High" is active when
transferring the data)
Input/ Data bus
Output
Input/ Data bus
Output
Input/ Data bus
Output
Input/ Data bus
Output
- IO Power supply 3.0 V (2.7 V~ 3.3 V)
Output Display panel R output signal
Output Display panel R output signal
Output Display panel R output signal
Output Display panel R output signal
Output MPEG4 control
Input/ Chip select output 0 (internal
Output decode output) (Not used)
Input/ External Bit Stream data bus
Output
Input/ External Bit Stream vertical synchro-
Output nization signal ("Low" is active)
Input/ Data bus
Output
Input/ Data bus
Output
Input/ Data bus
Output
Output MPEG4ASIC clock 15.36 MHz/CPU
supply XIN clock (Not used)
Input/ Data bus for External display
Output
- Logic ground
Input/ Address input for chip select
Output decode
Input/ External Bit Stream data bus
Output
Input Chip select input dedicated for chip
select decode
- IO Power supply 3.0 V (2.7 V~ 3.3 V)
Input/ External Bit Stream data bus
Output
Output Data output for 4-wire serial IF (default)
General-purpose PORT output
Input/ Data bus
Output