Wi-fi & bluetooth low energy connected mcu evaluation kit (62 pages)
Summary of Contents for Infineon Cypress CYTVII-B-H-8M-176-CPU
Page 1
The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio.
Page 2
CYTVII-B-H-8M-176-CPU Evaluation Board User Guide Document Number: 002-25907 Rev. *C Cypress Semiconductor An Infineon Technologies Company 198 Champion Court San Jose, CA 95134-1709 www.cypress.com, www.infineon.com...
Contents 1. Introduction Precautions and Warnings...................4 2. Overview Functional Overview ....................7 3. Operation 4. Connections and Settings Evaluation Board Connections ..................16 Power Supply Settings....................22 External Power Supply Control Signals Settings ............23 Ethernet Settings .......................23 Settings........................24 5. Power Management IC (PMIC) Power Management IC (PMIC) Module ..............25 A.
Introduction This user guide provides instructions to handle the CYTVII-B-H-8M-176-CPU and CYTVII-B-H-176-SO evaluation boards, collectively referred to as 'CPU board' in this document. This is an evaluation platform for the CYT4BF8C Traveo™ II device. The board can be used as a standalone for basic validation or in combination with the CYTVII-B-E-BB Traveo II base board (available separately from Cypress).
Overview Figure 2-1 shows the CYTVII-B-H-176-SO board. Insert a Traveo II device into the IC socket (highlighted in red) while the evaluation board is powered OFF. Figure 2-1. CYTVII-B-H-176-SO Board A variant of the CPU board (CYTVII-B-H-8M-176-CPU) is also available, where the Traveo II device is soldered directly onto the PCB.
Page 7
Overview Figure 2-2. Traveo II Base Board (CYTVII-B-E-BB) Two Samtec connectors on the CPU board and corresponding mating connectors on the base board are used to connect sig- nals across the two boards. When put together, the boards appear as shown in Figure 2-3.
Overview Functional Overview The CPU board has the following components: 1. One Traveo II device, either soldered or mounted on a socket (U3). 2. PMIC to generate the 5-V, 3.3-V, and 1.1-V output, which powers the CPU board and the base board (if connected). ®...
Overview 2.1.2 USB Connector The location of the USB Connector is shown in Figure 2-5. Figure 2-5. USB Connector CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *C...
Overview 2.1.3 Ethernet Connector The location of the Ethernet Connector is shown in Figure 2-6. Figure 2-6. Ethernet Connector CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *C...
Page 12
Overview 2.1.4 SMIF Connector The location of the SMIF Connector is shown in Figure 2-7. Figure 2-7. SMIF Connector CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *C...
Page 13
Overview 2.1.5 eMMC Connector The location of the eMMC Connector is shown in Figure 2-8. Figure 2-8. eMMC Connector CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *C...
Overview 2.1.6 Audio Connector The location of the Audio Connector is shown in Figure 2-9. Figure 2-9. Audio Connector CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *C...
Operation This section describes the operation of the CPU board and the base board. It is assumed that you have connected the CPU board to the base board using the Samtec interface and inserted a Traveo II device into the IC socket (applicable to CYTVII- B-H-176-SO boards only).
Page 16
Operation 8. Install the appropriate programming integrated design environment (IDE) on a PC. The programming IDE (GHS MULTI, IAR Embedded Workbench, Cypress Programmer, and so on) should be able to detect a device (read the device ID) and to load a firmware HEX file (.srec) into the device flash successfully. As part of the release package, various firmware examples compiled in .srec programming IDEs are available.
Connections and Settings Evaluation Board Connections 4.1.1 Base Board Connections Make sure that the following jumpers are inserted on the base board, so that each transceiver on the base board can be used with the respective firmware example that activate each functionality of the device: CAN0.0 from the device uses the CAN0 transceiver on the base board (connect jumpers J70, J71, J72).
Page 18
Connections and Settings Table 4-1. Device Port Pin Connections on Base Board Connection 1 Connection 1 Connection 1 MCU Port Pin CPU Board Base Board Signal Name of Schematics Test Point Test Point VSSD Not applicable P0.0 ETH_REFCLK TP110 Not applicable P0.1 ETH_TXEN TP111...
Page 19
Connections and Settings Table 4-1. Device Port Pin Connections on Base Board Connection 1 Connection 1 Connection 1 MCU Port Pin CPU Board Base Board Signal Name of Schematics Test Point Test Point VDDIO_1 Not applicable TP10 Not applicable VSSD Not applicable VCCD Not applicable...
Page 20
Connections and Settings Table 4-1. Device Port Pin Connections on Base Board Connection 1 Connection 1 Connection 1 MCU Port Pin CPU Board Base Board Signal Name of Schematics Test Point Test Point VSSD Not applicable P13.0 UART_RX TP185 JP10.4 P13.1 UART_TX TP186...
Page 21
Connections and Settings Table 4-1. Device Port Pin Connections on Base Board Connection 1 Connection 1 Connection 1 MCU Port Pin CPU Board Base Board Signal Name of Schematics Test Point Test Point P19.0 GPIO_P19_0 J36.3 Not applicable P19.1 GPIO_P19_1 J37.3 Not applicable P19.2...
Connections and Settings For each pin, the connected peripheral or net on the base board is depicted by the Netname of Schematics column. The Base Board Test Point column indicates the place where the signal can be probed on the base board. For example, JP6.15 refers to the 15 pin on the JP6 header.
Connections and Settings 4.1.6 JTAG Select Jumpers The correspondence between the JTAG Select Jumpers and selected functions is given in Table 4-6. Table 4-6. JTAG Select Jumpers Jumpers Name Part No. Connection Function 1-2 (default) SWJ_TRSTN TRSTN GPIO_P19_0 1-2 (default) SWJ_SWO_TDO SWO_TDO GPIO_P19_1...
Connections and Settings Figure 4-1. Power Supply Jumpers Settings VCC11_TR VCC11 VCC11_OUT CPU_VCCD VCC3 VDDD VCC5 CPU_VDDD VDDIO_1 CPU_VDDIO_1 VDDIO_2 CPU_VDDIO_2 CPU_VDDA External Power Supply Control Signals Settings Jumper Settings of the External Power Supply Control Signals from MCU are shown in Table 4-8.
Connections and Settings Settings Settings are shown in Table 4-10. Table 4-10. Settings Function Status Jumper Settings Remarks is enabled Closed is disabled Open CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *C...
Power Management IC (PMIC) Power Management IC (PMIC) Module 5.1.1 PMIC Module - CYALKIT-A18 CYALKIT-A18 is the PMIC module for the power block of an automotive application with CYT4B Series MCU. The PMIC Module implements the Cypress PMIC S6BP501A and is optimized for power supply of CYT4B Series MCU. 1.1 V output to supply to VCCD of CYT4B Series MCU needs external schottky barrier diode (SBD), output capacitor and constant load cur- rent no less than 20 mA.
Power Management IC (PMIC) 5.1.2 Input/Output Pin Descriptions Table 5-1. Input/Output Pin Descriptions Connector Symbol Function Description 1, 2 VOUT3V 3.3 V power rail output terminal (0 A - 0.75 A) 3, 4 PGND Ground terminal Mode setting or external clock input terminal SYNC Refer to the S6BP501A datasheet PG1V...
Revision History Document Revision History Document Title: CYTVII-B-H-8M-176-CPU Evaluation Board User Guide Document Number: 002-25907 Revision ECN# Issue Date Description of Change 6493098 02/25/2019 New User Guide 6923377 07/15/2020 Updated Overview chapter on page Updated description (Added content under Figure 2-1).
Need help?
Do you have a question about the Cypress CYTVII-B-H-8M-176-CPU and is the answer not in the manual?
Questions and answers