Data General NOVA 4/C Field Engineering Maintenance Manual page 91

Data General Corporation (DGC) has prepared this manual for use by DGC personnel and customers as a guide to the proper installation, operation, and
maintenance of DGC equipment and software. The drawings and specifications contained herein are the property of DGC and shall neither be reproduced in whole or
in part without DGC's prior written approval nor be implied to grant any license to make, use, or sell equipment manufactured in accordance herewith.
BAUDRATECLK supplies the UAR/T's transmitter and
receiver clock inputs.
When communicating with the terminal, the UAR/T
transmits and receives character codes in serial form. When
communicating with the CPU under program control, the
UAR/T's transmitter receives data in parallel form from
the ALUOUT bus and the receiver places data in parallel
The modem control signal, Clear to Send, is connected to
the UAR/T's transmitter clock input line and inhibits data
transmission when at the low state.
The real-time clock option provides four
program-selectable time bases: power line frequency, 10
Hz, 100 Hz, and 1000 Hz.
The Busy and Done flags and the priority mask bits for
these devices are located in the I/O flag register, which
resides in the data manipulation unit.
The non-maskable interrupt control compares previous
interrupt conditions (which are stored in the RF register in
the control processor) with current interrupt conditions.
Whenever a current condition differs from the
corresponding previous condition, the interrupt control
generates a non-maskable interrupt. Next, the control
processor equalizes both sets of interrupt conditions so the
interrupt control can detect future interrupt conditions.
An interrupt condition occurs when main memory
generates a refresh interrupt request, the interface receives
a start bit, the receiver buffer contains a character, the
transmitter buffer is empty, or the real-time clock changes
INTERCONNECTION WITH SYSTEM
The CPU board communicates with the rest of the system
via its A and B connectors to the backpanel. Tables 11.1
through 11.9 list each signal either generated or received
by the CPU board together with the backpanel location of
the signal. See Interface Designer's Reference (DGC No.
015-000031) for more information on how the I/O signals
Signal Back- Source | Destination | Description
panel Pin
B40CLK A36 Power CPU 40 MHz square
LCLK A88 Power CPU 50/60 Hz
Supply square wave
frequency)
500HZ A90 Power CPU 500 Hz square
Supply wave
Table 11.1 Clock signals
Signal Back- | Source | Destination | Description
Pin
Supply voltage OK
MEMDIASTER B96 CPU Power Supply | Failure on
-5MEM
Table 11.2 Memory control signals
Signal Back- Source | Destination | Description
DCHA A60 CPU \/O Data channel
acknowledge
DCHI B37 CPU 1/0 Data channel
input
DCHO B33 CPU 1/O Data channel
DCHMO B17 1/O CPU Data channel
mode select
DCHR B35 1/O CPU Data channel
request
device
INTA A40 CPU 1/O Interrupt
acknowledge
INTR B29 (/O CPU Interrupt
RQENB B41 CPU 1/0 Request
synchronizing
clock
busy
device done
Table 11.3 Data channel and interrupt signals
Signal Back- Source | Destination | Description
DSO A72 CPU 1/O Device select
| bit O
DS1 A68 CPU 1/O Device select
bit 1
DS2 A66 CPU 1/0 Device select
DS3 A46 CPU 1/O Device select
DS4 A62 CPU 1/O Device select
bit 4
DS5 A64 CPU 1/O Device select
Table 11.4 |/O device code