Cpu Operation; Control Processor - Data General NOVA 4/C Field Engineering Maintenance Manual

Data General Corporation (DGC) has prepared this manual for use by DGC personnel and customers as a guide to the proper installation, operation, and
maintenance of DGC equipment and software. The drawings and specifications contained herein are the property of DGC and shall neither be reproduced in whole or
in part without DGC's prior written approval nor be implied to grant any license to make, use, or sell equipment manufactured in accordance herewith.
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Chapter 11
CPU OPERATION
INTRODUCTION
The NOVA 4/C CPU board is a multi-function board
consisting of a central processing unit (CPU), main
memory, a virtual console, and an asynchronous
communications interface. A real-time clock is optional.
CPU - governs the system's activities by executing assembly
language instructions. It executes the NOVA instruction
set enhanced with load and store byte instructions and,
optionally, signed multiply and divide instructions. The
CPU operates in two modes: run and console. In run mode,
it executes instructions stored in main memory. In console
mode, it executes instructions stored in the virtual console.
Main memory - provides either 32K bytes (16K words) or
64K bytes (32K words) of dynamic random access memory.
Virtual console - allows a user to examine and modify the
system's state using a terminal (system terminal) connected
to the resident asynchronous interface.
Asynchronous interface - a programmed I/O controller
which contains both a transmitter and a receiver. It
provides full-duplex communication between a serial
asynchronous terminal and the CPU.
Real-time clock - an option which provides the system with
four program selectable time bases.
The major units of the CPU board are interconnected by
three 16-bit buses: ALUIN, ALUOUT, MBUS. The CPU board,
in turn, is connected to the system controllers by the 48-line
I/O bus. This bus consists of the 16-bit DATA bus, which
transfers all data, plus 32 lines which carry programmed
I/O, program interrupt, data channel, and system control
signals. Figure 11.1 shows the interconnection of these
CPU
The two major components of the CPU are a control
The control processor executes the NOVA 4/C instruction
set by interpreting each assembly language instruction as
a macroinstruction. It decodes the macroinstruction and
then executes the sequence of microinstructions needed to
perform the specified function. When executed, these
microinstructions control the data paths and the operation
of the data manipulation unit as well as the operation of
main memory and input/output.
Control Processor
The control processor consists of the following major units:
e System timing logic
e Instruction register
e Starting address generator (SAGE)
e I/O and EA decode logic
e Microsequencer
¢ Control store
e Two microinstruction registers
e ALC decode logic
e Control decode logic
e Test logic
Figure 11.2 shows the interconnection of these units.
System Timing Logic
The system timing logic generates the following system
clocks from the the B40CLK (EXT40CLK) clock supplied by
the power supply. (The B40CLK generated by the power
supply is called EXT40CLK on the CPU board and is inverted
before being used.)
¢ BUFACLK
¢ BUFBCLK
¢ B40CLK
° 20CLK
¢ 10CLK
¢ 5CLK
BUFACLK and BUFBCLK are nominally 200 ns clocks which
provide the microinstruction cycle timing. BUFACLK is the
complement of BUFBCLK. In other words, they are 100 ns
out of phase. BUFACLK, together with B40CLK, 10CLK, and
5CLK provide the timing for main memory.
Instruction Register
This register stores the instructions which the control
processor receives from memory in run mode and from
the virtual console in console mode.
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