Data General NOVA 4/C Field Engineering Maintenance Manual page 84

Data General Corporation (DGC) has prepared this manual for use by DGC personnel and customers as a guide to the proper installation, operation, and
maintenance of DGC equipment and software. The drawings and specifications contained herein are the property of DGC and shall neither be reproduced in whole or
in part without DGC's prior written approval nor be implied to grant any license to make, use, or sell equipment manufactured in accordance herewith.
MAIN MEMORY
VIRTUAL
CONSOLE
SCRATCHPAD
RAM
FROM 1t/O
BUS
BUS
ASYNCHRONOUS [f
INTERFACE
J
mM TERMINAL
DG-07339
Figure 11.1 CPU board block diagram
Starting Address Generator (SAGE) instruction, the I/O and EA decode logic determines which
branch in the sequence the control processor executes. The
The SAGE determines the starting address for the next I/O and EA decode logic supplies the starting address of
sequence of microinstructions to be executed and supplies this branch to the control store.
this address to the control store via the microinstruction
sequencer. Before the control processor begins a new Microinstruction Sequencer
sequence of microinstructions, the SAGE examines the
state of the service request lines listed below. These lines The microinstruction sequencer supplies the control store
are listed in order of priority with a service request from with the eight high-order address bits of the next
the data channel having the highest priority and a service microinstruction in the sequence to be executed.
request from an instruction having the lowest priority. A
non-maskable interrupt from the memory refresh logic is Each microinstruction specifies a state change condition (a
an exception to this priority structure. Such an interrupt test) that determines what information the
takes highest priority. microinstruction register uses to generate the address. This
l. Data channel information determines the address of the instruction
2. I/O or non-maskable interrupt "after the next instruction" to be executed. If the control
3. Instruction processor finds that the specified condition is true, the
If a service request is present, the SAGE generates the microinstruction sequencer uses the information specified
appropriate starting address for the service request with by the true field of the current microinstruction; otherwise,
the highest priority. it uses the information specified by the false field.
1/O and EA Decode Logic Control Store
This logic supplements the decoding of I/O instructions The control store contains 48-bit microinstructions stored
and memory reference instructions done by the SAGE. in six 012 word by 8-bit ROMs organized in two banks
After the SAGE selects the sequence of microinstructions (pages) of three ROMs. Each microinstruction is divided
needed to execute the I/O instruction or memory reference into two 24-bit parts - an A half and a B half. These halves