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Y-MP Series
Theory of operation
Cray Y-MP Series Theory Of Operation
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Contents
Table of Contents
Bookmarks
Table of Contents
Section 1
Notational Conventions
Related Publications
Table of Contents
Appendix A - Engini
Warning and Control Systi<:.\1
1- Cray Y-Mp Physical Of-Scription
Powersupplies
Logic Chassis
Cooling
Power Supplies
Figure 1-3. Power-Supply Configuration (Rear View)
Logic Chassis
Module Description
CPU Module
Figure 1-8. Memory Chip Group Layout
2-Centralmemory
Overview
Preliminary Information
Cpu Module
Memory Module
Cpu Data Registers
Address Functional Units
Address Fcnctional Units
Section 2
Lospchannelpairs
LOSP Channel Signals
Preliminary Information
LOSP Channel Errors
HISP Channel Signals
Data Transfer Signals
Initialization Signals
HISP Channel Errors
Vhisp Channels
VHISP Channel Signals
Input Transfer Signals
Output Transfer Signals
VHISP Channel Programming
VHISP Channel Errors
I/O Channel Memory Access
Channel Control Paths
Hardware Implementation
DA and DB Options
DC Option
DD Option
DE Option
HISP Address Channels
DJ Option
YR Option
Output Data Paths
System Clock
Option Descriptions
Clock Speed Select
L!-SYSTEMCLOCKMODULE
FAN-OUT Sche:vle
Forced 0 and 1 Fanouts
CLOCK .MODULE Tuni:\Ig
Section 3
Macrocellarrayoverview
The Mca2500Ecl Macrocell Array Layout
Major Cells
Clock Pulse Generator Cell
Macrocell Array Packaging
Macrocell Library Diagrams
Macrocell Library Table
Mca2500Ecl Macrocell Array Esd Sensitivity
Section 4
Appendix A - Engineering Documentation
Clock Period and Time Segments
Boolean
Cover Sheet
Boolean Equations
Option Design Change History
Option Pinouts
Module Board Layouts
Chip Map
Pcbd Documents
Connector Maps
Cpuchipmap
Load Charts
PCLDCPU Document
PCTAB Document
PCLD Documents
Subsection Data Documents
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CRAY Y--Mp Series
Theory of Op'e-ratidns Manual
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Chapters
Section 1
8
Section 2
118
Section 3
175
Section 4
208
Table of Contents
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