User Manuals: Cray 24 Supercomputer Manufacturer

Manuals and User Guides for Cray 24 Supercomputer Manufacturer. We have 1 Cray 24 Supercomputer Manufacturer manual available for free PDF download: Reference Manual

Cray 24 Reference Manual

Cray 24 Reference Manual (252 pages)

Brand: Cray | Category: Desktop | Size: 15 MB

Table of Contents

Table of Contents
5
System Description
13
- Introduction
  13
- Conventions
  16
  - Italics
    16
  - Register Conventions
    16
  - Number Conventions
    16
  - Clock Period
    16
  - Central Processing Units
    17
Basic Organization of the Dual-Processor System
17
- Interfaces
  19
- I/O Subsystem
  21
- Disk Storage Units
  23
DD-29 Disk Storage Unit
23
- Solid-State Storage Device
  24
- Condensing Units
  25
- Power Distribution Units
  26
- Motor-Generator Units
  27
- System Configuration
  28
Block Diagram of CRAY X-MP Dual-Processor System with Full Disk Capacity
28
- With Block Multiplexer Channels
  29
Cpu Shared Resources
31
- Introduction
  31
- Central Memory
  31
  - Memory Organization
    32
Central Memory Organization for a Dual-Processor System
32
- Memory Addressing
  33
  - Memory Addressing for 6-Co1Umn Mainframe
    33
6-Column Memory Address (32 Banks)
33
6-Column Memory Address (16 Banks)
33
- Memory Access
  34
L2-Column Memory Address (16 Banks)
34
- Conflict Resolution
  37
  - Bank Busy Conflict
    37
  - Simultaneous Bank Conflict
    37
  - Section Access Conflict
    37
  - Memory Access Priorities
    37
  - Memory Error Correction
    38
Memory Data Path with SECDED
38
Error Correction Matrix
39
- Inter-Cpu Communication Section
  40
  - Real-Time Clock
    40
  - Inter-CPU Communication and Control
    41
Shared Registers and Real-Time Clock
41
- Shared Address and Shared Scalar Registers
  42
- Semaphore Registers
  42
Access Conflicts to Shared Registers
43
Channel Word Assembly/Disassembly
48
- Input Channel Programming
  49
Basic I/O Program Flowchart
49
- Input Channel Error Conditions
  50
- Output Channel Programming
  50
- Ready Signal
  50
- Programmed Master Clear to External Device
  51
- Memory Access
  51
Channel I/O Control (Shown for One Processor)
52
Input/Output Data Paths
53
- Memory Bank Conflicts
  54
- I/O Memory Conflicts
  54
- I/O Memory Request Conditions
  55
- I/O Memory Addressing
  55
Instruction Issue and Control Elements
57
- Next Instruction Parcel Register
  58
- Current Instruction Parcel Register
  58
- Lower Instruction Parcel Register
  59
- Instruction Buffers
  59
- Exchange Mechanism
  61
  - Exchange Package
    61
Cpu Control Section
57
- Introduction
  57
- Instruction Issue and Control
  57
Exchange Package for a Dual-Processor System
62
- Vector Not Used (VNU)
  63
Exchange Package Assignments
63
- Memory Error Data
  64
- Exchange Registers
  65
  - Exchange Address Register
    65
  - Mode Register
    65
  - Flag Register
    67
  - Cluster Number Register
    68
  - Program State Register
    68
  - A Registers
    68
  - Program Address Register
    69
  - Memory Field Registers
    69
  - Active Exchange Package
    69
    
    Exchange Sequence
    69
    
    Exchange Initiated by Deadstart Sequence
    70
    
    Exchange Initiated by Interrupt Flag Set
    70
    
    Exchange Initiated by Program Exit
    70
    
    Exchange Sequence Issue Conditions
    71
  - Exchange Package Management
    71
- Memory Field Protection
  72
- Programmable Clock
  75
  - Instructions
    75
Interrupt Interval Register
75
- Interrupt Countdown Counter
  76
Clear Programmable Clock Interrupt Request
76
- Deadstart Sequence
  77
Cpu Computation Section
79
- Introduction
  79
- Operating Registers
  81
- Address Registers
  81
  - A Registers
    81
Address Registers and Functional Units
82
- B Registers
  83
- Scalar Registers
  84
  - S Registers
    84
Scalar Registers and Functional Units
85
- T Registers
  86
- Vector Registers
  87
  - Registers
    87
Vector Registers and Functional Units
88
Integer Data Formats
100
- Normalized Floating-Point Numbers
  101
Floating-Point Data Format
101
- Floating-Point Range Errors
  102
  - Floating-Point Add Functional Unit
    102
Exponent Matrix for Floating-Point Multiply Unit
103
Integer Multiply in Floating-Point Multiply Functional Unit
105
- Multiplication Algorithm
  106
Floating-Point Multiply Partial-Product Sums Pyramid
107
- Division Algorithm
  108
  - Newton's Method
    108
  - Derivation of the Division Algorithm
    109
- Logical Operations
  113
I-Parcel Instruction Format with Discrete J and K Fields
115
- I-Parcel Instruction Format with Combined J and
  116
- And K Fields
  116
Cpu Instructions
115
- Instruction Format
  115
  - And K Fields
    115
2-Parcel Instruction Format with Combined J, K, and
116
- And M Fields
  118
- Special Register Values
  118
2-Parcel Instruction Format for a Branch with
118
Combined I, J, K, and M Fields
118
2-Parcel Instruction Format for a 24-Bit Immediate Constant
118
- Instruction Issue
  119
- Instruction Descriptions
  120
Vector Left Double Shift, First Element, VL Greater than
185
Vector Left Double Shift, Second Element, VL Greater than
185
Vector Left Double Shift, Last Element
185
Vector Right Double Shift, First Element
186
Vector Right Double Shift, Last Operation
187
Instruction Summary for Cray X-Mp Models 22 and
207
- Cray
  207
Mbyte Per Seoond Channel Descriptions
215
- Introduction
  215
- Mbyte Per Seoond Input Channel Signal Sequence
  215
  - Data Bits 20 through 2 15
    215
  - Parity Bits 0 through 3
    216
Resume Signal
217
Disconnect Signal
217
- Selecting Performance Events
  221
- Mbyte Per Second Output Channel Signal Sequence
  245
  - Data Bits 2 0 through 2
    245
  - Parity Bits 0 through 3
    245
- Testing Performance Counters
  245
- Verification of Check Bit Storage
  245
- Verification of Check Bit Generation
  245
Control and Data Paths for a Single CPU
245
Typical Interface Cabinet
245
I/O Subsystem Chassis
245
Verification of Error Detection and Correction
245
Instruction Buffers
248

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