Icom IC-F10 Service Manual page 10

5-2-5 APC CIRCUIT (RF UNIT)
The APC circuit protects the power module (IC5) from a
mismatched output load and selects HIGH and LOW output
power.
Tne APC detector circuit (L14, D11, D12) detects forward
signals and rectified signals at D11 and D12 respectively.
The combined voltage is at a minimum level when the
antenna is matched at 50 Q and is increased when it is
mismatched.
The detected voltage is applied to a differential amplifier
circuit (018а). Тһе APC reference voltage is determined
by the power output control circuit (MAIN unit Q16). The
APC reference voltage is applied to the base of Q18b.
When the antenna impedance is mismatched, the base
voltage of Q18a exceeds the reference voltage. The
collector voltage of Q18a decreases.
The current from the differential amplifier circuit (Q18a,
Q18b) is amplified at Q19, then controls the bias voltage
of the power module (IC3) until the base voltage of Q18a
reaches the same level as the voltage of Q18b.
* APC CIRCUIT
RF signal
from ©з 3
5-3 PLL CIRCUITS
5-3-1 GENERAL
A PLL circuit provides stable oscillation of the transmit
frequency and the receive local frequency. The PLL
circuit compares the phase of the divided VCO frequency
to the reference frequency. The PLL output frequency
is controlled by a crystal oscillator and the divided ratio
(N-data) of a programmable divider.
5-3-2 PLL CIRCUIT (RF UNIT)
The РЦ circuit, using a one стр РЦ. IC (ІС2), directly
generates the transmit frequency and receive 1st LO
frequency with a VCO. The PLL IC sets the divided ratio
based on serial data from the CPU on the LOGIC unit and
compares the phases of a VCO signa! and the reference
oscillator frequency. The PLL IC detects the out-of-step
phase and outputs it from pin 7.
5-3-3 REFERENCE OSCILLATOR CIRCUIT
(RF UNIT)
A 12.8 MHz stable frequency is oscillated at X3 and Q17.
The frequency is adjusted with C112. The frequency is
divided by 2560 or 2048 to obtain the PLL reference
frequency (5 kHz or 6.25 kHz).
5-3-4 PROGRAMMABLE DIVIDER AND
PHASE DETECTOR CIRCUITS
(RF UNIT)
The VCO generated signal (PLL LO signal) is amplified at
Q9, and is applied to a РЦ. IC (IC2 pin 5). The PLL LO
signal is divided at the programmable divider section and
is then applied to the phase detector section.
The phase detector compares the input signal and the
reference frequency, and outputs the out of phase signal
(pulse signal) from pin 7.
* PLL CIRCUIT
зөвөө ссєллээлэааэаэхэ ч э эээ.
PLL lock voltage
RX
1st mixer
Q2
Mawwuwncas....................... ши Tx
Pre-driver
Q13
IC2
7 5
Рһазе N Programmable! Eo
detector counter
Reference
osc. Q17, X3
12.8 MHz
Fig. 4
5-3-5 CHARGE PUMP AND LOOP FILTER
CIRCUITS (RF UNIT)
The phase detected signal is applied to the charge pump
(Q4, Q5) and the lag-lead loop filter (R34, C53). The
loop filter converts the pulse signal to DC voltage while
increasing the DC voltage range.