Table of Contents
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1. Features
■
enCoRe™ II Low Voltage (enCoRe II LV)—enhanced
component reduction
❐
Internal crystalless oscillator with support for optional exter-
nal clock or external crystal or resonator
❐
Configurable IO for real world interface without external com-
ponents
■
Enhanced 8-bit microcontroller
❐
Harvard architecture
❐
M8C CPU speed up to 12 MHz or sourced by an external
crystal, resonator, or clock signal
■
Internal memory
❐
256 bytes of RAM
❐
8 Kbytes of Flash including EEROM emulation
■
Low power consumption
❐
Typically 2.25 mA at 3 MHz
5 μA sleep
❐
■
In-system reprogrammability
❐
Allows easy firmware update
■
General purpose IO ports
❐
Up to 36 General Purpose IO (GPIO) pins
❐
2 mA source current on all GPIO pins. Configurable 8 or
50 mA per pin current sink on designated pins
❐
Each GPIO port supports high impedance inputs, config-
urable pull up, open drain output, CMOS and TTL inputs, and
CMOS output
❐
Maskable interrupts on all IO pins
2. Logic Block Diagram
Internal
12 MHz
Oscillator
Clock
Control
Crystal
Oscillator
CY7C601xx only
POR /
Low-Voltage
Detect
Cypress Semiconductor Corporation
Document 38-16016 Rev. *E
enCoRe™ II Low Voltage Microcontroller
■
SPI serial communication
❐
❐
❐
■
2-channel 8-bit or 1-channel 16-bit capture timer registers.
Capture timer registers store both rising and falling edge times
❐
❐
❐
■
Internal low power wakeup timer during suspend mode
❐
■
Programmable interval timer interrupts
■
Reduced RF emissions at 27 MHz and 96 MHz
■
Watchdog timer (WDT)
■
Low voltage detection with user selectable threshold voltages
■
Improved output drivers to reduce EMI
■
Operating voltage from 2.7V to 3.6V DC
■
Operating temperature from 0–70°C
■
Available in 24 and 40-pin PDIP, 24-pin SOIC, 24-pin QSOP
and SSOP, 28-pin SSOP, and 48-pin SSOP
■
Advanced development tools based on Cypress PSoC
■
Industry standard programmer support
4 SPI/GPIO
Interrupt
Pins
Control
RAM
M8C CPU
256 Byte
Watchdog
Timer
•
198 Champion Court
CY7C601xx, CY7C602xx
Master or slave operation
Configurable up to 2 Mbit per second transfers
Supports half duplex single data line mode for optical sensors
Two registers each for two input pins
Separate registers for rising and falling edge capture
Simplifies interface to RF inputs for wireless applications
Periodic wakeup with no external components
16 GPIO
16 Extended
Pins
I/O Pins
Flash
12-bit Timer
8K Byte
,
•
San Jose
CA 95134-1709
®
tools
Wakeup
Timer
Capture
Timers
•
408-943-2600
Revised December 08, 2008
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Related Manuals for Cypress Semiconductor enCoRe CY7C601xx
Summary of Contents for Cypress Semiconductor enCoRe CY7C601xx
- Page 1 1. Features ■ enCoRe™ II Low Voltage (enCoRe II LV)—enhanced component reduction ❐ Internal crystalless oscillator with support for optional exter- nal clock or external crystal or resonator ❐ Configurable IO for real world interface without external com- ponents ■ Enhanced 8-bit microcontroller ❐...
- Page 2 3. Applications The CY7C601xx and CY7C602xx are targeted for the following applications: ■ PC wireless HID devices ❐ Mice (optomechanical, optical, trackball) ❐ Keyboards ❐ Presenter tools ■ Gaming ❐ Joysticks ❐ Gamepad ■ General purpose wireless applications ❐ Remote controls ❐...
- Page 3 6. Pinouts CY7C60223 24-Pin PDIP P1.3/SSEL P3.0 P3.1 P1.2 SCLK/P1.4 P1.1 SMOSI/P1.5 P1.0 SMISO/P1.6 P1.7 P2.0 P2.1 P0.0/CLKIN P0.7 P0.1/CLKOUT TIO1/P0.6 P0.2/INT0 TIO0/P0.5 INT2/P0.4 P0.3/INT1 CY7C60113 28-Pin SSOP P2.7 P3.7 P3.6 P2.6 P3.5 P2.5 P3.4 P2.4 P1.7 P0.7 P1.6/SMISO TIO1/P0.6 TIO0/P0.5 P1.5/SMOSI P1.4/SCLK...
- Page 4 6.1 Pin Assignments Table 6-1. Pin Assignments SSOP PDIP SSOP QSOP SOIC PDIP Document 38-16016 Rev. *E Name P4.0 GPIO Port 4—configured as a group (nibble) P4.1 P4.2 P4.3 P3.0 GPIO Port 3—configured as a group (byte) P3.1 P3.2 P3.3 P3.4 P3.5 P3.6...
- Page 5 Table 6-1. Pin Assignments (continued) SSOP PDIP SSOP QSOP SOIC PDIP 1,2,3, 45,46, 47,48 – – Document 38-16016 Rev. *E Name P0.0/CLKIN GPIO Port 0 bit 0—Configured individually On CY7C601xx, optional Clock In when external oscillator is disabled or external oscillator input when external oscillator is enabled.
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Page 6: Register Summary
7. Register Summary Table 7-1. enCoRe II LV Register Summary The XIO bit in the CPU Flags Register must be set to access the extended register space for all registers above 0xFF. Addr Name P0DATA P0.7 P0.6/TIO1 P0.5/TIO0 P1DATA P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P2DATA P3DATA... - Page 7 Table 7-1. enCoRe II LV Register Summary (continued) The XIO bit in the CPU Flags Register must be set to access the extended register space for all registers above 0xFF. Addr Name IOSCTR foffset[2:0] XOSCTR Reserved LPOSCTR 32 kHz Low Reserved Power SPIDATA...
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Page 8: Cpu Architecture
8. CPU Architecture This family of microcontrollers is based on a high performance, 8-bit, Harvard architecture microprocessor. Five registers control the primary operation of the CPU core. These registers are affected by various instructions, but are not directly accessible through the register space by the user. Table 8-1. - Page 9 9.1.1 Accumulator Register Table 9-2. CPU Accumulator Register (CPU_A) Bit # Field Read/Write – – Default Bit [7:0]: CPU Accumulator [7:0] 8-bit data value holds the result of any logical or arithmetic instruction that uses a source addressing mode. 9.1.2 Index Register Table 9-3.
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Page 10: Addressing Modes
9.2 Addressing Modes 9.2.1 Source Immediate The result of an instruction using this addressing mode is placed in the A register, the F register, the SP register, or the X register, which is specified as part of the instruction opcode. Operand 1 is an immediate value that serves as a source for the instruction. - Page 11 9.2.5 Destination Indexed The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is added to the X register forming the address that points to the location of the result. The source for the instruction is the A register.
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Page 12: Instruction Set Summary
9.2.9 Source Indirect Post Increment The result of an instruction using this addressing mode is placed in the Accumulator. Operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the source of the instruction. The indirect address is incremented as part of the instruction execution. - Page 13 Table 10-1. Instruction Set Summary Sorted Numerically by Opcode Order (continued) [1, 2] Instruction Format Flags 13 7 2 SUB A, [X+expr] C, Z 14 7 2 SUB [expr], A C, Z 15 8 2 SUB [X+expr], A C, Z 16 9 3 SUB [expr], expr C, Z...
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Page 14: Memory Organization
11. Memory Organization 11.1 Flash Program Memory Organization Figure 11-1. Program Memory Space with Interrupt Vector Table after reset 16-bit PC Document 38-16016 Rev. *E Address 0x0000 Program execution begins here after a reset 0x0004 POR/LVD 0x0008 INT0 0x000C SPI Transmitter Empty 0x0010 SPI Receiver Full 0x0014... -
Page 15: Data Memory Organization
11.2 Data Memory Organization The CY7C601xx and CY7C602xx microcontrollers provide up to 256 bytes of data RAM After Reset 8-bit PSP Top of RAM Memory 11.3 Flash This section describes the Flash block of enCoRe II LV. Much of the visible Flash functionality, including programming and security, are implemented in the M8C Supervisory Read Only Memory (SROM). - Page 16 Two important variables used for all functions are KEY1 and KEY2. These variables help discriminate between valid and inadvertent SSCs. KEY1 always has a value of 3Ah, while KEY2 has the same value as the stack pointer when the SROM function begins execution.
- Page 17 11.5.3 WriteBlock Function The WriteBlock function is used to store data in Flash. Data is moved 64 bytes at a time from SRAM to Flash using this function. The WriteBlock function first checks the protection bits and deter- mines if the desired BLOCKID is writable. If write protection is turned on, the WriteBlock function exits setting the accumulator and KEY2 back to 00h.
- Page 18 Table 11-8. ProtectBlock Parameters Name Address Description KEY1 0,F8h KEY2 0,F9h Stack Pointer value when SSC is executed CLOCK 0,FCh Clock Divider used to set the write pulse width DELAY 0,FEh For a CPU speed of 12 MHz set to 56h 11.5.6 EraseAll Function The EraseAll function performs a series of steps that destroy the user data in the Flash macros and resets the protection block in...
- Page 19 11.6 SROM Table Read Description The Silicon IDs for enCoRe II LV devices are stored in SROM tables in the part, as shown in The Silicon ID can be read out from the part using SROM Table reads. This is demonstrated in the following pseudo code. As mentioned in the section SROM on page 15, the SROM variables occupy address F8h through FFh in the SRAM.
- Page 20 Silicon ID Table 0 [15-8] Family / Table 1 Die ID Table 2 32 KHz Table 3 LPOSCTR at 3.30V Table 4 Table 5 Table 6 Table 7 11.6.1 Checksum Function The Checksum function calculates a 16-bit checksum over a user specifiable number of blocks, within a single Flash macro (Bank) starting from block zero.
- Page 21 12. Clocking The enCoRe II LV has two internal oscillators, the internal 24 MHz oscillator and the 32 kHz low power oscillator. The internal 24 MHz oscillator is designed such that it is trimmed to an output frequency of 24 MHz over temperature and voltage variation.
- Page 22 When using the 32 kHz oscillator, the PITMRL/H is read until two consecutive readings match before sending and receiving data. The following firmware example assumes the developer is interested in the lower byte of the PIT. Read_PIT_counter: mov A, reg[PITMRL] mov [57h], A mov A, reg[PITMRL] mov [58h],A...
- Page 23 P0.1 CLKOUT P0.0 CLKIN Crystal Oscillator Disabled CLK_EXT CLK_24MHz Table 12-2. CPU Clock Configuration (CPUCLKCR) [0x30] [R/W] Bit # Field Read/Write – – Default Bit [7:1]: Reserved Bit 0: CPU CLK Select 0 = Internal 24 MHz Oscillator 1 = External oscillator source Note The CPU speed selection is configured using the OSC_CR0 Register Table 12-3.
- Page 24 Table 12-3. OSC Control 0 (OSC_CR0) [0x1E0] [R/W] (continued) Read/Write – – Default Bit [7:6]: Reserved Bit 5: No Buzz During sleep (the Sleep bit is set in the CPU_SCR to detect any POR and LVD events on the V cycle—Table 15-3).
- Page 25 Table 12-4. Clock IO Configuration (CLKIOCR) [0x32] [R/W] Bit # Reserved Field Read/Write – – Default Bit [7:5]: Reserved Bit 4: XOSC Select This bit, when set, selects the external crystal oscillator clock as clock source of external clock. When selecting the crystal oscillator clock, first enable the crystal oscillator and wait for few cycles.
- Page 26 Figure 12-2. Programmable Interval Timer Block Diagram Configuration System Clock Clock Timer 12.2.3 Timer Capture Clock (TCAPCLK) The Timer Capture clock (TCAPCLK) is sourced from the external crystal oscillator, the internal 24 MHz oscillator or the internal 32 kHz low power oscillator. A programmable prescaler of 2, 4, 6, or 8 then divides the selected source. Captimer Clock Document 38-16016 Rev.
- Page 27 Table 12-5. Timer Clock Configuration (TMRCLKCR) [0x31] [R/W] Bit # Field TCAPCLK Divider Read/Write Default Bit [7:6]: TCAPCLK Divider [1:0] TCAPCLK Divider controls the TCAPCLK divisor. 0 0 = Divider Value 2 0 1 = Divider Value 4 1 0 = Divider Value 6 1 1 = Divider Value 8 Bit [5:4]: TCAPCLK Select The TCAPCLK Select field controls the source of the TCAPCLK.
- Page 28 12.2.4 Internal Clock Trim Table 12-6. IOSC Trim (IOSCTR) [0x34] [R/W] Bit # Field foffset[2:0] Read/Write Default The IOSC Calibrate Register is used to calibrate the internal oscillator. The reset value is undefined, but during boot the SROM writes a calibration value that is determined during manufacturing test. The ‘D’ indicates that the default value is trimmed to 24 MHz at 3.30V at power on.
- Page 29 12.2.6 LPOSC Trim Table 12-8. LPOSC Trim (LPOSCTR) [0x36] [R/W] Bit # Field 32 kHz Low Reserved Power Read/Write – Default – This register is used to calibrate the 32 kHz low speed oscillator. The reset value is undefined but during boot the SROM writes a calibration value that is determined during manufacturing test.
- Page 30 13. Reset The microcontroller supports two types of resets: Power on Reset (POR) and Watchdog Reset (WDR). When reset is initiated, all registers are restored to their default states and all interrupts are disabled. The occurrence of a reset is recorded in the System Status and Control Register (CPU_SCR). Bits within this register record the occurrence of POR and WDR Reset respectively.
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Page 31: Power On Reset
13.1 Power On Reset POR occurs every time the power to the device is switched on. POR is released when the supply is typically 2.6V for the upward supply transition, with typically 50 mV of hysteresis during the power on transient. Bit 4 of the System Status and Control Register (CPU_SCR) is set to record this event (the register contents are set to 00010000 by the POR). - Page 32 14.1 Sleep Sequence The SLEEP bit is an input into the sleep logic circuit. This circuit is designed to sequence the device into and out of the hardware sleep state. The hardware sequence to put the device to sleep is shown in Figure 14-1.
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Page 33: Wakeup Sequence
14.2 Wakeup Sequence When asleep, the only event that wakes the system up is an interrupt. The global interrupt enable of the CPU flag register need not be set. Any unmasked interrupt wakes the system up. It is optional for the CPU to actually take the interrupt after the wakeup sequence. - Page 34 15. Low Voltage Detect Control Table 15-1. Low Voltage Control Register (LVDCR) [0x1E3] [R/W] Bit # Field Reserved Read/Write – – Default This register controls the configuration of the Power on Reset and Low Voltage Detection circuit. This register is accessed only in the second bank of IO space.
- Page 35 15.1 POR Compare State Table 15-2. Voltage Monitor Comparators Register (VLTCMP) [0x1E4] [R] Bit # Field Read/Write – – Default This read-only register allows reading the current state of the LVD and PPOR comparators. Bit [7:2]: Reserved Bit 1: LVD This bit is set to indicate that the LVD comparator has tripped, indicating that the supply voltage has gone below the trip point set by VM[2:0] (See Table...
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Page 36: General Purpose Io Ports
16. General Purpose IO Ports 16.1 Port Data Registers 16.1.1 P0 Data Table 16-1. P0 Data Register (P0DATA)[0x00] [R/W] Bit # Field P0.7 P0.6/TIO1 Read/Write Default This register contains the data for Port 0. Writing to this register sets the bit values to be output on output enabled pins. Reading from this register returns the current state of the Port 0 pins. -
Page 37: Gpio Port Configuration
16.1.3 P2 Data Table 16-3. P2 Data Register (P2DATA) [0x02] [R/W] Bit # Field Read/Write Default This register contains the data for Port 2. Writing to this register sets the bit values to be output on output enabled pins. Reading from this register returns the current state of the Port 2 pins. - Page 38 16.2.4 High Sink When set, the output sinks up to 50 mA. When clear, the output sinks up to 8 mA. On the CY7C601xx, only the P3.7, P2.7, P0.1, and P0.0 have 50 mA sink drive capability. Other pins have 8 mA sink drive capability.
- Page 39 16.2.10 P0.1/CLKOUT Configuration Table 16-7. P0.1/CLKOUT Configuration (P01CR) [0x06] R/W] Bit # Field CLK Output Int Enable Read/Write Default This pin is shared between the P0.1 GPIO use and the CLKOUT pin for the external crystal oscillator. When the external oscillator is enabled the settings of this register are ignored.
- Page 40 16.2.12 P0.5/TIO0–P0.6/TIO1 Configuration Table 16-9. P0.5/TIO0–P0.6/TIO1 Configuration (P05CR–P06CR) [0x0A–0x0B] [R/W] Bit # Field TIO Output Int Enable Read/Write Default These registers control the operation of pins P0.5 through P0.6, respectively. P0.5 and P0.6 are shared with TIO0 and TIO1 respectively. To use these pins as capture timer inputs, configure them as inputs by clearing the corresponding Output Enable.
- Page 41 16.2.15 P1.1 Configuration Table 16-12. P1.1 Configuration (P11CR) [0x0E] [R/W] Bit # Field Reserved Int Enable Read/Write – Default This register controls the operation of the P1.1 pin. The pull up resistor on this pin is enabled by the P10CR Register. Note There is no 2 mA sourcing capability on this pin.
- Page 42 16.2.18 P1.4–P1.6 Configuration (SCLK, SMOSI, SMISO) Table 16-15. P1.4–P1.6 Configuration (P14CR–P16CR) [0x11–0x13] [R/W] Bit # Field SPI Use Int Enable Read/Write Default These registers control the operation of pins P1.4–P1.6, respectively. These registers exist in all enCoRe II LV parts. Bit 7: SPI Use 0 = Disable the SPI alternate function.
- Page 43 16.2.21 P3 Configuration Table 16-18. P3 Configuration (P3CR) [0x16] [R/W] Bit # Field Reserved Int Enable Read/Write – Default In CY7C602xx, this register controls the operation of pins P3.0–P3.1. In CY7C601xx, this register controls the operation of pins P3.0–P3.7. The 50 mA sink drive capability is only available on pin P3.7 and only on CY7C601xx. In CY7C602xx, only 8 mA sink drive capability is available on this pin regardless of the setting of the High Sink bit.
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Page 44: Serial Peripheral Interface (Spi)
17. Serial Peripheral Interface (SPI) The SPI Master and Slave Interface core logic runs on the SPI clock domain. The SPI clock is a divider off of the CPUCLK when in Master Mode. SPI is a four pin serial interface comprised of a clock, an enable, and two data pins. Register Block SCK Speed Sel Master/Slave Sel... - Page 45 17.1 SPI Data Register Table 17-1. SPI Data Register (SPIDATA) [0x3C] [R/W] Bit # Field Read/Write Default When read, this register returns the contents of the receive buffer. When written, it loads the transmit holding register. Bit [7:0]: SPI Data [7:0] When an interrupt occurs to indicate to firmware that a byte of receive data is available or the transmitter holding register is empty, firmware has seven SPI clocks to manage the buffers—to empty the receiver buffer or to refill the transmit holding register.
- Page 46 Table 17-3. SPI Mode Timing vs. LSB First, CPOL, and CPHA First CPHA CPOL S C L K S S E L D A T A S C L K S S E L D A T A S C L K S S E L D A T A SC L K...
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Page 47: Timer Registers
Table 17-4. SPI SCLK Frequency SCLK CPUCLK SCLK Frequency when Select Divisor CPUCLK = 12 MHz 2 MHz 1 MHz 250 kHz 125 kHz 17.3 SPI Interface Pins The SPI interface uses the P1.3–P1.6 pins. These pins are configured using the P1.3 and P1.4–P1.6 configuration. 18. - Page 48 Table 18-2. Free Running Timer High Order Byte (FRTMRH) [0x21] [R/W] Bit # Field Read/Write Default Bit [7:0]: Free Running Timer [15:8] When reading the free running timer, the low order byte is read first and the high order second. When writing, the low order byte is written first, then the high order byte.
- Page 49 Table 18-4. Capture Interrupt Enable (TCAPINTE) [0x2B] [R/W] Bit # Field Reserved Read/Write – – Default Bit [7:4]: Reserved Bit 3: Cap1 Fall Enable 0 = Disable the capture 1 falling edge interrupt 1 = Enable the capture 1 falling edge interrupt Bit 2: Cap1 Rise Enable 0 = Disable the capture 1 rising edge interrupt 1 = Enable the capture 1 rising edge interrupt...
- Page 50 Table 18-8. Timer Capture 1 Falling (TCAP1F) [0x25] [R/W] Bit # Field Read/Write Default Bit [7:0]: Capture 1 Falling [7:0] This register holds the value of the free running timer when the last falling edge occurred on the TIO1 input. The bits stored here are selected by the Prescale [2:0] bits in the Timer Configuration register.
- Page 51 Table 18-11. Programmable Interval Timer High (PITMRH) [0x27] [R] Bit # Field Reserved Read/Write Default Bit [7:4]: Reserved Bit [3:0]: Prog Internal Timer [11:8] This register holds the high order nibble of the 12-bit programmable interval timer. Reading this register returns the high order nibble of the 12-bit timer at the instant when the low order byte was last read.
- Page 52 CY7C601xx, CY7C602xx Figure 18-3. Timer Functional Sequence Diagram Document 38-16016 Rev. *E Page 52 of 68 [+] Feedback [+] Feedback...
- Page 53 Figure 18-4. 16-Bit Free Running Counter Loading Timing Diagram clk_sys write valid addr write data FRT reload ready Clk Timer 12b Prog Timer 12b reload interrupt Capture timer 16b free running counter load 16b free 00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AB 00AC 00AD 00AE 00AF 00B0 00B1 00B2 ACBE ACBF ACC0 running counter Figure 18-5.
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Page 54: Interrupt Controller
19. Interrupt Controller The interrupt controller and its associated registers allow the user’s code to respond to an interrupt from almost every functional block in the enCoRe II LV devices. The registers associated with the interrupt controller are disabled either globally or individually. -
Page 55: Interrupt Processing
19.2 Interrupt Processing The sequence of events that occur during interrupt processing is as follows: 1. An interrupt becomes active, either because: a. The interrupt condition occurs (for example, a timer expires). b. A previously posted interrupt is enabled through an update of an interrupt mask register. - Page 56 Table 19-3. Interrupt Clear 1 (INT_CLR1) [0xDB] [R/W] Bit # Field TCAP0 Prog Interval Timer Read/Write Default When reading this register, 0 = There is no posted interrupt for the corresponding hardware. 1 = There is a posted interrupt for the corresponding hardware. Writing a ‘0’...
- Page 57 Table 19-6. Interrupt Mask 2 (INT_MSK2) [0xDF] [R/W] Bit # Field Reserved GPIO Port 4 Int Enable Read/Write – Default Bit 7: Reserved Bit 6: GPIO Port 4 Interrupt Enable 0 = Mask GPIO Port 4 interrupt 1 = Unmask GPIO Port 4 interrupt Bit 5: GPIO Port 3 Interrupt Enable 0 = Mask GPIO Port 3 interrupt 1 = Unmask GPIO Port 3 interrupt...
- Page 58 Table 19-8. Interrupt Mask 0 (INT_MSK0) [0xE0] [R/W] Bit # Field GPIO Port 1 Sleep Timer Int Enable Int Enable Read/Write Default Bit 7: GPIO Port 1 Interrupt Enable 0 = Mask GPIO Port 1 interrupt 1 = Unmask GPIO Port 1 interrupt Bit 6: Sleep Timer Interrupt Enable 0 = Mask Sleep Timer interrupt 1 = Unmask Sleep Timer interrupt...
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Page 59: Absolute Maximum Ratings
20. Absolute Maximum Ratings Storage Temperature ... –40°C to +90°C Ambient Temperature with Power Applied... –0°C to +70°C Supply Voltage on V Relative to V ...–0.5V to +7.0V DC Input Voltage ... –0.5V to + V DC Voltage Applied to Outputs in High-Z State... - Page 60 20.2 AC Characteristics Parameter Description Clock External Clock Duty Cycle ECLKDC External Clock Frequency ECLK2 Internal Main Oscillator Frequency Internal Low Power Oscillator GPIO Timing Output Rise Time R_GPIO Output Fall Time F_GPIO SPI Timing SPI Master Clock Rate SMCK SPI Slave Clock Rate SSCK SPI Clock High Time...
- Page 61 GPIO Pin Output Voltage SCK (CPOL=0) SCKH SCK (CPOL=1) MOSI MISO Document 38-16016 Rev. *E Figure 20-2. GPIO Timing Diagram R_GPIO Figure 20-3. SPI Master Timing, CPHA = 1 (SS is under firmware control in SPI Master mode) SCKL CY7C601xx, CY7C602xx F_GPIO Page 61 of 68 [+] Feedback...
- Page 62 SCK (CPOL=0) SCKH SCK (CPOL=1) MOSI MISO SCK (CPOL=0) SCKH SCK (CPOL=1) MDO1 MOSI MISO Document 38-16016 Rev. *E Figure 20-4. SPI Slave Timing, CPHA = 1 SCKL Figure 20-5. SPI Master Timing, CPHA = 0 (SS is under firmware control in SPI Master mode) SCKL CY7C601xx, CY7C602xx Page 62 of 68...
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Page 63: Ordering Information
SCK (CPOL=0) SCKH SCK (CPOL=1) MOSI SDO1 MISO 21. Ordering Information Ordering Code CY7C60123-PVXC CY7C60123-PXC CY7C60113-PVXC CY7C60223-PXC CY7C60223-SXC CY7C60223-QXC 22. Package Handling Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving the factory. -
Page 64: Package Diagrams
23. Package Diagrams 0.597[15.163] 0.615[15.621] 0.004[0.101] 0.0118[0.299] 0.050[1.270] 0.013[0.330] TYP. 0.019[0.482] Document 38-16016 Rev. *E Figure 23-1. 24-Pin (300-Mil) SOIC S13 NOTE : 1. JEDEC STD REF MO-119 PIN 1 ID 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE. - Page 65 0.033 REF. 0.150 0.157 0.228 0.244 SEATING PLANE 0.053 0.069 0.004 0.004 0.010 Figure 23-4. 28-Pin (5.3 mm) Shrunk Small Outline Package O28 Document 38-16016 Rev. *E Figure 23-3. 24-Pin QSOP O241 PIN 1 ID 0.337 0.344 0.007 0.010 0.008 0.012 0.025 BSC.
- Page 66 CY7C601xx, CY7C602xx Figure 23-5. 40-Pin (600-Mil) Molded DIP P17 51-85019-*A Figure 23-6. 48-Pin Shrunk Small Outline Package O48 51-85061-*C Document 38-16016 Rev. *E Page 66 of 68 [+] Feedback [+] Feedback...
- Page 67 24. Document History Page Document Title: CY7C601xx, CY7C602xx enCoRe™ II Low Voltage Microcontroller Document Number: 38-16016 Orig. of Submission Rev. Change 327601 See ECN 400134 See ECN 505222 See ECN 524104 KKVTMP See ECN 1821746 VGT/FSU/AES See ECN 2620679 CMCC/PYRS Document 38-16016 Rev.
- Page 68 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless wireless.cypress.com Memories memory.cypress.com...
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