1. Manuals
  2. Brands
  3. Cypress Semiconductor Manuals
  4. Microcontrollers
  5. MoBL-USB CY7C68053
  6. Specification sheet

Cypress Semiconductor MoBL-USB CY7C68053 Specification Sheet

Fx2lp18 usb microcontroller
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
1.0
CY7C68053 Features
• USB 2.0 – USB-IF High-Speed and Full-Speed Compliant
(TID# 40000188)
• Single-chip integrated USB 2.0 transceiver, smart SIE, and
enhanced 8051 microprocessor
• Ideal for mobile applications (cell phone, smart phones,
PDAs, MP3 players)
— Ultra low power
— Suspend current: 20 µA (typical)
• Software: 8051 code runs from:
— Internal RAM, which is loaded from EEPROM
• 16 kBytes of on-chip Code/Data RAM
• Four programmable BULK/INTERRUPT/ISOCHRONOUS
endpoints
— Buffering options: double, triple, and quad
• Additional programmable (BULK/INTERRUPT) 64-byte
endpoint
• 8- or 16-bit external data interface
• Smart Media Standard ECC generation
• GPIF (General Programmable Interface)
— Allows direct connection to most parallel interface
— Programmable waveform descriptors and configuration
registers to define waveforms
— Supports multiple Ready (RDY) inputs and Control (CTL)
outputs

Block Diagram

24 MHz
Ext. XTAL
VCC
1.5K
Connected for
Full-Speed
D+
D–
XCVR
Integrated
Full- and High-speed
XCVR
Enhanced USB Core
Simplifies 8051 Code
Cypress Semiconductor Corporation
Document # 001-06120 Rev *F
MoBL-USB™ FX2LP18 USB Microcontroller
High-performance micro
using standard tools
with lower-power options
/0.5
8051 Core
x20
/1.0
12/24/48 MHz,
PLL
/2.0
Four Clocks/Cycle
USB
CY
16 KB
2.0
Smart
RAM
USB
1.1/2.0
Engine
"Soft Configuration"
Easy Firmware Changes
•
198 Champion Court
• Integrated, industry standard enhanced 8051
— 48 MHz, 24 MHz, or 12 MHz CPU operation
— Four clocks per instruction cycle
— Three counter/timers
— Expanded interrupt system
— Two data pointers
• 1.8V core operation
• 1.8V - 3.3V IO operation
• Vectored USB interrupts and GPIF/FIFO interrupts
• Separate data buffers for the Set-up and Data portions of a
CONTROL transfer
2
• Integrated I
C™ controller, runs at 100 or 400 kHz
• Four integrated FIFO's
— Integrated glue logic and FIFO's lower system cost
— Automatic conversion to and from 16-bit buses
— Master or slave operation
— Uses external clock or asynchronous strobes
— Easy interface to ASIC and DSP IC's
• Available in Industrial temperature grade
• Available in one lead-free package with up to 24 GPIO's
— 56-pin VFBGA (24 GPIO's)
MoBL-USB FX2LP18
2
I
C
Master
Additional I/Os (24)
GPIF
RDY (2)
CTL (3)
ECC
4 KB
8/16
FIFO
FIFO and Endpoint Memory
(master or slave operation)
,
•
San Jose
CA 95134-1709
CY7C68053
Abundant I/O
General
Programmable I/F
To Baseband processors/
Application processors/
ASICS/DSPs
Up to 96 MBytes/sec
Burst Rate
•
408-943-2600
Revised September 9th 2006
[+] Feedback

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the MoBL-USB CY7C68053 and is the answer not in the manual?

Questions and answers

Related Manuals for Cypress Semiconductor MoBL-USB CY7C68053

Summary of Contents for Cypress Semiconductor MoBL-USB CY7C68053

  • Page 1: Block Diagram

    MoBL-USB™ FX2LP18 USB Microcontroller CY7C68053 Features • USB 2.0 – USB-IF High-Speed and Full-Speed Compliant (TID# 40000188) • Single-chip integrated USB 2.0 transceiver, smart SIE, and enhanced 8051 microprocessor • Ideal for mobile applications (cell phone, smart phones, PDAs, MP3 players) —...

  • Page 2: Functional Overview

    Cypress Semiconductor Corporation’s MoBL-USB FX2LP18 (CY7C68053) is a low-voltage (1.8 volt) version of the EZ- ® FX2LP (CY7C68013A), which is a highly integrated, low-power USB 2.0 microcontroller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a very cost-effective solution that provides superior time-to-market advantages with low power to enable bus powered applications.
  • Page 3 Table 3-1. Special Function Registers EXIF DPL0 MPAGE DPH0 DPL1 DPH1 PCON TCON SCON0 TMOD SBUF0 AUTOPTRH1 AUTOPTRL1 Reserved AUTOPTRH2 CKCON AUTOPTRL2 Reserved C™ Bus FX2LP18 supports the I C bus as a master only at 100-/400- KHz. SCL and SDA pins have open-drain outputs and hysteresis inputs.
  • Page 4 pushes the program counter onto its stack then jumps to address 0x0043, where it expects to find a ‘jump’ instruction to the USB interrupt service routine. The FX2LP18 jump instruction is encoded as shown in Table 3-2. Table 3-2. INT2 USB Interrupts Priority INT2VEC Value SUDAV...
  • Page 5 RESET# RESET Power on Reset Reset and Wakeup The reset and wakeup pins are described in detail in this section. 3.9.1 Reset Pin The input pin, RESET#, resets the FX2LP18 when asserted. This pin has hysteresis and is active LOW. When a crystal is used with the CY7C68053, the reset period must allow for the stabilization of the crystal and the PLL.

  • Page 6: Register Addresses

    Figure 3-3. FX2LP18 Internal Code Memory FFFF 7.5 kBytes USB regs and 4K FIFO buffers E200 E1FF 0.5 kBytes RAM Data E000 3FFF 16 kBytes RAM Code and Data 0000 3.10 Program/Data RAM This section describes the FX2LP18 RAM. 3.10.1 Size The FX2LP18 has 16 kBytes of internal program/data RAM.
  • Page 7 vertical columns of Figure 3-5. When operating in full-speed BULK mode only the first 64 bytes of each buffer are used. For example, in high-speed the maximum packet size is 512 bytes, but in full-speed it is 64 bytes. Even though a buffer is configured to be a 512 byte buffer, in full-speed only the first EP0 IN&OUT EP1 IN...
  • Page 8 3.12.6 Default High-Speed Alternate Settings Table 3-5. Default High-Speed Alternate Settings Alternate Setting ep1out 512 bulk ep1in 512 bulk 512 bulk out (2×) 512 bulk out (2×) 512 bulk in (2×) 512 bulk in (2×) 3.13 External FIFO Interface The architecture, control signals, and clock rates are presented in this section.
  • Page 9 3.14.1 Three Control OUT Signals The 56-pin package brings out three of these signals, CTL0–CTL2. The 8051 programs the GPIF unit to define the CTL waveforms. CTLx waveform edges can be programmed to make transitions as fast as once per clock cycle (20.8 ns using a 48 MHz clock).

  • Page 10: Pin Assignments

    Table 3-6. Strap Boot EEPROM Address Lines to These Values Bytes Example EEPROM 24AA00 24AA01 24AA02 24AA32 24AA64 24AA128 3.18.2 C Interface Boot Load Access At power on reset the I C interface boot loader loads the VID/PID/DID and configuration bytes and up to 16 kBytes of program/data.
  • Page 11 Figure 4-2. CY7C68053 56-pin VFBGA Pin Assignment - Top view Document # 001-06120 Rev *F CY7C68053 Page 11 of 39 [+] Feedback...
  • Page 12 CY7C68053 Pin Descriptions Table 4-1. FX2LP18 Pin Descriptions 56 VFBGA Name Type Power Power AGND Ground AGND Ground DMINUS I/O/Z DPLUS I/O/Z RESET# Input XTALIN Input XTALOUT Output CLKOUT Port A PA0 or I/O/Z INT0# PA1 or I/O/Z INT1# PA2 or I/O/Z SLOE PA3 or...
  • Page 13 Table 4-1. FX2LP18 Pin Descriptions (continued) 56 VFBGA Name Type PA4 or I/O/Z FIFOADR0 PA5 or I/O/Z FIFOADR1 PA6 or I/O/Z PKTEND PA7 or I/O/Z FLAGD or SLCS# Port B PB0 or I/O/Z FD[0] PB1 or I/O/Z FD[1] PB2 or I/O/Z FD[2] PB3 or...
  • Page 14 Table 4-1. FX2LP18 Pin Descriptions (continued) 56 VFBGA Name Type PORT D PD0 or I/O/Z FD[8] PD1 or I/O/Z FD[9] PD2 or I/O/Z FD[10] PD3 or I/O/Z FD[11] PD4 or I/O/Z FD[12] PD5 or I/O/Z FD[13] PD6 or I/O/Z FD[14] PD7 or I/O/Z FD[15]...
  • Page 15 Table 4-1. FX2LP18 Pin Descriptions (continued) 56 VFBGA Name Type IFCLK I/O/Z WAKEUP Input Power CC_IO Power CC_IO Power CC_IO Power CC_IO Power CC_D Power CC_A Ground Ground Ground Ground Ground Ground Ground Document # 001-06120 Rev *F Default Interface Clock, used for synchronously clocking data into or out of the slave FIFO’s.

  • Page 16: Register Summary

    Register Summary FX2LP18 register bit definitions are described in the MoBL-USB TRM in greater detail. Table 5-1. FX2LP18 Register Summary Size Name Description GPIF Waveform Memories E400 128 WAVEDATA GPIF Waveform Descriptor 0, 1, 2, 3 data E480 128 Reserved GENERAL CONFIGURATION E50D GPCR2...
  • Page 17 Table 5-1. FX2LP18 Register Summary (continued) Size Name Description E62C ECC1B2 ECC1 Byte 2 Address E62D ECC2B0 ECC2 Byte 0 Address E62E ECC2B1 ECC2 Byte 1 Address E62F ECC2B2 ECC2 Byte 2 Address [10] E630 EP2FIFOPFH Endpoint 2/slave FIFO H.S. Programmable Flag H [10] E630...
  • Page 18 Table 5-1. FX2LP18 Register Summary (continued) Size Name Description E65E EPIE Endpoint Interrupt Enables [11] E65F EPIRQ Endpoint Interrupt Requests [10] E660 GPIFIE GPIF Interrupt Enable [10] E661 GPIFIRQ GPIF Interrupt Request E662 USBERRIE USB Error Interrupt Enables [11] E663 USBERRIRQ USB Error Interrupt Requests...
  • Page 19 Table 5-1. FX2LP18 Register Summary (continued) Size Name Description E6A1 EP1OUTCS Endpoint 1 OUT Control and Status E6A2 EP1INCS Endpoint 1 IN Control and Status E6A3 EP2CS Endpoint 2 Control and Status E6A4 EP4CS Endpoint 4 Control and Status E6A5 EP6CS Endpoint 6 Control and Status...
  • Page 20 Table 5-1. FX2LP18 Register Summary (continued) Size Name Description [10] E6CF GPIFTCB2 GPIF Transaction Count Byte 2 [10] E6D0 GPIFTCB1 GPIF Transaction Count Byte 1 [10] E6D1 GPIFTCB0 GPIF Transaction Count Byte 0 Reserved Reserved Reserved [10] E6D2 EP2GPIFFLGSEL Endpoint 2 GPIF Flag select E6D3 EP2GPIFPFSTOP...
  • Page 21 Table 5-1. FX2LP18 Register Summary (continued) Size Name Description Stack Pointer DPL0 Data Pointer 0 L DPH0 Data Pointer 0 H [12] DPL1 Data Pointer 1 L [12] DPH1 Data Pointer 1 H [12] Data Pointer 0/1 select PCON Power Control TCON Timer/Counter Control (bit addressable)
  • Page 22 Table 5-1. FX2LP18 Register Summary (continued) Size Name Description Reserved RCAP2L Capture for Timer 2, auto- reload, up-counter RCAP2H Capture for Timer 2, auto- reload, up-counter Timer 2 reload L Timer 2 reload H Reserved Program Status Word (bit addressable) Reserved [12] EICON...

  • Page 23: Absolute Maximum Ratings

    Absolute Maximum Ratings Storage Temperature ...– 65°C to +150°C Ambient Temperature with Power Supplied Industrial ...– 40°C to +85°C Supply Voltage to Ground Potential For 3.3V Power domain ... – 0.5V to +4.0V For 1.8V Power domain ... – 0.5V to +2.0V DC Input Voltage to Any Input Pin For pins under 3.3V Power Domain...
  • Page 24 DC Characteristics Table 8-1. DC Characteristics Parameter Description 3.3 V supply (to Osc. and PHY) 1.8V to 3.3V supply (to I/O) CC_IO 1.8 V supply to Analog Core CC_A 1.8 V supply to Digital Core CC_D Input HIGH Voltage Input LOW Voltage Crystal Input HIGH Voltage IH_X Crystal Input LOW Voltage...

  • Page 25: Ac Electrical Characteristics

    AC Electrical Characteristics USB Transceiver USB 2.0-compliant in full- and high-speed modes. GPIF Synchronous Signals Figure 9-1. GPIF Synchronous Signals Timing Diagram IFCLK GPIFADR[8:0] DATA(input) DATA(output) Table 9-1. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK Parameter IFCLK Period IFCLK to Clock Set-up Time Clock to RDY GPIF Data to Clock Set-up Time...
  • Page 26 Slave FIFO Synchronous Read Figure 9-2. Slave FIFO Synchronous Read Timing Diagram IFCLK SLRD FLAGS DATA SLOE Table 9-3. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK Parameter IFCLK Period IFCLK SLRD to Clock Set-up Time Clock to SLRD Hold Time SLOE Turn-on to FIFO Data Valid OEon SLOE Turn-off to FIFO Data Hold...
  • Page 27 Slave FIFO Asynchronous Read Figure 9-3. Slave FIFO Asynchronous Read Timing Diagram SLRD FLAGS DATA SLOE Table 9-5. Slave FIFO Asynchronous Read Parameters Parameter SLRD Pulse Width LOW RDpwl SLRD Pulse Width HIGH RDpwh SLRD to FLAGS Output Propagation Delay XFLG SLRD to FIFO Data Output Propagation Delay SLOE Turn-on to FIFO Data Valid...
  • Page 28 Slave FIFO Synchronous Write Figure 9-4. Slave FIFO Synchronous Write Timing Diagram IFCLK SLWR DATA FLAGS Table 9-6. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK Parameter IFCLK Period IFCLK SLWR to Clock Set-up Time Clock to SLWR Hold Time FIFO Data to Clock Set-up Time Clock to FIFO Data Hold Time Clock to FLAGS Output Propagation Time...
  • Page 29 Slave FIFO Asynchronous Write Figure 9-5. Slave FIFO Asynchronous Write Timing Diagram SLWR/SLCS# DATA FLAGS Table 9-8. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK Parameter SLWR Pulse LOW WRpwl SLWR Pulse HIGH WRpwh SLWR to FIFO DATA Set-up Time FIFO DATA to SLWR Hold Time SLWR to FLAGS Output Propagation Delay Slave FIFO Synchronous Packet End Strobe...
  • Page 30 There is no specific timing requirement that needs to be met for asserting the PKTEND pin with regards to asserting SLWR. PKTEND can be asserted with the last data value clocked into the FIFO’s or thereafter. The only consideration is that the set- up time t and the hold time t must be met.
  • Page 31 Slave FIFO Output Enable Figure 9-9. Slave FIFO Output Enable Timing Diagram SLOE DATA Table 9-12. Slave FIFO Output Enable Parameters Parameter SLOE Assert to FIFO DATA Output OEon SLOE Deassert to FIFO DATA Hold OEoff 9.10 Slave FIFO Address to Flags/Data Figure 9-10.
  • Page 32 9.11 Slave FIFO Synchronous Address Figure 9-11. Slave FIFO Synchronous Address Timing Diagram IFCLK SLCS/FIFOADR [1:0] Table 9-14. Slave FIFO Synchronous Address Parameters Parameter Interface Clock Period IFCLK FIFOADR[1:0] to Clock Set-up Time Clock to FIFOADR[1:0] Hold Time 9.12 Slave FIFO Asynchronous Address Figure 9-12.
  • Page 33 9.13 Sequence Diagram Various sequence diagrams and examples are presented in this section. 9.13.1 Single and Burst Synchronous Read Example Figure 9-13. Slave FIFO Synchronous Read Sequence and Timing Diagram IFCLK IFCLK FIFOADR SLRD SLCS FLAGS Data Driven: N DATA OEon SLOE Figure 9-14.
  • Page 34 9.13.2 Single and Burst Synchronous Write Figure 9-15. Slave FIFO Synchronous Write Sequence and Timing Diagram IFCLK IFCLK FIFOADR SLWR SLCS FLAGS DATA PKTEND Figure 9-15 shows the timing relationship of the SLAVE FIFO signals during a synchronous write using IFCLK as the synchronizing clock.
  • Page 35 9.13.3 Sequence Diagram of a Single and Burst Asynchronous Read Figure 9-16. Slave FIFO Asynchronous Read Sequence and Timing Diagram FIFOADR RDpwl RDpwh SLRD SLCS XFLG FLAGS Data (X) DATA Driven OEon OEoff SLOE Figure 9-17. Slave FIFO Asynchronous Read Sequence of Events Diagram SLOE SLRD FIFO POINTER...
  • Page 36 9.13.4 Sequence Diagram of a Single and Burst Asynchronous Write Figure 9-18. Slave FIFO Asynchronous Write Sequence and Timing Diagram FIFOADR WRpwl WRpwh SLWR t =1 SLCS XFLG FLAGS DATA PKTEND Figure 9-18 illustrates the timing relationship of the SLAVE FIFO write in an asynchronous mode.

  • Page 37: Ordering Information

    10.0 Ordering Information Table 10-1. Ordering Information Ordering Code CY7C68053-56BAXI Development Tool Kit CY3687 11.0 Package Diagram The FX2LP18 is available in a 56-pin VFBGA package. Figure 11-1. 56 VFBGA (5 x 5 x 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56 TOP VIEW PIN A1 CORNER 5.00±0.10...

  • Page 38: Pcb Layout Recommendations

    12.0 PCB Layout Recommendations The following recommendations must be followed to ensure reliable high-performance operation. • At least a four-layer impedance controlled board is required to maintain signal quality. • Specify impedance targets (ask your board vendor what they can achieve). •...
  • Page 39 Document History Page Document Title: CY7C68053 MoBL-USB FX2LP18 USB Microcontroller Document Number: 001-06120 Orig. of REV. ECN NO. Issue Date Change 430449 03/03/06 434754 03/24/06 465471 See ECN 484726 See ECN 492009 See ECN 500408 See ECN 502115 See ECN Document # 001-06120 Rev *F Description of Change New data sheet...

Table of Contents

Save PDF