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Cypress Semiconductor CYW4343W Manual

Single-chip 802.11 b/g/n mac/baseband/radio with bluetooth 4.1
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  • Page 1 Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio.
  • Page 2 CYW4343W Single-Chip 802.11 b/g/n MAC/Baseband/Radio with Bluetooth 4.1 The Cypress CYW4343W is a highly integrated single-chip solution and offers the lowest RBOM in the industry for wearables, Internet of Things (IoT) gateways, home automation, and a wide range of other portable devices. The chip includes a 2.4 GHz WLAN IEEE 802.11 b/g/n MAC/baseband/radio and Bluetooth 4.1 support.
  • Page 3 74-ball[4343W+43CS4343W1]74-ball 63-ball WLBGA ■ up (WPS). package (4.87 mm × 2.87 mm, 0.4 mm pitch). Worldwide regulatory support: Global products supported with ■ worldwide homologated design. Figure 1. CYW4343W System Block Diagram VDDIO VBAT WL_REG_ON WLAN WL_IRQ Host I/F SDIO/SPI 2.4 GHz WLAN +...

  • Page 4: Table Of Contents

    12.4 Wireless Configuration Utility ......50 2.1 Power Supply Topology ........8 13. Pinout and Signal Descriptions ......51 2.2 CYW4343W PMU Features ........ 8 13.1 Ball Map .............51 2.3 WLAN Power Management ......11 13.2 WLBGA Ball List in Ball Number Order with 2.4 PMU Sequencing ..........
  • Page 5 CYW4343W Worldwide Sales and Design Support ..... 109 Cypress Developer Community ....... 109 Products ..............109 Technical Support ........... 109 ® PSoC Solutions ............. 109 Document Number: 002-14797 Rev. *J Page 4 of 109...

  • Page 6: Overview

    The CYW4343W provides the highest level of integration for a mobile or handheld wireless system, with integrated IEEE 802.11 b/g/n. It provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and function. The CYW4343W is designed to address the needs of highly mobile devices that require minimal power consumption and reliable operation.

  • Page 7: Features

    CYW4343W 1.2 Features The CYW4343W supports the following WLAN and Bluetooth features: IEEE 802.11b/g/n single-band radio with an internal power amplifier, LNA, and T/R switch ■ Bluetooth v4.1 with integrated Class 1 PA ■ Concurrent Bluetooth, and WLAN operation ■...

  • Page 8: Standards Compliance

    ■ IEEE 802.11i MAC Enhancements ■ IEEE 802.11r Fast Roaming Support ■ IEEE 802.11k Radio Resource Measurement ■ The CYW4343W supports the following security features and proprietary protocols: Security: ■ ❐ ™ Personal ❐ ™ WPA2 Personal ❐...

  • Page 9: Power Supplies And Power Management

    2.1 Power Supply Topology One Buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW4343W. All regulators are programmable via the PMU. These blocks simplify power supply design for Bluetooth and WLAN functions in embedded designs.
  • Page 10 CYW4343W Figure 3. Typical Power Topology (1 of 2) SR _ V D D B A T 5V W L R F — T X M ixer an d P A V B A T (n o t all v ersio n s)
  • Page 11 CYW4343W Figure 4. Typical Power Topology (2 of 2) CYW4343W 6.4 mA 1.8V, 2.5V, and 3.3V WL BBPLL/DFLL WL OTP 3.3V LDO3P3 with Back-Power VOUT_3P3 WLRF_PA_VDD 480 to 800 mA VBAT Protection WL RF—PA (2.4 GHz) 1 uF LDO_ (Peak 450-800 mA 4.7 uF...

  • Page 12: Wlan Power Management

    2.3 WLAN Power Management The CYW4343W has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages.

  • Page 13: Power-Off Shutdown

    When the CYW4343W is powered on from this state, it is the same as a normal power-up, and the device does not retain any information about its state from before it was powered down.

  • Page 14: Frequency References

    As an alternative to a crystal, an external precision TCXO can be used as the frequency reference, provided that it meets the phase noise requirements listed in Table If the TCXO is dedicated to driving the CYW4343W, it should be connected to the WLRF_XTAL_XOP pin through an external capacitor with value ranges from 200 pF to 1000 pF as shown in Figure Figure 6.
  • Page 15 –147 dBc/Hz a. The frequency step size is approximately 80 Hz. The CYW4343W does not auto-detect the reference clock frequency; the frequency is specified in the software and/or NVRAM file. b. To use 256-QAM, a 800 mV minimum voltage is required.

  • Page 16: External 32.768 Khz Low-Power Oscillator

    Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock that meets the requirements listed in Table Note: The CYW4343W will auto-detect the LPO clock. If it senses a clock on the EXT_SLEEP_CLK pin, it will use that clock. If it doesn't sense a clock, it will use its own internal LPO.

  • Page 17: Wlan System Interfaces

    4.1 SDIO v2.0 The CYW4343W WLAN section supports SDIO version 2.0. for both 1-bit (25 Mbps) and 4-bit modes (100 Mbps), as well as high speed 4-bit mode (50 MHz clocks—200 Mbps). It has the ability to map the interrupt signal on a GPIO pin. This out-of-band interrupt signal notifies the host when the WLAN device wants to turn on the SDIO interface.

  • Page 18: Generic Spi Mode

    CYW4343W 4.2 Generic SPI Mode In addition to the full SDIO mode, the CYW4343W includes the option of using the simplified generic SPI (gSPI) interface/protocol. Characteristics of the gSPI mode include: Up to 50 MHz operation ■ Fixed delays for responses and data from the device ■...

  • Page 19: Spi Protocol

    CYW4343W 4.3 SPI Protocol The SPI protocol supports both 16-bit and 32-bit word operation. Byte endianess is supported in both modes. Figure 10 Figure 11 show the basic write and write/read commands. Figure 10. gSPI Write Protocol Figure 11. gSPI Read Protocol Document Number: 002-14797 Rev.
  • Page 20 CYW4343W 4.3.1 Command Structure The gSPI command structure is 32 bits. The bit positions and definitions are shown in Figure Figure 12. gSPI Command Structure SPID Command Structure 11 10 Address – 17 bits Packet length – 11 bits* * 11’h0 = 2048 bytes Function No: 00 –...
  • Page 21 CYW4343W Figure 13. gSPI Signal Timing Without Status Write SCLK MOSI Command 32 bits Command 32 bits Command 32 bits Write Data 16*n bits Write Data 16*n bits Write Data 16*n bits Write-Read SCLK MOSI MISO Response Response Response Command...

  • Page 22: Gspi Host-Device Handshake

    To initiate communication through the gSPI after power-up, the host needs to bring up the WLAN chip by writing to the wake-up WLAN register bit. Writing a 1 to this bit will start up the necessary crystals and PLLs so that the CYW4343W is ready for data trans- fer.
  • Page 23 CYW4343W or pulsed low to induce a subsequent reset. Note: The CYW4343W has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 3 ms after VDDC and VDDIO have both passed the 0.6V threshold.
  • Page 24 CYW4343W Figure 15. WLAN Boot-Up Sequence Ramp time from 0V to 4.3V > 40 µs VBAT 0.6V VDDIO > 2 Sleep Clock cycles WL_REG_ON < 1.5 ms VDDC (from internal PMU) < 3 ms Internal POR After a fixed delay following internal POR going high, <...

  • Page 25: Wireless Lan Mac And Phy

    5. Wireless LAN MAC and PHY 5.1 MAC Features The CYW4343W WLAN MAC supports features specified in the IEEE 802.11 base standard, and amended by IEEE 802.11n. The salient features are listed below: Transmission and reception of aggregated MPDUs (A-MPDU).
  • Page 26 CYW4343W The following sections provide an overview of the important modules in the MAC. The programmable state machine (PSM) is a microcoded engine that provides most of the low-level control to the hardware to implement the IEEE 802.11 specification. It is a microcontroller that is highly optimized for flow-control operations, which are predom- inant in implementations of communication protocols.

  • Page 27: Phy Description

    PSM to configure and control the PHY. 5.2 PHY Description The CYW4343W WLAN digital PHY is designed to comply with IEEE 802.11b/g/n single stream to provide wireless LAN connectivity supporting data rates from 1 Mbps to 96 Mbps for low-power, high-performance handheld applications.
  • Page 28 CYW4343W 5.2.1 PHY Features Supports the IEEE 802.11b/g/n single-stream standards. ■ Explicit IEEE 802.11n transmit beamforming. ■ Supports optional Greenfield mode in TX and RX. ■ Tx and Rx LDPC for improved range and power efficiency. ■ Supports IEEE 802.11h/d for worldwide operation.

  • Page 29: Wlan Radio Subsystem

    6. WLAN Radio Subsystem The CYW4343W includes an integrated WLAN RF transceiver that has been optimized for use in 2.4 GHz Wireless LAN systems. It is designed to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM band.

  • Page 30: Receive Path

    CYW4343W 6.1 Receive Path The CYW4343W has a wide dynamic range, direct conversion receiver. It employs high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. 6.2 Transmit Path Baseband data is modulated and upconverted to the 2.4 GHz ISM band. A linear on-chip power amplifier is included, which is capable of delivering high output powers while meeting IEEE 802.11b/g/n specifications without the need for an external PA.

  • Page 31: Bluetooth Subsystem Overview

    The CYW4343W is the optimal solution for any Bluetooth voice and/or data application. The Bluetooth subsystem presents a standard Host Controller Interface (HCI) via a high speed UART and PCM interface for audio. The CYW4343W incorporates all Bluetooth 4.1 features including secure simple pairing, sniff subrating, and encryption pause and resume.

  • Page 32: Bluetooth Radio

    7.2 Bluetooth Radio The CYW4343W has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM band.

  • Page 33: Bluetooth Baseband Core

    ■ Note: The CYW4343W is compatible with the Bluetooth Low Energy operating mode, which provides a dramatic reduction in the power consumption of the Bluetooth radio and baseband. The primary application for this mode is to provide support for low data rate devices, such as sensors and remote controls.

  • Page 34: Test Mode Support

    CYW4343W 8.3 Test Mode Support The CYW4343W fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth System Version 3.0. This includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence.
  • Page 35 CYW4343W Figure 19. Startup Signaling Sequence Host IOs unconfigured VDDIO Host IOs configured HostResetX BT_GPIO_0 (BT_DEV_WAKE) BTH IOs unconfigured BTH IOs configured BT_REG_ON BT_GPIO_1 (BT_HOST_WAKE) Host side drives BT_UART_CTS_N this line low BTH device drives this line low indicating BT_UART_RTS_N...

  • Page 36: Bbc Power Management

    When the CYW4343W is not needed in the system, the RF and core supplies are shut down while the I/O remains powered. This allows the CYW4343W to effectively be off while keeping the I/O pins powered, so they do not draw extra current from any other I/ O-connected devices.

  • Page 37: Adaptive Frequency Hopping

    8.6.2 Multiple Simultaneous A2DP Audio Streams The CYW4343W has the ability to take a single audio stream and output it to multiple Bluetooth devices simultaneously. This allows a user to share his or her music (or any audio stream) with a friend.

  • Page 38: Microprocessor And Memory Unit For Bluetooth

    9.2 Reset The CYW4343W has an integrated power-on reset circuit that resets all circuits to a known power-on state. The BT POR circuit is out of reset after BT_REG_ON goes high. If BT_REG_ON is low, then the POR circuit is held in reset.

  • Page 39: Bluetooth Peripheral Transport Unit

    The CYW4343W may be configured to generate and accept several different data formats. For conventional narrowband speech mode, the CYW4343W uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface.
  • Page 40 CYW4343W 10.1.5 PCM Interface Timing Short Frame Sync, Master Mode Figure 22. PCM Timing Diagram (Short Frame Sync, Master Mode) PCM_BCLK PCM_SYNC PCM_OUT High Impedance PCM_IN Table 9. PCM Interface Timing Specifications (Short Frame Sync, Master Mode) Ref No. Characteristics...
  • Page 41 CYW4343W Short Frame Sync, Slave Mode Figure 23. PCM Timing Diagram (Short Frame Sync, Slave Mode) PCM_BCLK PCM_SYNC PCM_OUT High Impedance PCM_IN Table 10. PCM Interface Timing Specifications (Short Frame Sync, Slave Mode) Ref No. Characteristics Minimum Typical Maximum Unit PCM bit clock frequency –...
  • Page 42 CYW4343W Long Frame Sync, Master Mode Figure 24. PCM Timing Diagram (Long Frame Sync, Master Mode) PCM_BCLK PCM_SYNC PCM_OUT High Impedance Bit 0 Bit 1 Bit 0 Bit 1 PCM_IN Table 11. PCM Interface Timing Specifications (Long Frame Sync, Master Mode) Ref No.
  • Page 43 CYW4343W Long Frame Sync, Slave Mode Figure 25. PCM Timing Diagram (Long Frame Sync, Slave Mode) PCM_BCLK PCM_SYNC PCM_OUT Bit 0 HIGH IMPEDANCE Bit 1 Bit 0 Bit 1 PCM_IN Table 12. PCM Interface Timing Specifications (Long Frame Sync, Slave Mode) Ref No.

  • Page 44: Uart Interface

    10.2 UART Interface The CYW4343W uses UART for Bluetooth HCI. The UART is a standard 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 9600 bps to 4.0 Mbps. The interface features an automatic baud rate detection capability that returns a baud rate selection.

  • Page 45: I 2 S Interface

    S WS is low, and right-channel data is transmitted when I S WS is high. Data bits sent by the CYW4343W are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on the rising edge of I2S_SSCK.
  • Page 46 CYW4343W 10.3.1 I S Timing Note: Timing values specified in Table 15 are relative to high and low threshold levels Table 15. Timing for I S Transmitters and Receivers Transmitter Receiver Lower LImit Upper Limit Lower Limit Upper Limit Notes Min.
  • Page 47 CYW4343W Figure 27. I S Transmitter Timing > 0.35T > 0.35T = 2.0V = 0.8V > 0 < 0.8T SD and WS T = Clock period = Minimum allowed clock period for transmitter T = T is only relevant for transmitters in slave mode.

  • Page 48: Cpu And Global Functions

    11.3 GPIO Interface Five general purpose I/O (GPIO) pins are available on the CYW4343W that can be used to connect to various external devices. GPIOs are tristated by default. Subsequently, they can be programmed to be either input or output pins via the GPIO control register.
  • Page 49 CYW4343W 11.4.1 2-Wire Coexistence Figure 29 shows a 2-wire LTE coexistence example. The following definitions apply to the GPIOs in the figure: GPIO_1: WLAN_SECI_TX output to an LTE IC. ■ GPIO_2: WLAN_SECI_RX input from an LTE IC. ■ Figure 29. 2-Wire Coexistence Interface to an LTE IC...

  • Page 50: Jtag Interface

    The UART is primarily for debugging during development. By adding an external RS-232 transceiver, this UART enables the CYW4343W to operate as RS-232 data termination equipment (DTE) for exchanging and managing data with other serial devices. It is compatible with the industry standard 16550 UART, and it provides a FIFO size of 64 × 8 in each direction.

  • Page 51: Wlan Software Architecture

    Pass control requests from the host to the CYW4343W device, returning the CYW4343W device responses. ■ The driver communicates with the CYW4343W over the bus using a control channel and a data channel to pass control messages and data messages. The actual message format is based on the BDC protocol.

  • Page 52: Pinout And Signal Descriptions

    CYW4343W 13. Pinout and Signal Descriptions 13.1 Ball Map Figure 33 shows the 74-ball WLBGA ball map. Figure 34 shows the 153-bump WLCSP. Figure 33. 74-Ball WLBGA Ball Map (Bottom View) BT_UART_ BT_DEV_ BT_HOST_ BT_VCO_V WLRF_2G_ WLRF_2G_ WLRF_PA_ FM_RF_IN BT_IF_VDD BT_PAVDD...
  • Page 53 CYW4343W Figure 34. 153-Bump WLCSP (Top View) Document Number: 002-14797 Rev. *J Page 52 of 109...

  • Page 54: Wlbga Ball List In Ball Number Order With X-Y Coordinates

    The table includes the X and Y coordinates for a top view with a (0,0) center. Table 16. CYW4343W WLBGA Ball List — Ordered By Ball Number Ball Number Ball Name...
  • Page 55 CYW4343W Table 16. CYW4343W WLBGA Ball List — Ordered By Ball Number (Cont.) Ball Number Ball Name X Coordinate Y Coordinate WCC_VDDIO 800.001 199.998 LDO_VBAT5V 1199.988 199.998 BT_IF_VDD –1199.988 –199.998 BTFM_PLL_VSS –799.992 –199.998 VDDC –199.998 BT_GPIO_4 399.996 –199.998 WL_REG_ON 800.001 –199.998...

  • Page 56: Wlcsp Bump List In Bump Order With X-Y Coordinates

    CYW4343W 13.3 WLCSP Bump List in Bump Order with X-Y Coordinates Table 17. CYW4343W WLCSP Bump List — Ordered By Bump Number Bump View Top View Bump (0,0 Center of Die) (0,0 Center of Die) Bump Name Number X Coordinate...
  • Page 57 CYW4343W Table 17. CYW4343W WLCSP Bump List — Ordered By Bump Number (Cont.) Bump View Top View Bump (0,0 Center of Die) (0,0 Center of Die) Bump Name Number X Coordinate Y Coordinate X Coordinate Y Coordinate FM_DAC_VOUT1 1243.031 1443.096 –1243.031...
  • Page 58 CYW4343W Table 17. CYW4343W WLCSP Bump List — Ordered By Bump Number (Cont.) Bump View Top View Bump (0,0 Center of Die) (0,0 Center of Die) Bump Name Number X Coordinate Y Coordinate X Coordinate Y Coordinate WRF_XTAL_XON 131.126 –2298.978 –131.126...
  • Page 59 CYW4343W Table 17. CYW4343W WLCSP Bump List — Ordered By Bump Number (Cont.) Bump View Top View Bump (0,0 Center of Die) (0,0 Center of Die) Bump Name Number X Coordinate Y Coordinate X Coordinate Y Coordinate PACKAGEOPTION_1 –32.274 –1692.846 32.274...
  • Page 60 CYW4343W Table 17. CYW4343W WLCSP Bump List — Ordered By Bump Number (Cont.) Bump View Top View Bump (0,0 Center of Die) (0,0 Center of Die) Bump Name Number X Coordinate Y Coordinate X Coordinate Y Coordinate PLL_VSSC –116.586 –985.716 116.586...

  • Page 61: Wlbga Ball List Ordered By Ball Name

    CYW4343W 13.4 WLBGA Ball List Ordered By Ball Name Table 18 provides the ball numbers and names in ball name order. Table 18. CYW4343W WLBGA Ball List — Ordered By Ball Name Ball Name Ball Number Ball Name Ball Number...

  • Page 62: Wlcsp Bump List Ordered By Name

    CYW4343W 13.5 WLCSP Bump List Ordered By Name Table 19 provides the bump numbers and names in bump name order. Table 19. CYW4343W WLCSP Bump List — Ordered By Bump Name Bump Name Bump Number(s) Bump Name Bump Number(s) FM_IFDVDD1P2...
  • Page 63 CYW4343W Bump Name Bump Number(s) SDIO_DATA_2 SDIO_DATA_3 SR_PVSS 123, 124 SR_VDDBAT5V 129, 130, 132 SR_VLX 126, 127, 128 SYS_VDDIO VDDC 86, 93, 95, 107, 114 VOUT_3P3 139, 144 VOUT_3P3_SENSE VOUT_CLDO 134, 136 VOUT_LNLDO 21, 25, 27, 29, 30, 32, 33, 36, 78, 85, 88, 90,...

  • Page 64: Signal Descriptions

    CYW4343W 13.6 Signal Descriptions Table 20 provides the WLBGA package signal descriptions. Table 20. WLBGA Signal Descriptions Signal Name WLBGA Ball Type Description RF Signal Interface WLRF_2G_RF 2.4 GHz BT and WLAN RF output port SDIO Bus Interface SDIO_CLK SDIO clock input...
  • Page 65 CYW4343W Table 20. WLBGA Signal Descriptions (Cont.) Signal Name WLBGA Ball Type Description Bluetooth UART and Wake UART clear-to-send. Active-low clear-to-send signal for the HCI UART BT_UART_CTS_N interface. UART request-to-send. Active-low request-to-send signal for the HCI UART BT_UART_RTS_N interface. BT_UART_RXD UART serial input.
  • Page 66 CYW4343W Table 20. WLBGA Signal Descriptions (Cont.) Signal Name WLBGA Ball Type Description Integrated Voltage Regulators SR_VDDBAT5V SR VBAT input power supply CBUCK switching regulator output. See Table 39 for details of the inductor SR_VLX and capacitor required on this output.
  • Page 67 CYW4343W Table 21. WLCSP Signal Descriptions Signal Name WLCSP Bump Type Description or Instruction RF Signal Interface Connect to an external inductor. See the reference WRF_RFIN_ELG_2G schematic for details. WRF_RFIO_2G 2.4 GHz BT and WLAN RF input/output port SDIO Bus Interface...
  • Page 68 CYW4343W Table 21. WLCSP Signal Descriptions (Cont.) Signal Name WLCSP Bump Type Description or Instruction BT_GPIO_5 BSC_SCL from wireless charging PMU BT_TM1 ARM JTAG mode Bluetooth UART and Wake UART clear-to-send. Active-low clear-to-send signal for BT_UART_CTS_N the HCI UART interface.
  • Page 69 CYW4343W Table 21. WLCSP Signal Descriptions (Cont.) Signal Name WLCSP Bump Type Description or Instruction GPIO_3 Programmable GPIO pin GPIO_4 Programmable GPIO pin GPIO_5 Programmable GPIO pin GPIO_6 Programmable GPIO pin GPIO_7 Programmable GPIO pin GPIO_8 Programmable GPIO pin GPIO_9...
  • Page 70 CYW4343W Table 21. WLCSP Signal Descriptions (Cont.) Signal Name WLCSP Bump Type Description or Instruction PLL_VDDC Core PLL power supply SYS_VDDIO VDDIO input supply. Connect to VDDIO. 86, 93, 95, 107, VDDC Core supply for WLAN and BT 3.3V output supply. See the reference schematic for...
  • Page 71 CYW4343W Table 21. WLCSP Signal Descriptions (Cont.) Signal Name WLCSP Bump Type Description or Instruction Ground BT_DVSS Bluetooth digital ground BT_LNAVSS Bluetooth LNA ground BT_PAVSS Bluetooth PA ground BT_PLLVSS Bluetooth PLL ground BT_VCOVSS Bluetooth VCO ground FM_DAC_AVSS FM DAC analog ground...

  • Page 72: Wlan Gpio Signals And Strapping Options

    CYW4343W 13.7 WLAN GPIO Signals and Strapping Options The pins listed in Table 22 are sampled at power-on reset (POR) to determine the various operating modes. Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative function specified in the signal descriptions table.

  • Page 73: I/O States

    CYW4343W 13.9 I/O States The following notations are used in Table I: Input signal ■ O: Output signal ■ I/O: Input/Output signal ■ PU = Pulled up ■ PD = Pulled down ■ NoPull = Neither pulled up nor pulled down ■...
  • Page 74 CYW4343W Table 24. I/O States (Cont.) Out-of-Reset; Out-of-Reset; Power-Down (WL_REG_ON = 1 Low Power State/Sleep (WL_REG_ON = 1; (WL_REG_ON = 0 Name I/O Keeper Active Mode WL_REG_ON = 0 BT_REG_ON = 0) Power Rail (All Power Present) BT_REG_ON = BT_REG_ON = 1)
  • Page 75 CYW4343W Table 24. I/O States (Cont.) Out-of-Reset; Out-of-Reset; Power-Down (WL_REG_ON = 1 Low Power State/Sleep (WL_REG_ON = 1; (WL_REG_ON = 0 Name I/O Keeper Active Mode WL_REG_ON = 0 BT_REG_ON = 0) Power Rail (All Power Present) BT_REG_ON = BT_REG_ON = 1)

  • Page 76: Dc Characteristics

    CYW4343W 14. DC Characteristics Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. 14.1 Absolute Maximum Ratings Caution! The absolute maximum ratings in Table 25 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration.

  • Page 77: Electrostatic Discharge Specifications

    CYW4343W 14.3 Electrostatic Discharge Specifications Extreme caution must be exercised to prevent electrostatic discharge (ESD) damage. Proper use of wrist and heel grounding straps to discharge static electricity is required when handling these devices. Always store unused material in its antistatic packaging.
  • Page 78 – – a. The CYW4343W is functional across this range of voltages. However, optimal RF performance specified in the data sheet is guaranteed only for 3.2V < VBAT < 4.8V. b. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration over the lifetime of the device are allowed.

  • Page 79: Wlan Rf Specifications

    CYW4343W 15. WLAN RF Specifications The CYW4343W includes an integrated direct conversion radio that supports the 2.4 GHz band. This section describes the RF characteristics of the 2.4 GHz radio. Note: Values in this data sheet are design goals and may change based on device characterization results.

  • Page 80: Wlan 2.4 Ghz Receiver Performance Specifications

    CYW4343W 15.2 WLAN 2.4 GHz Receiver Performance Specifications Note: Unless otherwise specified, the specifications in Table 30 are measured at the chip port (for the location of the chip port, see Figure 35). Table 30. WLAN 2.4 GHz Receiver Performance Specifications...
  • Page 81 CYW4343W Table 30. WLAN 2.4 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit 704–716 MHz – –13 – 777–787 MHz – –13 – 776–794 MHz CDMA2000 – –13.5 – 815–830 MHz – –12.5 – 816–824 MHz CDMA2000 –...
  • Page 82 CYW4343W Table 30. WLAN 2.4 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit Adjacent channel rejection-DSSS. (Difference between interfering and desired signal [25 MHz apart] at 8% 11 Mbps DSSS –70 dBm – – PER for 1024 octet PSDU with desired signal level as specified in Condition/Notes.)

  • Page 83: Wlan 2.4 Ghz Transmitter Performance Specifications

    CYW4343W 15.3 WLAN 2.4 GHz Transmitter Performance Specifications Note: Unless otherwise specified, the specifications in Table 30 are measured at the chip port (for the location of the chip port, see Figure 35). Table 31. WLAN 2.4 GHz Transmitter Performance Specifications...

  • Page 84: General Spurious Emissions Specifications

    CYW4343W Table 31. WLAN 2.4 GHz Transmitter Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit Closed loop TX power Across full temperature and voltage range. Applies variation at highest power – – ±1.5 across 5 to 21 dBm output power range.

  • Page 85: Bluetooth Rf Specifications

    CYW4343W 16. Bluetooth RF Specifications Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Unless otherwise stated, limit values apply for the conditions specified in Table 26 Table 28.
  • Page 86 CYW4343W Table 33. Bluetooth Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit Out-of-Band Blocking Performance, Modulated Interferer (LTE) GFSK (1 Mbps) 2310 MHz LTE band40 TDD 20M BW – –20 – 2330 MHz LTE band40 TDD 20M BW –...
  • Page 87 CYW4343W Table 33. Bluetooth Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit 1850–1910 MHz GSM1900 – – 1850–1910 MHz WCDMA – –17 – 1880–1920 MHz TD-SCDMA – –18 – 1920–1980 MHz WCDMA – –18 – 2010–2025 MHz TD–SCDMA –...
  • Page 88 CYW4343W Table 33. Bluetooth Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit Spurious Emissions 30 MHz–1 GHz – –95 –62 1–12.75 GHz – –70 –47 869–894 MHz – –147 – dBm/Hz 925–960 MHz – –147 – dBm/Hz 1805–1880 MHz –...
  • Page 89 CYW4343W Table 35. Bluetooth Transmitter RF Specifications Parameter Conditions Minimum Typical Maximum Unit General Frequency range 2402 – 2480 Basic rate (GFSK) TX power at Bluetooth – 12.0 – QPSK TX power at Bluetooth – – 8PSK TX power at Bluetooth –...
  • Page 90 CYW4343W Table 36. LTE Specifications for Out-of-Band Noise Floor Parameter Conditions Typical Unit 2500–2570 MHz Band 7 –130 dBm/Hz 2300–2400 MHz Band 40 –130 dBm/Hz 2570–2620 MHz Band 38 –130 dBm/Hz 2545–2575 MHz XGP Band –130 dBm/Hz Table 37. Local Oscillator Performance...

  • Page 91: Internal Regulator Electrical Specifications

    CYW4343W 17. Internal Regulator Electrical Specifications Note: Values in this data sheet are design goals and are subject to change based on device characterization results. Functional operation is not guaranteed outside of the specification limits provided in this section. 17.1 Core Buck Switching Regulator Table 39.

  • Page 92: Ldo (Ldo3P3)

    CYW4343W 17.2 3.3V LDO (LDO3P3) Table 40. LDO3P3 Specifications Specification Notes Min. Typ. Max. Units Min. = V + 0.2V = 3.5V dropout voltage requirement Input supply voltage, V must be met under maximum load for performance specifications. Output current –...

  • Page 93: Cldo

    CYW4343W 17.3 CLDO Table 41. CLDO Specifications Specification Notes Min. Typ. Max. Units Min. = 1.2 + 0.15V = 1.35V dropout voltage requirement Input supply voltage, V 1.35 must be met under maximum load. Output current – – Programmable in 10 mV steps.

  • Page 94: Lnldo

    CYW4343W 17.4 LNLDO Table 42. LNLDO Specifications Specification Notes Min. Typ. Max. Units Min. V + 0.15V = 1.35V Input supply voltage, Vin (where V = 1.2V) dropout voltage requirement must be 1.35 met under maximum load. Output current –...

  • Page 95: System Power Consumption

    Table 18.1 WLAN Current Consumption Table 43 shows typical currents consumed by the CYW4343W’s WLAN section. All values shown are with the Bluetooth core in Reset mode with Bluetooth off. 18.1.1 2.4 GHz Mode Table 43. 2.4 GHz Mode WLAN Power Consumption VBAT = 3.6V, VDDIO = 1.8V, TA 25°C...

  • Page 96: Bluetooth Current Consumption

    CYW4343W 18.2 Bluetooth Current Consumption The Bluetooth current consumption measurements are shown in Table Note: The WLAN core is in reset (WLAN_REG_ON = low) for all measurements provided in Table ■ The BT current consumption numbers are measured based on GFSK TX output power = 10 dBm.

  • Page 97: Interface Timing And Ac Characteristics

    CYW4343W 19. Interface Timing and AC Characteristics Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Unless otherwise stated, the specifications in this section apply when the operating conditions are within the limits specified in...

  • Page 98: Sdio High-Speed Mode Timing

    CYW4343W 19.2 SDIO High-Speed Mode Timing SDIO high-speed mode timing is shown by the combination of Figure 37 Table Figure 37. SDIO Bus Timing (High-Speed Mode) 50% VDD SDIO_CLK Input Output ODLY Table 46. SDIO Bus Timing Parameters (High-Speed Mode)

  • Page 99: Jtag Timing

    CYW4343W 19.3 JTAG Timing Table 47. JTAG Timing Characteristics Output Output Signal Name Period Setup Hold Maximum Minimum 125 ns – – – – – – – 20 ns 0 ns – – – 20 ns 0 ns – 100 ns 0 ns –...

  • Page 100: Power-Up Sequence And Timing

    (one for WL_REG_ON and one for BT_REG_ON), then only one of the two signals needs to be high to enable the CYW4343W regulators. The CYW4343W has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 110 ms after VDDC ■...
  • Page 101 CYW4343W 20.1.2 Control Signal Timing Diagrams Figure 38. WLAN = ON, Bluetooth = ON 32.678 kHz Sleep Clock VBAT 90% of VH VDDIO ~ 2 Sleep cycles WL_REG_ON BT_REG_ON Figure 39. WLAN = OFF, Bluetooth = OFF 32.678 kHz Sleep Clock...
  • Page 102 CYW4343W Figure 40. WLAN = ON, Bluetooth = OFF 32.678 kHz Sleep Clock VBAT 90% of VH VDDIO ~ 2 Sleep cycles WL_REG_ON BT_REG_ON Figure 41. WLAN = OFF, Bluetooth = ON 32.678 kHz Sleep Clock VBAT 90% of VH...

  • Page 103: Package Information

    CYW4343W 21. Package Information 21.1 Package Thermal Characteristics Table 48. Package Thermal Characteristics Characteristic Value in Still Air θ (°C/W) 53.11 θ (°C/W) 13.14 θ (°C/W) 6.36 Ψ (°C/W) 0.04 Ψ (°C/W) 14.21 Maximum Junction Temperature T (°C) Maximum Power Dissipation (W) a.

  • Page 104: Mechanical Information

    CYW4343W 22. Mechanical Information Figure 42 shows the mechanical drawing for the CYW4343W WLBGA package. Figure 42. 74-Ball WLBGA Mechanical Information Figure 43 shows the mechanical drawing for the CYW4343W WLCSP package. Figure 44 shows the WLCSP keep-out areas. Document Number: 002-14797 Rev. *J...
  • Page 105 CYW4343W Figure 43. 153-Bump WLCSP Mechanical Information Note: No top-layer metal is allowed in the keep-out areas Note: A DXF file containing WLBGA keep-outs can be imported into a layout program. Contact your Cypress FAE for more information. Document Number: 002-14797 Rev. *J...
  • Page 106 CYW4343W Figure 44. WLCSP Package Keep-Out Areas—Top View with the Bumps Facing Down Document Number: 002-14797 Rev. *J Page 105 of 109...
  • Page 107 CYW4343W Figure 45. WLBGA Package Keep-Out Areas—Top View with the Bumps Facing Down Document Number: 002-14797 Rev. *J Page 106 of 109...

  • Page 108: Ordering Information

    CYW4343W 23. Ordering Information Table 49. Part Ordering Information Operating Ambient Part Number Package Description Temperature 74-ball WLBGA halogen-free package 2.4 GHz single-band WLAN CYW4343WKUBG –30°C to +70°C (4.87 mm x 2.87 mm, 0.40 pitch) IEEE 802.11n + BT 4.1 2.4 GHz single-band WLAN...

  • Page 109: Document History Page

    CYW4343W Document History Page Document Title: CYW4343W Single-Chip 802.11 b/g/n MAC/Baseband/Radio with Bluetooth 4.1 Document Number: 002-14797 Submission Revision Description of Change Date 03/10/2014 4343W-DS100-R Initial release 04/18/2014 4343W-DS101-R Refer to the earlier release for detailed revision history. 06/09/2014 4343W-DS102-R...

  • Page 110: Sales, Solutions, And Legal Information

    © Cypress Semiconductor Corporation, 2014-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights.

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