Cypress Semiconductor Perform STK14D88 Manual

32kx8 autostore nvsram

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Features
25, 35, 45 ns Read Access and R/W Cycle Time
Unlimited Read/Write Endurance
Automatic Nonvolatile STORE on Power Loss
Nonvolatile STORE Under Hardware or Software Control
Automatic RECALL to SRAM on Power Up
Unlimited RECALL Cycles
200K STORE Cycles
20-Year Nonvolatile Data Retention
Single 3.0V +20%, -10% Power Supply
Commercial, Industrial Temperatures
Small Footprint SOIC and SSOP Packages (RoHS-Compliant)
Logic Block Diagram
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DQ
0
DQ
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Cypress Semiconductor Corporation
Document Number: 001-52037 Rev. **
Quantum Trap
512 x 512
STORE
STATIC RAM
RECALL
ARRAY
512 x 512
COLUMN I/O
COLUMN DEC
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0
1
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10
198 Champion Court
32Kx8 AutoStore™ nvSRAM
Description
The Cypress STK14D88 is a 256Kb fast static RAM with a
nonvolatile Quantum Trap™ storage element included with each
memory cell.
The SRAM provides fast access and cycle times, ease of use,
and unlimited read and write endurance of a normal SRAM.
Data transfers automatically to the nonvolatile storage cells
when power loss is detected (the STORE operation). On power
up, data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
The Cypress nvSRAM is the first monolithic nonvolatile memory
to offer unlimited writes and reads. It is the highest performance,
most reliable nonvolatile memory available.
V
V
CCX
CAP
POWER
CONTROL
STORE/
RECALL
CONTROL
SOFTWARE
DETECT
,
San Jose
CA 95134-1709
STK14D88
HSB
A
- A
0
13
G
E
W
408-943-2600
Revised March 02, 2009
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Summary of Contents for Cypress Semiconductor Perform STK14D88

  • Page 1 Features ■ 25, 35, 45 ns Read Access and R/W Cycle Time ■ Unlimited Read/Write Endurance ■ Automatic Nonvolatile STORE on Power Loss ■ Nonvolatile STORE Under Hardware or Software Control ■ Automatic RECALL to SRAM on Power Up ■ Unlimited RECALL Cycles ■...
  • Page 2: Pin Configurations

    Pin Configurations Figure 1. Pin Diagram 48-Pin SSOP/32-SOIC 48-Pin SSOP Pin Descriptions Pin Name Input Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array Data: Bi-directional 8-bit data bus for accessing the nvSRAM Input Chip Enable: The active low E input selects the device Input Write Enable: The active low W enables data on the DQ pins to be written to the address location latched by the falling edge of E...
  • Page 3: Absolute Maximum Ratings

    Absolute Maximum Ratings Voltage on Input Relative to Ground...–0.5V to 4.1V Voltage on Input Relative to V ...–0.6V to (V Voltage on DQ or HSB ...–0.5V to (V Temperature under Bias ... –55°C to 125°C Storage Temperature ... –65°C to 140°C Power Dissipation...
  • Page 4: Ac Test Conditions

    DC Characteristics (continued) = 2.7V-3.6V) Symbol Parameter Output Logic “0” Voltage Operating Temperature Operating Voltage Storage Capacitance DATA Data Retention Nonvolatile STORE Operations AC Test Conditions Input Pulse Levels ... 0V to 3V Input Rise and Fall Times ... <5 ns Input and Output Timing Reference Levels ...
  • Page 5 SRAM READ Cycles #1 and #2 Symbols Alt. Chip Enable Access Time ELQV Read Cycle Time AVAV ELEH Address Access Time AVQV AVQV Output Enable to Data Valid GLQV Output Hold after Address Change AXQX AXQX Address Change or Chip Enable to ELQX Output Active Address Change or Chip Disable to...
  • Page 6 SRAM WRITE Cycle #1 and #2 Symbols Alt. AVAV AVAV WLWH WLEH ELWH ELEH DVWH DVEH WHDX EHDX AVWH AVEH AVWL AVEL WHAX EHAX [6, 8] WLQZ WHQX Figure 6. SRAM WRITE Cycle 1: W Controlled ADDRESS AVWL DATA IN DATA OUT PREVIOUS DATA Figure 7.
  • Page 7 AutoStore/POWER UP RECALL Symbols Alt. 22 t Power up RECALL Duration RECALL 23 t STORE Cycle Duration STORE HLHZ 24 V Low Voltage Trigger Level SWITCH 25 V Vcc Rise Time CCRISE Note: Read and Write cycles are ignored during STORE, RECALL, and while V Notes 10.
  • Page 8 Software-Controlled STORE/RECALL Cycle Symbols Alternate E Cont 26 t STORE/RECALL Initiation Cycle Time AVAV 27 t Address Setup Time AVEL 28 t Clock Pulse Width ELEH 29 t Address Hold Time EHAX 30 t RECALL Duration RECALL Figure 9. E and G Controlled Software STORE/RECALL Cycle AVAV ADDRESS ADDRESS #1...
  • Page 9 Hardware STORE Cycle Symbols Standard Alternate DELAY HLQZ HLHX Soft Sequence Commands Symbols Standard Notes 15. Read and Write cycles in progress before HSB is asserted are given this minimum amount of time to complete. 16. This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command. 17.
  • Page 10: Mode Selection

    Mode Selection Notes 18. The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. 19. While there are 15 addresses on the STK14D88, only the lower 14 are used to control software modes 20.
  • Page 11 nvSRAM Operation nvSRAM The STK14D88 nvSRAM is made up of two functional compo- nents paired in the same physical cell. These are the SRAM memory cell and a nonvolatile QuantumTrap™ cell. The SRAM memory cell operates like a standard fast static RAM. Data in the SRAM can be transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation).
  • Page 12 To initiate the software STORE cycle, the following READ sequence must be performed: 1. Read Address 0x0E38, Valid READ 2. Read Address 0x31C7, Valid READ 3. Read Address 0x03E0, Valid READ 4. Read Address 0x3C1F, Valid READ 5. Read Address 0x303F, Valid READ 6.
  • Page 13 Figure 13. Current versus Cycle Time 100 150 200 300 Cycle Time (ns) Noise Considerations The STK14D88 is a high-speed memory and so must have a high-frequency bypass capacitor of 0.1 µF connected between both V pins and V ground plane with no plane break to chip .
  • Page 14: Part Numbering Nomenclature

    Part Numbering Nomenclature STK14D88 - R F 45 I TR Ordering Codes Part Number STK14D88-NF25 3V 32Kx8 AutoStore nvSRAM SOP32-300 STK14D88-NF35 3V 32Kx8 AutoStore nvSRAM SOP32-300 STK14D88-NF45 3V 32Kx8 AutoStore nvSRAM SOP32-300 STK14D88-NF25TR 3V 32Kx8 AutoStore nvSRAM SOP32-300 STK14D88-NF35TR 3V 32Kx8 AutoStore nvSRAM SOP32-300 STK14D88-NF45TR 3V 32Kx8 AutoStore nvSRAM SOP32-300 STK14D88-RF25...
  • Page 15: Package Diagrams

    Package Diagrams 0.810[20.574] 0.822[20.878] 0.050[1.270] TYP. 0.014[0.355] 0.020[0.508] Document Number: 001-52037 Rev. ** Figure 14. 32-Pin (300 Mil) SOIC (51-85127) PIN 1 ID DIMENSIONS IN INCHES[MM] 0.292[7.416] 0.299[7.594] REFERENCE JEDEC MO-119 0.405[10.287] 0.419[10.642] SEATING PLANE 0.090[2.286] 0.100[2.540] 0.004[0.101] 0.026[0.660] 0.032[0.812] 0.004[0.101] 0.0100[0.254] STK14D88...
  • Page 16 STK14D88 Package Diagrams (continued) Figure 15. 48-Pin (300 Mil) SSOP (51-85061) 51-85061-*C Document Number: 001-52037 Rev. ** Page 16 of 17 [+] Feedback...
  • Page 17 Document History Page Document Title: STK14D88 32Kx8 AutoStore™ nvSRAM Document Number: 001-52037 Orig. of Submission Revision Change Date 2668632 GVCH 03/04/2009 New data sheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

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