1. Manuals
  2. Brands
  3. Cypress Semiconductor Manuals
  4. Computer Hardware
  5. AutoStore STK14CA8
  6. Specification sheet

Cypress Semiconductor AutoStore STK14CA8 Specification Sheet

128kx8 nvsram
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
Features
■
25, 35, 45 ns Read Access and Read/Write Cycle Time
■
Unlimited Read/Write Endurance
■
Automatic Nonvolatile STORE on Power Loss
■
Nonvolatile STORE Under Hardware or Software Control
■
Automatic RECALL to SRAM on Power Up
■
Unlimited RECALL Cycles
■
200K STORE Cycles
■
20-Year Nonvolatile Data Retention
■
Single 3.0V + 20%, -10% Operation
■
Commercial and Industrial Temperatures
■
Small Footprint SOIC and SSOP Packages (RoHS Compliant)
Logic Block Diagram
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
A
15
A
16
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
Cypress Semiconductor Corporation
Document Number: 001-51592 Rev. **
128Kx8
Description
The Cypress STK14CA8 is a 1 Mb fast static RAM with a nonvol-
atile QuantumTrap™ storage element included with each
memory cell. This SRAM provides fast access and cycle times,
ease of use, and unlimited read and write endurance of a normal
SRAM.
Data transfers automatically to the nonvolatile storage cells
when power loss is detected (the STORE operation). On power
up, data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
The Cypress nvSRAM is the first monolithic nonvolatile memory
to offer unlimited writes and reads. It is the highest performing
and most reliable nonvolatile memory available.
Quantum Trap
1024 X 1024
STORE
STATIC RAM
RECALL
ARRAY
1024 X 1024
COLUMN I/O
COLUMN DEC
A
A
A
A
A
A
A
0
1
2
3
4
10
11
•
198 Champion Court
AutoStore™
V
V
CC
CAP
POWER
CONTROL
STORE/
RECALL
HSB
CONTROL
SOFTWARE
A
DETECT
,
•
San Jose
CA 95134-1709
STK14CA8
nvSRAM
– A
15
0
G
E
W
•
408-943-2600
Revised March 04, 2009
[+] Feedback

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the AutoStore STK14CA8 and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Cypress Semiconductor AutoStore STK14CA8

Summary of Contents for Cypress Semiconductor AutoStore STK14CA8

  • Page 1 Features ■ 25, 35, 45 ns Read Access and Read/Write Cycle Time ■ Unlimited Read/Write Endurance ■ Automatic Nonvolatile STORE on Power Loss ■ Nonvolatile STORE Under Hardware or Software Control ■ Automatic RECALL to SRAM on Power Up ■ Unlimited RECALL Cycles ■...

  • Page 2: Pin Descriptions

    Pinouts Figure 1. 48-Pin SSOP Pin Descriptions Pin Name Input Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array. Data: Bi-directional 8-bit data bus for accessing the nvSRAM. Input Chip Enable: The active low E input selects the device. Input Write Enable: The active low W allows to write the data on the DQ pins to the address location latched by the falling edge of E.

  • Page 3: Absolute Maximum Ratings

    Absolute Maximum Ratings Voltage on Input Relative to Ground...–0.5V to 4.1V Voltage on Input Relative to V ...–0.5V to (V Voltage on DQ or HSB ...–0.5V to (V Temperature under Bias ... –55°C to 125°C Junction Temperature ... –55°C to 140°C Storage Temperature ...

  • Page 4: Ac Test Conditions

    AC Test Conditions Input Pulse Levels ...0V to 3V Input Rise and Fall Times ... ≤ 5 ns Input and Output Timing Reference Levels ... 1.5V Output Load...See Figure 4 Capacitance = 25°C, f = 1.0 MHz) Symbol Parameter Max Units Input Capacitance Output Capacitance OUTPUT...
  • Page 5 SRAM READ Cycles #1 and #2 Symbols Alt. Chip Enable Access Time ELQV Read Cycle Time AVAV ELEH Address Access Time AVQV AVQV Output Enable to Data Valid GLQV Output Hold after Address Change AXQX AXQX Address Change or Chip Enable to ELQX Output Active Address Change or Chip Disable to...
  • Page 6 SRAM WRITE Cycles #1 and #2 Symbols Alt. Write Cycle Time AVAV AVAV Write Pulse Width WLWH WLEH Chip Enable to End of Write ELWH ELEH Data Setup to End of Write DVWH DVEH Data Hold after End of Write WHDX EHDX Address Setup to End of Write...
  • Page 7 AutoStore/POWER UP RECALL Symbols Standard Alternate Power up RECALL Duration HRECALL STORE Cycle Duration STORE HLHZ Low Voltage Trigger Level SWITCH CCRISE Note Read and Write cycles are ignored during STORE, RECALL, and while V Notes 9. t starts from the time V rises above V HRECALL 10.
  • Page 8 Software Controlled STORE/RECALL Cycle Symbols E Cont G Cont STORE/RECALL Initiation Cycle AVAV AVAV Time Address Setup Time AVEL AVGL Clock Pulse Width ELEH GLGH Address Hold Time EHAX GHAX RECALL Duration RECALL RECALL Figure 11. Software STORE/RECALL CYCLE: E Controlled Figure 12.
  • Page 9 Hardware STORE Cycle Symbols Standard Alternate Hardware STORE to SRAM Disabled DELAY HLQZ Hardware STORE Pulse Width HLHX Soft Sequence Commands Symbols Standard Soft Sequence Processing Time Notes 14. On a hardware STORE initiation, SRAM operation continues to be enabled for time t 15.

  • Page 10: Mode Selection

    Mode Selection 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x08B45 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x04B46 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x08FC0 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x04C63 Notes 17. The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. 18.
  • Page 11 nvSRAM Operation nvSRAM The STK14CA8 nvSRAM has two functional components paired in the same physical cell. These are the SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates similar to a standard fast static RAM. Data in the SRAM can be transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation).
  • Page 12 Software STORE Data can be transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK14CA8 software STORE cycle is initiated by executing sequential E controlled or G controlled READ cycles from six specific address locations in exact order. During the STORE cycle, previous data is erased and then the new data is programmed into the nonvol- atile elements.
  • Page 13 Low Average Active Power CMOS technology provides the STK14CA8 with the benefit of power supply current that scales with cycle time. Less current is drawn as the memory cycle time becomes longer than 50 ns. Figure 16 shows relationship READ/WRITE cycle time. Worst case current consumption is shown for commercial temperature range, V enable at maximum frequency.

  • Page 14: Ordering Information

    Ordering Information STK14CA8-R F 45 ITR Ordering Codes Part Number STK14CA8-NF25 3V 128Kx8 AutoStore nvSRAM SOP32-300 STK14CA8-NF35 3V 128Kx8 AutoStore nvSRAM SOP32-300 STK14CA8-NF45 3V 128Kx8 AutoStore nvSRAM SOP32-300 STK14CA8-NF25TR 3V 128Kx8 AutoStore nvSRAM SOP32-300 STK14CA8-NF35TR 3V 128Kx8 AutoStore nvSRAM SOP32-300 STK14CA8-NF45TR 3V 128Kx8 AutoStore nvSRAM SOP32-300 STK14CA8-RF25...

  • Page 15: Package Diagrams

    STK14CA8 Package Diagrams Figure 17. 32-Pin 300 mil SOIC (51-85127) 51-85127 *A Figure 18. 48-Pin 300 mil SSOP (51-85061) 51-85061 *C Document Number: 001-51592 Rev. ** Page 15 of 16 [+] Feedback...
  • Page 16 Document History Page Document Title: STK14CA8 128Kx8 AutoStore™ nvSRAM Document Number: 001-51592 Orig. of Revision Change 2665610 GVCH/PYRS Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Table of Contents

Save PDF