Silicon Laboratories C8051F06 Series User Manual page 8

C8051F06x-DK
6.7. Analog Inputs (AIN_0, AIN_1)
Two mini BNC connectors are provided on the C8051F060 target board, AIN_0 and AIN_1. These analog inputs
can be used to input an analog signal to the 16-bit ADCs located on the device, ADC0 and ADC1. Additionally, op-
amp circuitry is provided to filter the analog signals. To use this circuitry the following guidelines should be followed:
• Enable the –5 V voltage supply by placing a shorting block at header J20[1–2].
• Provide an external VREF0 to ADC0 by placing a shorting block at header J28.
• Provide an external VREF1 to ADC1 by placing a shorting block at header J17.
• Provide an external Conversion Start signal to ADC0 by placing a shorting block at header J27.
• Provide an external Conversion Start signal to ADC1 by placing a shorting block at header J26.
6.8. PORT I/O Connectors (J12, J15, J16 & J18)
In addition to all port I/O signals being routed to the 96-pin expansion connector, four of the eight parallel ports of
the C8051F060 has its own 10-pin header connector. Each connector provides a pin for the corresponding port
pins 0-7, +3.3 VDC and digital ground. Table 5 defines the pins for the port connectors. The same pin-out order is
used for all of the port connectors.
Table 5. J12- J19 Port Connector Pin Descriptions
6.9. VDD Monitor Disable (J23)
The VDD Monitor of the C8051F060 may be disabled by moving the shorting block on J23 from pins 1-2 to pins 2-
3, as shown in Figure 3.
6.10. VREF Connector (J22)
The VREF connector (J22) can be used to connect the VREF (Voltage Reference) output of the C8051F060 to any
(or all) of its voltage reference inputs. Install shorting blocks on J22 in the following manner:
1-2 to connect VREF to VREFD
3-4 to connect VREF to VREF2
8
Pin # Description
1
2
3
4
5
6
7
8
9 +3 VD (+3.3 VDC)
10 GND (Ground)
MONEN
Figure 3. VDD Monitor Hardware Setup
Rev. 0.7
Pn.0
Pn.1
Pn.2
Pn.3
Pn.4
Pn.5
Pn.6
Pn.7
1
2
3