NEC V40HL Datasheet
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NEC V40HL Datasheet

NEC V40HL Datasheet

Mos integrated circuit, 16/8, 16-bit microprocessor
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DESCRIPTION
The µ PD70208H (V40HL) is a high-speed, low-power 16-/8-bit microprocessor based on the µ PD70208 (V40
16-bit architecture, 8-bit data bus, and general-purpose peripheral functions.
The µ PD70216H (V50HL) is a high-speed, low-power 16-bit microprocessor based on the µ PD70216 (V50
bit architecture, 16-bit data bus, and general-purpose peripheral functions.
The V40HL and V50HL offer 20 MHz operation, and in addition to the conventional standby functions, also allows the
clock to be stopped by the use of fully static internal circuitry, thus achieving greatly reduced power consumption. It is also
capable of 3 V operation in addition to the previous 5 V operation, making it ideally suited to battery driven systems.
Details are given in the following manuals. Be sure to read when carrying out design work.
• V40HL, V50HL User's Manual – Hardware (U11610E)
• 16-bit V series
FEATURES
•
High-speed, low-power version of V40 and V50
•
High-performance CPU (V20
• Minimum instruction execution time:
• Memory addressing space: 1M bytes
• High-speed multiply/divide instructions:
• Maskable (ICU) & non-maskable (NMI) interrupt inputs
• µ PD8080AF emulation function
• Standby functions, clock stoppage capability
•
Standard peripheral LSI functions on chip
• Clock generator (CG)
• Programmable wait control unit (WCU)
• Refresh control unit (REFU)
• Timer/counter unit (TCU)
• Serial control unit (SCU)
• Interrupt control unit (ICU)
• DMA control unit (DMAU)
•
Operating frequency:
Document No. U13225EJ3V0DS00 (3rd edition)
Previous No. IC-3659
Date Published March 1998 N CP(K)
Printed in Japan
DATA SHEET
µ PD70208H, 70216H
V40HL
16/8, 16-BIT MICROPROCESSOR
TM
User's Manual – Instruction (U11301J: Japanese version)
TM
TM
/V30
software compatible)
100 ns (20 MHz, 5 V)
200 ns (10 MHz, 3 V)
0.95 to 2.8 µ s (20 MHz, 5 V)
1.9 to 5.6 µ s (10 MHz, 3 V)
··· µ PD71054 subset
··· µ PD71051 subset
··· µ PD71059 subset
··· µ PD71071/71037 subset (functions of either selectable)
10/12.5/16/20 MHz (at 5 V, with 20/25/32/40 MHz supplied externally)
5/6.25/8/10 MHz (at 3 V, with 10/12.5/16/20 MHz supplied externally)
The information in this document is subject to change without notice.
The mark
shows the the major revised points.
MOS INTEGRATED CIRCUIT
TM
TM
, V50HL
TM
) with
TM
) with 16-
©
1995

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  • Page 1 16-bit data bus, and general-purpose peripheral functions. The V40HL and V50HL offer 20 MHz operation, and in addition to the conventional standby functions, also allows the clock to be stopped by the use of fully static internal circuitry, thus achieving greatly reduced power consumption. It is also capable of 3 V operation in addition to the previous 5 V operation, making it ideally suited to battery driven systems.
  • Page 2 µ PD70208H, 70216H ORDERING INFORMATION (1) V40HL Max. Operating Part Number Package Frequency (MHz) µ PD70208HGF-10-3B9 80-pin plastic QFP (14 × 20 mm) (Resin thickness 2.7 mm) µ PD70208HGF-12-3B9 80-pin plastic QFP (14 × 20 mm) 12.5 (Resin thickness 2.7 mm) µ...
  • Page 3 µ PD70208H, 70216H PIN CONFIGURATION (Top View) (1) V40HL • 80-pin Plastic QFP (14 × 20 mm) µ PD70208HGF-10-3B9 µ PD70208HGF-12-3B9 µ PD70208HGF-16-3B9 µ PD70208HGF-20-3B9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65...
  • Page 4 µ PD70208H, 70216H • 80-pin Plastic TQFP (Fine pitch) (12 × 12 mm) µ PD70208HGK-10-9EU µ PD70208HGK-12-9EU µ PD70208HGK-16-9EU µ PD70208HGK-20-9EU 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 IOWR BUSLOCK BUFR/W...
  • Page 5 µ PD70208H, 70216H • 68-pin Plastic QFJ (950 × 950 mil) µ PD70208HLP-10 µ PD70208HLP-12 µ PD70208HLP-16 µ PD70208HLP-20 7 6 5 2 1 68 67 66 65 64 63 62 61 IOWR BUSLOCK BUFR/W BUFEN CLKOUT High ASTB POLL TCTL2 TOUT2 TCLK...
  • Page 6 µ PD70208H, 70216H (2) V50HL • 80-pin Plastic QFP (14 × 20 mm) µ PD70216HGF-10-3B9 µ PD70216HGF-12-3B9 µ PD70216HGF-16-3B9 µ PD70216HGF-20-3B9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 A16/PS0 IORD AD15 AD14 IOWR AD13...
  • Page 7 µ PD70208H, 70216H • 80-pin Plastic TQFP (Fine pitch) (12 × 12 mm) µ PD70216HGK-10-9EU µ PD70216HGK-12-9EU µ PD70216HGK-16-9EU µ PD70216HGK-20-9EU 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AD15 AD14 IOWR...
  • Page 8 µ PD70208H, 70216H • 68-pin Plastic QFJ (950 × 950 mil) µ PD70216HLP-10 µ PD70216HLP-12 µ PD70216HLP-16 µ PD70216HLP-20 7 6 5 2 1 68 67 66 65 64 63 62 61 AD15 AD14 IOWR AD13 BUSLOCK AD12 BUFR/W AD11 BUFEN AD10 CLKOUT...
  • Page 9 µ PD70208H, 70216H PIN NAMES A8-A15 : Address Bus A16/PS0-A19/PS3 : Address/Processor Status AD0-AD15 : Address Bus/Data Bus ASTB : Address Strobe BS0-BS2 : Bus Status BUFEN : Buffer Enable BUFR/W : Buffer Read/Write BUSLOCK : Bus Lock CLKOUT : Clock Output DMAAK0-DMAAK2 : DMA Acknowledge DMAAK3/T...
  • Page 10 µ PD70208H, 70216H BLOCK DIAGRAM (1) V40HL TOUT2 POLL TOUT1 BUSLOCK TCTL2 BUFEN BUFR/W TCLK High ASTB IOWR IORD INTP7 INTP6 INTP5 READY INTP4 RESOUT INTP3 RESET INTP2 INTP1 HLDAK INTAK HLDRQ REFU DMAU CPU : Central Processing Unit REFU :...
  • Page 11 µ PD70208H, 70216H (2) V50HL TOUT2 POLL TOUT1 BUSLOCK TCTL2 BUFEN BUFR/W TCLK ASTB IOWR IORD INTP7 INTP6 INTP5 READY INTP4 RESOUT INTP3 RESET INTP2 INTP1 HLDAK INTAK HLDRQ DMAU REFU...
  • Page 12 µ PD70208H, 70216H DIFFERENCES FROM V40 AND V50 Item V40HL, V50HL V40, V50 Operating supply voltage 3 V, 5 V O p e r a t i n g = 5 V MAX. : 10, 12.5, 16, 20 MHz MAX. : 8, 10 MHz frequency MIN.

  • Page 13: Table Of Contents

    µ PD70208H, 70216H CONTENTS PIN FUNCTIONS ........................... LIST OF PIN FUNCTIONS ........................... PROCESSING OF UNUSED PINS ......................MEMORY AND I/O CONFIGURATION ....................MEMORY SPACE ............................I/O SPACE ..............................CPU ................................ CG (CLOCK GENERATOR) ......................... BIU (BUS INTERFACE UNIT) ......................BAU (BUS ARBITRATION UNIT) ......................7.
  • Page 14 µ PD70208H, 70216H 16. ELECTRICAL SPECIFICATIONS ......................16.1 AT 5 V OPERATION ............................ 16.2 AT 3 V OPERATION ............................ 17. PACKAGE DRAWINGS ........................100 18. RECOMMENDED SOLDERING CONDITIONS ................... 103...

  • Page 15: Pin Functions

    Interrupt acknowledge/serial reception ready/timer 1 output Notes 1. V50HL only 2. V40HL only 3. These pins are provided with a latch. Therefore, when they go into a high-impedance state, they hold the status before the high-impedance state until driven by an external device. It is not necessary to pull up or down the data bus.
  • Page 16 µ PD70208H, 70216H Pin Name Input/Output Function DMAAK3/T Output DMA acknowledge 3/serial transmit data DMARQ3/R Input DMA request 3/serial receive data DMAAK0 to DMAAK2 Output DMA acknowledge DMARQ0 to DMARQ2 Input DMA request END/TC DMA service forcible termination/DMA service completion —...

  • Page 17: Processing Of Unused Pins

    Open INTAK/SRDY/TOUT1 Output DMAAK3/TxD Output DMARQ3/RxD Input Connect to GND via resistor DMAAK0 to DMAAK2 Output Open DMARQ0 to DMARQ2 Input Connect to GND via resistor END/TC Individually connect to V via resistor Notes 1. V50HL only 2. V40HL only...
  • Page 18 µ PD70208H, 70216H Remark The circuit configuration of the latch is as illustrated below. To invert the level of the pin with a latch, a drive current higher than the latch invert current is necessary. (1) Output pin Output buffer Latch Output pin address bus,...

  • Page 19: Memory And I/O Configuration

    µ PD70208H, 70216H 2. MEMORY AND I/O CONFIGURATION MEMORY SPACE The V40HL and V50HL can access a 1M-byte (512K-word) memory space. Figure 2-1. Memory Map FFFFFH Reserved FFFFCH FFFFBH Dedicated FFFF0H FFFEFH General Use 00400H 003FFH Interrupt Vector Table 00000H Figure 2-2.
  • Page 20 µ PD70208H, 70216H Figure 2-2. Interface with Memory (2/2) (b) V50HL A1-A19 Address Bus (19) BSEL BSEL Memory Memory Upper Bank Lower Bank 512K Byte 512K Byte D8-D15 D0-D7 D0-D15 Data Bus (16)

  • Page 21: I/O Space

    µ PD70208H, 70216H 2.2 I/O SPACE In the V40HL and V50HL, I/Os up to 64K bytes (32K words) can be accessed in an area independent of the memory. The various on-chip peripheral LSIs are set by accessing the system I/O area.

  • Page 22: Cpu

    CPU is fully compatible. The internal block diagram of the CPU is shown in Figure 3-1. Figure 3-1. Internal Block Diagram of CPU (1/2) (a) V40HL Internal Address/Data Bus (20) To BIU...
  • Page 23 µ PD70208H, 70216H Figure 3-1. Internal Block Diagram of CPU (2/2) (b) V50HL Internal Address/Data Bus (20) To BIU T-STATE CONTROL CYCLE INTERRUPT DECISION CONTROL TEMP (From ICU) QUEUE STANDBY CLOCK CONTROL CONTROL (From CG) EFFECTIVE ADDRESS GENERATOR µ INSTRUCTION Micro Data Bus µ...

  • Page 24: Cg (Clock Generator)

    The BIU synchronizes the RESET input signal and READY input signal using the CLOCK signal generated by the clock generator (CG). In addition to being supplied to the inside of the V40HL and V50HL, the synchronized reset signal is also output externally from the RESOUT pin.

  • Page 25: Bau (Bus Arbitration Unit)

    BAU bus arbitration is performed as follows. A bus master such as the CPU, DMAU, REFU, etc., incorporated in the V40HL and V50HL normally release the bus at the end of the bus cycle currently being executed, as shown in Figure 6-1. However, in the case of a bus master connected to the HLDRQ pin, or cascaded external DMA controllers, for instance, the situation is as shown in Figure 6-2.
  • Page 26 Bus Cycle Bus Release Refresh HLDRQ Pin HLDAK Pin Internal Refresh Request (Highest Priority) Note The period in which the external bus master which has been given the bus after its release by the V40HL and V50HL can use the bus.

  • Page 27: Wcu (Wait Control Unit)

    µ PD70208H, 70216H 7. WCU (WAIT CONTROL UNIT) The WCU has the function of automatically inserting a wait state (TW) of 0 to 3 clock cycles in a CPU, DMAU or REFU bus cycle. FEATURES • Automatic setting of 0 to 3 waits for a CPU memory bus cycle •...

  • Page 28: Relation Between Wcu And Ready Pin

    When wait cycles exceeding 3 clock cycles are necessary, the WCU and the READY signal pin can be used in combination. The number of wait cycles specified by the WCU set value or the number of wait cycles under READY control, whichever is larger, is inserted. Figure 7-3. WCU and READY Control V40HL/V50HL Bus Control READY...

  • Page 29: Refu (Refresh Control Unit)

    (See 6. BAU.) The refresh address is output on A0 to A15. Every refresh cycle the refresh address is incremented by 1 (for the V40HL) or by 2 (for the V50HL), and the next refresh address is generated.

  • Page 30: Tcu (Timer/Counter Unit)

    µ PD70208H, 70216H 9. TCU (TIMER/COUNTER UNIT) The TCU incorporates 3 counters, and can be used as a timer, event counter, rate generator, etc. Functionally it is a subset of the µ PD71054. FEATURES 3 × 16-bit counters • • Six programmable count modes •...

  • Page 31: Scu (Serial Control Unit)

    µ PD70208H, 70216H 10. SCU (SERIAL CONTROL UNIT) The SCU performs control of serial communication (asynchronous). Its functions are a subset of the µ PD71051 excluding synchronous communication. Also, what was the control word register in the µ PD71051 has been divided into two: a command register and a mode register.

  • Page 32: Icu (Interrupt Control Unit)

    The ICU arbitrates among up to 8 interrupt requests (maskable interrupts) generated inside and outside the V40HL and V50HL, and transfers one of them to the CPU. The ICU functions comprise the functions of the V40HL and V50HL minus those functions not required by the V40HL and V50HL.

  • Page 33: Dmau (Dma Control Unit)

    µ PD70208H, 70216H 12. DMAU (DMA CONTROL UNIT) The DMAU has 4 DMA channels, and provides the functions (subset) of two LSIs, the µ PD71071 and µ PD71037. 12.1 FEATURES Two operating modes ( µ PD71071 mode, µ PD71037 mode) •...

  • Page 34: Standby Functions

    When the RESET pin subsequently returns to the high level, the CPU begins an instruction prefetch from address FFFF0H. When the V40HL and V50HL are reset, its status is fully compatible with the V40 and V50. Extended functions added to those of the V40 and V50 are mapped onto unused V40 and V50 registers and the reserved area.

  • Page 35: Instruction Set

    µ PD70208H, 70216H 15. INSTRUCTION SET Table 15-1. Operand Type Legend Identifier Description 8/16-bit general register (destination register in an instruction using two 8/16-bit general registers) reg’ Source register in an instruction using two 8/16-bit general registers reg8 8-bit general register (destination register in an instruction using two 8-bit general registers) reg8’...
  • Page 36 µ PD70208H, 70216H Table 15-2. Operation Code Legend Identifier Description Byte/word specification bit (0: byte, 1: word). However, when s =1, byte data of sign extension is 16-bit operand if W = 1. Register field (000 to 111) reg’ Register field (000 to 111) (source register in instruction which uses two registers) Memory field (000 to 111) Mode field (00 to 10) Sign-extended specification bit (0: without sign extension, 1: with sign extension)
  • Page 37 µ PD70208H, 70216H Table 15-3. Operand Description Legend Identifier Description Accumulator (16-bit) Accumulator (higher byte) Accumulator (lower byte) Register BW (16-bit) Register CW (16-bit) Register CL (lower byte) Register DW (16-bit) Base pointer (16-bit) Stack pointer (16-bit) Program counter (16-bit) Program status word (16-bit) Index register (source) (16-bit) Index register (destination) (16-bit)
  • Page 38 µ PD70208H, 70216H Table 15-4. Flag Operation Legend Identifier Description (Blank) No change Cleared to 0 Set to 1 × Set or cleared depending upon result Undefined Previously saved value is restored Table 15-5. Memory Addressing BW + IX BW + IX + disp 8 BW + IX + disp 16 BW + IY BW + IY + disp 8...
  • Page 39 On the right of "/": The value corresponding to word processing (W =1) of odd address For the clock of block transfer related instruction of V40HL, see Table 15-8. Table 15-8. Number of Clock Cycles in Block Transfer Related Instruction (V40HL)
  • Page 40 µ PD70208H, 70216H (2) V50HL On the left of "/" The value corresponding to byte processing (W= 0) or word processing (W = 1) of even address On the right of "/" : The value corresponding to word processing (W =1) of odd address For the clock of block transfer related instruction of V50HL, see Table 15-9.
  • Page 41 Operand(s) Bytes Operation Group 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 V40HL V50HL AC CY V reg ← reg’ reg, reg’ 1 0 0 0 1 0 1 W reg reg’...
  • Page 42 Operation Group 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 V40HL V50HL AC CY V While CW ≠ 0, the following byte primitive block transfer REPC 0 1 1 0 0 1 0 1 instruction is executed and CW is decremented (–1).
  • Page 43 Bytes Operation Group 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 V40HL V50HL AC CY V 16-bit field ← AW reg8, reg8’ 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1...
  • Page 44 Clock Cycles tion Mnemonic Operand(s) Bytes Operation Group 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 V40HL V50HL AC CY V reg ← reg + reg’ × × × × × ×...
  • Page 45 Bytes Operation Group 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 V40HL V50HL AC CY V 19 × n 19 × n dst BCD string ← dst BCD string + src BCD string* ×...
  • Page 46 Mnemonic Operand(s) Bytes Operation Group 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 V40HL V50HL AC CY V AW ← AL × reg8 × × MULU reg8 1 1 1 1 0 1 1 0...
  • Page 47 Operation Group 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 AC CY V V40HL V50HL temp ← AW DIVU reg8 1 1 1 1 0 1 1 0 1 1 1 1 0 reg U U U U U U If temp ÷...
  • Page 48 Bytes Operation Group 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 V40HL V50HL AC CY V temp ← AW reg8 1 1 1 1 0 1 1 0 1 1 1 1 1 reg...
  • Page 49 Operand(s) Bytes Operation Group 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 V40HL V50HL AC CY V 0FH > 9 or AC = 1: AL ← AL + 6 × × ADJBA...
  • Page 50 Mnemonic Operand(s) Bytes Operation Group 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 V40HL V50HL AC CY V × × × TEST reg, reg’ 1 0 0 0 0 1 0 W reg’...
  • Page 51 Operand(s) Bytes Operation Group 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 V40HL V50HL AC CY V reg8 bit NO.CL = 0 : Z ← 1 × TEST1 reg8, CL 0 0 0 1 0 0 0 0 1 1 0 0 0 reg reg8 bit NO.CL = 1 : Z ←...
  • Page 52 Bytes Operation Group 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 V40HL V50HL AC CY V reg8 bit NO.CL ← 0 CLR1 reg8, CL 0 0 0 1 0 0 1 0 1 1 0 0 0 reg (mem8) bit NO.CL ←...
  • Page 53 Operand(s) Bytes Operation tion Group 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 V40HL V50HL AC CY V CY ← reg MSB, reg ← reg × 2 × × × × ×...
  • Page 54 Operand(s) Operation tion Bytes Group 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 V40HL V50HL AC CY V CY ← reg LSB, reg ← reg ÷ 2 × × × × ×...
  • Page 55 Operand(s) Bytes Operation Group 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 V40HL V50HL AC CY V CY ← reg LSB, reg ← reg ÷ 2, V ← 0 × × ×...
  • Page 56 Operand(s) Bytes Operation Group 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 V40HL V50HL AC CY V CY ← reg MSB, reg ← reg × 2 + CY × × reg, 1...
  • Page 57 Mnemonic Operand(s) Bytes Operation Group 7 6 5 4 3 2 1 0 V40HL V50HL AC CY V 7 6 5 4 3 2 1 0 CY ← reg LSB, reg← reg ÷ 2 × × reg, 1 1 1 0 1 0 0 0 W 1 1 0 0 1 reg reg MSB ←...
  • Page 58 Mnemonic Operand(s) Bytes Operation Group 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 V40HL V50HL AC CY V × × tmpcy ← CY, CY ← reg MSB ROLC reg, 1 1 1 0 1 0 0 0 W 1 1 0 1 0 reg reg ←...
  • Page 59 Bytes Operation Group 7 6 5 4 3 2 1 0 AC CY V 7 6 5 4 3 2 1 0 V40HL V50HL tmpcy ← CY, CY ← reg LSB × × RORC reg, 1 1 1 0 1 0 0 0 W 1 1 0 1 1 reg reg ←...
  • Page 60 Bytes Group 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 V40HL V50HL AC CY V SP ← SP – 2, (SP + 1, SP) ← PC CALL near-proc 1 1 1 0 1 0 0 0 16/20 PC ←...
  • Page 61 Bytes Operation Group 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 AC CY V V40HL V50HL SP ← SP – 2 PUSH 15/23 mem16 1 1 1 1 1 1 1 1 mod 1 1 0 mem (SP + 1, SP) ←...
  • Page 62 Operation Group 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 AC CY V V40HL V50HL PC ← PC+ dsip near-label 1 1 1 0 1 0 0 1 PC ← PC+ ext-disp8...
  • Page 63 Bytes Operation Group 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 AC CY V V40HL V50HL PC ← PC + ext-disp8 short-label 0 1 1 1 0 0 0 0 14/4 14/4 if V = 1 PC ←...
  • Page 64 Group 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 AC CY V V40HL V50HL TA ← (00DH, 00CH), TC ← (00FH, 00EH) 1 1 0 0 1 1 0 0 38/50 SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0 SP ←...
  • Page 65 Bytes Operation Group 7 6 5 4 3 2 1 0 AC CY V 7 6 5 4 3 2 1 0 V40HL V50HL HALT 1 1 1 1 0 1 0 0 CPU Halt POLL 2 + 5n 1 0 0 1 1 0 1 1...

  • Page 66: Electrical Specifications

    Therefore, these characteristics are different from those conforming to the K mask. For the electrical characteristics of the K mask, consult NEC. “Others” in the table below means products conforming to the masks other than E, P, X, and M (but conforming to the L, F mask).
  • Page 67 µ PD70208H, 70216H DC CHARACTERISTICS ° ± ± 10% ( µ PD70208H, 70216H-10/12/16), V 5% ( µ PD70208H, 70216H-20)) = –40 to +85 C, V = 5 V = 5 V Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Input voltage high E, P, X, M Except RESET +0.3...
  • Page 68 µ PD70208H, 70216H AC CHARACTERISTICS ° ± (1) µ PD70208H, 70216H-10/12/16 (T = –40 to +85 C, V = 5 V 10%) (1/3) Output Pin Load Capacitance: C = 100 pF µ PD70208H-10 µ PD70208H-12 µ PD70208H-16 µ PD70216H-10 µ PD70216H-12 µ...
  • Page 69 µ PD70208H, 70216H ° ± (1) µ PD70208H, 70216H-10/12/16 (T = –40 to +85 C, V = 5 V 10%) (2/3) Output Pin Load Capacitance: C = 100 pF µ PD70208H-10 µ PD70208H-12 µ PD70208H-16 µ PD70216H-10 µ PD70216H-12 µ PD70216H-16 Parameter Symbol Unit...
  • Page 70 µ PD70208H, 70216H ° ± (1) µ PD70208H, 70216H-10/12/16 (T = –40 to +85 C, V = 5 V 10%) (3/3) Output Pin Load Capacitance: C = 100 pF µ PD70208H-10 µ PD70208H-12 µ PD70208H-16 Parameter Symbol µ PD70216H-10 µ PD70216H-12 µ...
  • Page 71 µ PD70208H, 70216H ° ± (2) µ PD70208H, 70216H-20 (T = –40 to +85 C, V = 5 V 5%) (1/3) Output Pin Load Capacitance: C = 100 pF µ PD70208H-20 µ PD70216H-20 Parameter Symbol Unit MIN. MAX. External clock input cycle <1>...
  • Page 72 µ PD70208H, 70216H ° ± (2) µ PD70208H, 70216H-20 (T = –40 to +85 C, V = 5 V 5%) (2/3) Output Pin Load Capacitance: C = 100 pF µ PD70208H-20 µ PD70216H-20 Parameter Symbol Unit MIN. MAX. ASTB ↓ → address hold time <36>...
  • Page 73 µ PD70208H, 70216H ° ± (2) µ PD70208H, 70216H-20 (T = –40 to +85 C, V = 5 V 5%) (3/3) Output Pin Load Capacitance: C = 100 pF µ PD70208H-20 µ PD70216H-20 Parameter Symbol Unit MIN. MAX. TOUT1 ↓ → TxD delay time <71>...
  • Page 74 Cautions 1. The oscillation circuit should be as close as possible to the X1 and X2 pins. 2. No other signal lines should pass through the area enclosed in dashed line. 3. For matching between V40HL, V50HL and resonator, the efficient evaluation should be carried out.

  • Page 75: At 3 V Operation

    µ PD70208H, 70216H 16.2 AT 3 V OPERATION OPERATING RANGE E, P, X, M Masks Others µ PD70208H, 70216H-10/12/16 = 3 V ±10% µ PD70208H, 70216H-20 = 3 V ±10% — ° ABSOLUTE MAXIMUM RATINGS (T = 25 Parameter Symbol Test Conditions Rating Unit...
  • Page 76 µ PD70208H, 70216H ° ± DC CHARACTERISTICS (T = –40 to +85 C, V = 3 V 10%) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Input voltage high Except RESET 0.7 V +0.3 RESET 0.8 V +0.3 Input voltage low Except RESET –0.5 0.2 V...
  • Page 77 µ PD70208H, 70216H AC CHARACTERISTICS ° (1) µ PD70208H, 70216H-10/12/16 (T = 3 V ±10%) (1/3) = –40 to +85 C, V Output Pin Load Capacitance: C = 100 pF µ PD70208H-10 µ PD70208H-12 µ PD70208H-16 µ PD70216H-10 µ PD70216H-12 µ...
  • Page 78 µ PD70208H, 70216H ° (1) µ PD70208H, 70216H-10/12/16 (T = 3 V ±10%) (2/3) = –40 to +85 C, V Output Pin Load Capacitance: C = 100 pF µ PD70208H-10 µ PD70208H-12 µ PD70208H-16 µ PD70216H-10 µ PD70216H-12 µ PD70216H-16 Parameter Symbol Unit...
  • Page 79 µ PD70208H, 70216H ° (1) µ PD70208H, 70216H-10/12/16 (T = 3 V ±10%) (3/3) = –40 to +85 C, V Output Pin Load Capacitance: C = 100 pF µ PD70208H-10 µ PD70208H-12 µ PD70208H-16 µ PD70216H-10 µ PD70216H-12 µ PD70216H-16 Parameter Symbol Unit...
  • Page 80 µ PD70208H, 70216H ° ± (2) µ PD70208H, 70216H-20 (T = –40 to +85 C, V = 3 V 10%) (1/3) Output Pin Load Capacitance: C = 100 pF µ PD70208H-20 µ PD70216H-20 Parameter Symbol Unit MIN. MAX. External clock input cycle <1>...
  • Page 81 µ PD70208H, 70216H ° ± (2) µ PD70208H, 70216H-20 (T = –40 to +85 C, V = 3 V 10%) (2/3) Output Pin Load Capacitance: C = 100 pF µ PD70208H-20 µ PD70216H-20 Parameter Symbol Unit MIN. MAX. ASTB ↓ → address hold time –20 <36>...
  • Page 82 µ PD70208H, 70216H ° ± (2) µ PD70208H, 70216H-20 (T = –40 to +85 C, V = 3 V 10%) (3/3) Output Pin Load Capacitance: C = 100 pF µ PD70208H-20 µ PD70216H-20 Parameter Symbol Unit MIN. MAX. TOUT1 ↓ → TxD delay time <71>...
  • Page 83 2. No other signal lines should pass through the area enclosed in dashed line. 3. V40HL, V50HL and resonator matching requires careful evaluation. 4. The values of the oscillation circuit constants C1 and C2 depend on the characteristics of the resonator used.
  • Page 84 µ PD70208H, 70216H AC Test Input Waveform (Except X1 and X2) (at 5 V operation) 2.4 V 2.2 V 2.2 V Test points 0.8 V 0.8 V 0.4 V AC Test Output Test Points (at 5 V operation) 2.2 V 2.2 V Test points...
  • Page 85 µ PD70208H, 70216H Clock Timing <1> <4> <5> <2> External Clock (Input) (X1) <11> <11> <3> <6> <9> <10> <7> CLKOUT (Output) <8> Reset Timing CLKOUT (Output) <16> <17> <16> <88> RESET (Input) Note <18> <18> RESOUT (Output) Ready Timing (1) CLKOUT (Output) <22>...
  • Page 86 µ PD70208H, 70216H Read Timing CLKOUT (Output) <27> <28> <30> A16/PS0- A19/PS3 A16-A19 PS0-PS3 (Output) <27> <29> <31> A8-A15 (Output): V40HL UBE (Output): V50HL <27> <25> <31> <28> <32> AD0-AD7 (I/O): V40HL A0-A7(Output) : V40HL D0-D7(Intput) : V40HL AD0-AD15 (I/O): V50HL A0-A15(Output)
  • Page 87 CLKOUT (Output) <27> <28> <30> A16/PS0- A19/PS3 A16-A19 PS0-PS3 (Output) <27> <29> <31> A8-A15 (Output): V40HL UBE (Output): V50HL <27> <45> <46> AD0-AD7 (I/O): V40HL A0-A7 (Output) : V40HL D0-D7 (Output) : V40HL AD0-AD15 (I/O): V50HL A0-A15 (Output) : V50HL...
  • Page 88 Status Timing CLKOUT (Output) <28> <30> <27> <29> A16/PS0- A19/PS3 A16-A19 PS0-PS3 (Output) <27> <31> A8-A15 (Output): V40HL UBE (Output): V50HL <25> <27> <28> <26> <31> <32> AD0-AD7 (I/O): V40HL A0-A7 (Output) : V40HL D0-D7 (Input) : V40HL AD0-AD15 (I/O): V50HL...
  • Page 89 µ PD70208H, 70216H Interrupt Acknowledge Timing (V40HL) CLKOUT (Output) A8-A15 (Output) Note 1 <26> <25> <27> <32> <32> Note 1 Note 2 AD0-AD7 (I/O) Vector Number ASTB (Output) <38> INTAK (Output) <38> <38> Note 3 Note 3 BUFEN (Output) BUFR/W (Output) <27>...
  • Page 90 µ PD70208H, 70216H Interrupt Acknowledge Timing (V50HL) TI×3 CLKOUT (Output) <32> <27> <32> <25> <26> Note 1 Note 2 AD0-AD15 (I/O) Vector Number ASTB (Output) <38> INTAK (Output) <38> <38> BUFEN (Output) Note 3 Note 3 BUFR/W (Output) <27> BUSLOCK (Output) Notes 1.
  • Page 91 <27> <32> BS0-BS2 (Output) Note A16/PS0 to A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR (all output): V40HL, V50HL A8-A15 (output): V40HL AD0-AD7 (input/output): V40HL AD0-AD15 (input/output) V50HL Remark A dashed line indicates high impedance. HLDRQ/HLDAK Timing (2) CLKOUT (Output) <51>...
  • Page 92 µ PD70208H, 70216H POLL, NMI Input Timing CLKOUT (Output) <24> POLL (Input) <23> NMI (Input) BUSLOCK Output Timing CLKOUT (Output) <27> <27> BUSLOCK (Output) Access Interval <86> MRD (Output) IORD (Output) <86> <86> MWR (Output) IOWR (Output) <86>...
  • Page 93 µ PD70208H, 70216H Refresh Timing (V40HL) CLKOUT (Output) <28> <27> <29> A16/PS0- A19/PS3 Invalid (Output) <27> Refresh Address A8-A15 (Output) <27> <28> <31> <32> AD0-AD7 (I/O) Refresh Address <33> <36> <35> ASTB (Output) <34> BUFEN (Output) <41> <39> <40> MRD (Output) <43>...
  • Page 94 µ PD70208H, 70216H Refresh Timing (V50HL) CLKOUT (Output) <28> <27> <29> A16/PS0- Invalid A19/PS3 (Output) <27> UBE (Output) <28> <27> <31> <32> AD0-AD15 (I/O) Refresh Address <33> <36> <35> ASTB (Output) <34> BUFEN (Output) <39> <41> <40> MRD (Output) <43> <38>...
  • Page 95 µ PD70208H, 70216H TCU Timing (1) CLKOUT (Output) <72> <72> <74> <77> <76> <74> TCTL2 (Input) Note <80> <78> TOUTn (Output) (n=1, 2) Note Applies to TOUT2 output. TCU Timing (2) <82> <81> <83> <85> TCLK (Input) <84> <75> <73> <76>...
  • Page 96 µ PD70208H, 70216H SCU Timing RxD (Input) <68> <69> TOUT1 (Output) 16 Cycles or 64 Cycles 16 Cycles or 64 Cycles TxD (Output) <71> CLKOUT (Output) <70> SRDY (Output)
  • Page 97 BS0-BS2 (Output) Bus Status <33> <36> <35> ASTB (Output) <34> <29> <27> <28> A16/PS0- A19/PS3 (Output) <27> A8-A15 (Output): V40HL UBE (Output): V50HL <27> <28> <32> AD0-AD7 (I/O): V40HL AD0-AD15 (I/O): V50HL <53> <53> DMAAK (Output) <39> <58> <41> <40>...
  • Page 98 µ PD70208H, 70216H DMAU Timing (2) CLKOUT (Output) <61> <60> <63> TC (Input/Output) <64> <62> <65> END (Input/Output) CLKOUT (Output) <66> DMARQn (Input) (n=0-3)
  • Page 99 µ PD70208H, 70216H DMAU Timing (3) (Cascade Mode) In Normal Operation: CLKOUT (Output) <66> <66> DMARQ (Input) <54> <54> DMAAK (Output) When Refresh Cycle is Inserted: CLKOUT (Output) DMARQ (Input) <54> <54> DMAAK (Output) ICU Timing <67> INTPn (Input) (n=1-7)

  • Page 100: Package Drawings

    µ PD70208H, 70216H 17. PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14x20) detail of lead end NOTE 1. Controlling dimension millimeter. ITEM MILLIMETERS INCHES 23.6±0.4 0.929±0.016 2. Each lead centerline is located within 0.15 mm (0.006 inch) of 0.795 +0.009 20.0±0.2 its true position (T.P.) at maximum material condition.
  • Page 101 µ PD70208H, 70216H 80 PIN PLASTIC TQFP (FINE PITCH) ( 12) detail of lead end NOTE ITEM MILLIMETERS INCHES Each lead centerline is located within 0.10 mm (0.004 inch) of 14.0±0.2 0.551±0.008 its true position (T.P.) at maximum material condition. +0.009 12.0±0.2 0.472...
  • Page 102 µ PD70208H, 70216H 68 PIN PLASTIC QFJ ( 950 mil) P68L-50A1-2 NOTE ITEM MILLIMETERS INCHES Each lead centerline is located within 0.12 25.2 ± 0.2 0.992 ± 0.008 mm (0.005 inch) of its true position (T.P.) at maximum material condition. 24.20 0.953 24.20...

  • Page 103: Recommended Soldering Conditions

    µ PD70208H, 70216H 18. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the conditions recommended in the table below. For the details of recommended soldering conditions for the surface mounting type, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact our salesman.
  • Page 104 µ PD70208H, 70216H (c) L, F masks Recommended Soldering Method Soldering Conditions Conditions Symbol Package peak temperature: 235 °C, Time: 30 sec. max. (210 ˚C min.), Infrared reflow IR35-00-3 Number of times: 3 max. < Precautions > Products other than in heat-resistance trays (such as those packaged in a magazine, taping, or non-heat-resistance tray) cannot be baked while they are in their package.
  • Page 105 µ PD70208H, 70216H (2) µ PD70208HGK-×-9EU : 80-pin plastic TQFP (fine pitch) (12 × 12 mm) µ PD70216HGK-×-9EU : 80-pin plastic TQFP (fine pitch) (12 × 12 mm) (a) K, E, X masks Recommended Soldering Method Soldering Conditions Conditions Symbol Package peak temperature : 230 °C, Time: 30 sec.
  • Page 106 µ PD70208H, 70216H (3) µ PD70208HLP-× : 68-pin plastic QFJ (950 × 950 mil) µ PD70216HLP-× : 68-pin plastic QFJ (950 × 950 mil) (a) K, E, X masks Recommended Soldering Method Soldering Conditions Conditions Symbol Package peak temperature : 230 °C, Time: 30 sec. max. (210 °C min.), Infrared reflow IR30-367-1 Note...
  • Page 107 µ PD70208H, 70216H [MEMO]...
  • Page 108 µ PD70208H, 70216H NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
  • Page 109 Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
  • Page 110 The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.

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