Download Print this page

NEC VR4100 Series User Manual

Companion chip

Table Of Contents

page of 413

/ 413
Contents
Table of Contents
Bookmarks

Table of Contents

Advertisement

Quick Links

Download this manual

User's Manual

V

4173™

RC

V

4100 Series™ Companion Chip

R

µ µ µ µ PD31173

Document No. U14579EJ2V0UM00 (2nd edition)

Date Published February 2002 N CP(K)

Printed in Japan

Table of Contents

Advertisement

Table of Contents

Need help?

Need help?

Do you have a question about the VR4100 Series and is the answer not in the manual?

Questions and answers

Summary of Contents for NEC VR4100 Series

Page 1 User’s Manual 4173™ 4100 Series™ Companion Chip µ µ µ µ PD31173 Document No. U14579EJ2V0UM00 (2nd edition) Date Published February 2002 N CP(K) Printed in Japan...
Page 2 [MEMO] User’s Manual U14579EJ2V0UM...
Page 3 4100 Series, V 4121, V 4122, and V 4173 are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation.
Page 4 NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others.
Page 5 Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 Major Revisions in This Edition (1/2) Page Description Throughout Deletion of descriptions related to 32-bit PC card (CardBus card) p.25 Modification of description in 1.1 Features p.27 Modification of description in 1.3 (14) CARDU1, CARDU2 (PC Card Units) p.50 Modification of pin I/O direction in Table 2-1 PCI Bus Interface Signals p.51 Modification of pin I/O direction in Table 2-4 PC Card Interface Signals p.56...
Page 7 Major Revisions in This Edition (2/2) Page Description p.255 Addition of Caution to 13.3.67 MEM1_CMD_TIM (PCI offset address: 0x889, ExCA extended offset address: 0x0E) p.258 Modification of Table 13-4 CardBus Socket Registers p.259 Modification of description in 13.4.1 SKT_EV (offset address: 0x000) pp.262, 263 Addition of Note to 13.4.3 SKT_PRE_STATE (offset address: 0x008) p.272...
Page 8 INTRODUCTION Target Readers This manual is intended for users who understand the functions of the V 4173 and develop application systems using them. Purpose This manual is designed to help users understand the architecture of the V 4173, as described below. Organization This manual covers the following general topics.
Page 9 Related Documents See the following documents when using this manual. The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. O Documents related to device Document Name Document Number 4173 User’s Manual This manual µ...
Page 10: Table Of Contents
CONTENTS CHAPTER 1 OVERVIEW ..........................25 Features .............................25 Ordering Information........................26 Internal Block Configuration ....................26 PCI Device Configuration......................28 Lists of Registers........................29 CHAPTER 2 PIN FUNCTIONS ........................44 Pin Configuration........................44 Pin Function Lists........................50 2.2.1 PCI bus interface signals......................50 2.2.2 USB interface signals .......................50 2.2.3 AC-Link interface signals......................50 2.2.4 PC card interface signals ......................51...
Page 11 3.2.12 SUBVID (offset address: 0x2C to 0x2D) .................. 71 3.2.13 SUBID (offset address: 0x2E to 0x2F) ..................71 3.2.14 INTL (offset address: 0x3C) ..................... 72 3.2.15 INTP (offset address: 0x3D)..................... 72 3.2.16 MIN_GNT (offset address: 0x3E) ..................... 72 3.2.17 MAX_LAT (offset address: 0x3F) ..................... 73 3.2.18 BUSCNT (offset address: 0x40)....................
Page 12 7.2.7 MSYSINT1REG (base address + 0x06C) ................100 7.2.8 MPIUINTREG (base address + 0x06E)..................102 7.2.9 MAIUINTREG (base address + 0x070) ..................103 7.2.10 MKIUINTREG (base address + 0x072) ..................104 7.2.11 MGIULINTREG (base address + 0x074)................105 7.2.12 MGIUHINTREG (base address + 0x076) ................105 Notes for Register Setting .....................106 CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) ................107 General.............................107...
Page 13 Relationships Among TPX, TPY, ADX, ADY, TPEN, ADIN, and AUDIOIN Pins and States ....................148 Timing............................149 9.6.1 Touch/release detection timing ....................149 9.6.2 A/D port scan timing....................... 149 Data Lost Generation Conditions ..................150 CHAPTER 10 AIU (AUDIO INTERFACE UNIT) ..................152 10.1 General ............................152 10.2 Register Set..........................152...
Page 14 12.3 Transmission Procedure......................186 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS)..............187 13.1 General.............................187 13.2 Configuration Register Set ....................188 13.2.1 VID (offset address: 0x00 to 0x01)..................190 13.2.2 DID (offset address: 0x02 to 0x03)..................190 13.2.3 PCICMD (offset address: 0x04 to 0x05).................191 13.2.4 PCISTS (offset address: 0x06 to 0x07) ..................193 13.2.5 RID (offset address: 0x08) .....................194 13.2.6...
Page 15 13.2.40 PMC (offset address: 0xA2 to 0xA3) ..................218 13.2.41 PMCSR (offset address: 0xA4 to 0xA5) ................. 219 13.2.42 PMCSR_BSE (offset address: 0xA6) ..................219 13.2.43 DATA (offset address: 0xA7) ....................220 13.2.44 TEST (offset address: 0xFC) ....................220 13.3 ExCA Register Set ........................221 13.3.1 ID_REV (PCI offset address: 0x800, ExCA offset address: 0x00) .........
Page 16 13.3.40 MEM_WIN3_EAH (PCI offset address: 0x82B, ExCA offset address: 0x2B)......244 13.3.41 MEM_WIN3_OAL (PCI offset address: 0x82C, ExCA offset address: 0x2C)......245 13.3.42 MEM_WIN3_OAH (PCI offset address: 0x82D, ExCA offset address: 0x2D) ......245 13.3.43 EXT_INDX (ExCA offset address: 0x2E)................245 13.3.44 EXT_DATA (ExCA offset address: 0x2F)................246 13.3.45 MEM_WIN4_SAL (PCI offset address: 0x830, ExCA offset address: 0x30) ......246 13.3.46...
Page 17 14.1 Features...........................274 14.2 USB Host Control Configuration Registers .................275 14.2.1 Register set ..........................276 14.2.2 Command register (offset address: 0x04) ................277 14.2.3 Status register (offset address: 0x06) ..................278 14.2.4 Base address register (offset address: 0x10) ................ 279 14.2.5 Power management register (offset address: 0xE0) ..............
Page 18 14.4.14 HC state transitions ........................329 14.4.15 List service flow ........................330 CHAPTER 15 AC97U (AC97 UNIT)......................336 15.1 General.............................336 15.2 Configuration Register Set ....................336 15.2.1 VID (offset address: 0x00 to 0x01)..................337 15.2.2 DID (offset address: 0x02 to 0x03)..................337 15.2.3 PCICMD (offset address: 0x04 to 0x05).................338 15.2.4 PCISTS (offset address: 0x06 to 0x07) ..................339 15.2.5...
Page 19 15.3.20 ADC1_CTRL (offset address: 0x54)..................370 15.3.21 ADC1L (offset address: 0x58)....................371 15.3.22 ADC1_BADDR (offset address: 0x5C)................... 372 15.3.23 ADC2_CTRL (offset address: 0x60)..................373 15.3.24 ADC2L (offset address: 0x64)....................374 15.3.25 ADC2_BADDR (offset address: 0x68) ................... 375 15.3.26 ADC3_CTRL (offset address: 0x6C) ..................376 15.3.27 ADC3L (offset address: 0x70)....................
Page 20 LIST OF FIGURES (1/2) Figure No. Title Page Internal Block Diagram and Connection Example with External Blocks............26 External Circuit of Clock Oscillator .........................62 Examples of Improperly Connected Resonators ....................63 DMA Space Used in DMA Transfers ......................75 Interrupt Control Outline Diagram........................91 Time Lag Until Status Change Is Reflected in VRCINT Signal (When Sampling with SCLK) ......92 Time Lag Until Status Change Is Reflected in VRCINT Signal (When Sampling with PCLK) ......93 PIU Peripheral Block Diagram........................126...
Page 21 LIST OF FIGURES (2/2) Figure No. Title Page 14-4 Low-Speed Device Cable and Resistor Connections...................317 14-5 Relationship Between EDs and TDs ......................318 14-6 InterruptED List ............................319 14-7 Bandwidth Allocation Method ........................320 14-8 4:1 Control Bulk Service Ratio ........................320 14-9 ED Format ..............................321 14-10 GeneralTD Format ............................323 14-11...
Page 22 LIST OF TABLES (1/3) Table No. Title Page PCI Devices and Component Units ........................28 BCU Configuration Registers .........................29 DMAAU Registers ............................30 DCU Registers..............................30 CMU Registers ...............................30 ICU Registers ..............................31 GIU Registers ..............................31 PIU Registers ..............................32 AIU Registers ..............................33 1-10 KIU Registers ..............................33 1-11 PS2CH1 Registers ............................34 1-12...
Page 23 LIST OF TABLES (2/3) Table No. Title Page BCU Configuration Registers .........................64 DMAAU Registers ............................76 DMA Priority Levels............................81 DCU Registers ...............................81 CMU Registers ...............................87 Assignment of Sampling Clocks and Interrupt Sources .................92 ICU Registers ..............................93 GPIO Pin Outline............................107 GIU Registers...............................108 Correspondences Between Interrupt Mask and Interrupt Hold ..............122 Alternate Function Correspondence Table of V 4173................124...
Page 24 LIST OF TABLES (3/3) Table No. Title Page 13-8 CARDU1 (Slot 1) V Settings........................271 13-9 CARDU1 (Slot 1) V Settings ........................271 13-10 CARDU2 (Slot 2) V Settings........................272 13-11 CARDU2 (Slot 2) V Settings ........................272 14-1 USB Host Control Configuration Registers....................276 14-2 Host Control Operational Registers......................282 14-3...
Page 25: Chapter 1 Overview
The V 4173 is a companion chip that is to be connected to a product having a PCI bus in the V 4100 Series such as NEC’s 64-bit RISC processor V 4122. The V 4173 incorporates the I/O macros necessary for a handheld PC running Windows™ CE, and can also access design resources on a personal computer by means of the PCI bus interface.
Page 26: Ordering Information
CHAPTER 1 OVERVIEW Ordering Information Part Number Package Internal Maximum Operating Frequency µ PD31173F1-33-HN1 304-pin plastic FBGA (19 × 19) 33 MHz Internal Block Configuration Figure 1-1 shows an internal block diagram of the V 4173 and connection example with external blocks. Figure 1-1.
Page 27 CHAPTER 1 OVERVIEW (4) DMAAU (DMA Address Unit) The DMAAU controls the addresses of DMA transfers that are used by the audio interface (MIC, speakers). (5) DCU (DMA Control Unit) The DCU controls the arbitration of DMA transfers that are used by the audio interface (MIC, speakers). (6) CMU (Clock Mask Unit) The CMU controls the supply of PCI clock (PCICLK), PIB bus clock (TClock, internal), and 48 MHz clock pulses to internal peripheral units.
Page 28: Pci Device Configuration
CHAPTER 1 OVERVIEW PCI Device Configuration The V 4173 consists of a total of five PCI devices, which include three multifunction devices having BCU, AC97, and USB functions and two single function devices for PCMCIA channel 1 and channel 2. The following table shows the PCI devices and the corresponding units comprising each one.
Page 29: Lists Of Registers
CHAPTER 1 OVERVIEW Lists of Registers The following tables list the registers of each unit. Table 1-2. BCU Configuration Registers Register Symbol Function Offset Address Vendor ID register 0x00 to 0x01 Device ID register 0x02 to 0x03 PCICMD PCI command register 0x04 to 0x05 PCISTS PCI device status register...
Page 30 CHAPTER 1 OVERVIEW Table 1-3. DMAAU Registers Register Symbol Function Address AIUIBALREG AIU IN DMA base address lower register 0x000 AIUIBAHREG AIU IN DMA base address higher register 0x002 AIUIALREG AIU IN DMA address lower register 0x004 AIUIAHREG AIU IN DMA address higher register 0x006 AIUOBALREG AIU OUT DMA base address lower register...
Page 31 CHAPTER 1 OVERVIEW Table 1-6. ICU Registers Register Symbol Function Address SYSINT1REG System interrupt register 1 (level 1) 0x060 PIUINTREG PIU interrupt register (level 2) 0x062 AIUINTREG AIU interrupt register (level 2) 0x064 KIUINTREG KIU interrupt register (level 2) 0x066 GIULINTREG GIUL interrupt register (level 2) 0x068...
Page 32 CHAPTER 1 OVERVIEW Table 1-8. PIU Registers Register Symbol Function Address PIUCNTREG PIU control register 0x0A2 PIUINTREG PIU interrupt register 0x0A4 PIUSIVLREG PIU data sampling period setting register 0x0A6 PIUSTBLREG PIU A/D converter delay time setting register 0x0A8 PIUCMDREG PIU A/D command register 0x0AA PIUASCNREG PIU A/D port scan register...
Page 33 CHAPTER 1 OVERVIEW Table 1-9. AIU Registers Register Symbol Function Address MDMADATREG MIC DMA data register 0x0E0 SDMADATREG Speaker DMA data register 0x0E2 SODATREG Speaker output data register 0x0E6 SCNTREG Speaker output control register 0x0E8 SCNVRREG Speaker conversion rate register 0x0EA MIDATREG MIC input data register...
Page 34 CHAPTER 1 OVERVIEW Table 1-11. PS2CH1 Registers Register Symbol Function Address PS2CH1DATA PS/2 channel 1 transmission/reception data register 0x120 PS2CH1CTRL PS/2 channel 1 control register 0x122 PS2CH1RST PS/2 channel 1 reset register 0x124 Remark The sum of a value in the Address column added to the base address that is set according to the BADR register of the BCU will be the physical address.
Page 35 CHAPTER 1 OVERVIEW Table 1-13. CARDU Configuration Registers (1/2) Register Symbol Function Offset Address Vendor ID register 0x00 to 0x01 Device ID register 0x02 to 0x03 PCICMD PCI command register 0x04 to 0x05 PCISTS PCI device status register 0x06 to 0x07 Revision ID register 0x08 CLASSC...
Page 36 CHAPTER 1 OVERVIEW Table 1-13. CARDU Configuration Registers (2/2) Register Symbol Function Offset Address INTL Interrupt line register 0x3C INTP Interrupt pin register 0x3D BRGCNT Bridge control register 0x3E to 0x3F SUBVID Subsystem vendor ID register 0x40 to 0x41 SUBID Subsystem ID register 0x42 to 0x43 PC16BADR...
Page 37 CHAPTER 1 OVERVIEW Table 1-14. ExCA Registers (1/2) Register Symbol Function Offset Address PCI Memory ExCA ID_REV ID/revision register 0x800 0x00 IF_STATUS Interface status register 0x801 0x01 PWR_CNT Power control register 0x802 0x02 INT_GEN_CNT Interrupt/general-purpose control register 0x803 0x03 CARD_SC Card status change register 0x804 0x04...
Page 38 CHAPTER 1 OVERVIEW Table 1-14. ExCA Registers (2/2) Register Symbol Function Offset Address PCI Memory ExCA MEM_WIN1_OAH Memory window 1 offset address higher byte register 0x81D 0x1D GLO_CNT Global control register 0x81E 0x1E − Reserved 0x81F 0x1F MEM_WIN2_SAL Memory window 2 start address lower byte register 0x820 0x20 MEM_WIN2_SAH...
Page 39 CHAPTER 1 OVERVIEW Table 1-15. ExCA Extended Registers Register Symbol Function Offset Address PCI Memory ExCA Extension MEM_WIN0_SAU Memory window 0 start address higher byte register 0x840 0x00 MEM_WIN1_SAU Memory window 1 start address higher byte register 0x841 0x01 MEM_WIN2_SAU Memory window 2 start address higher byte register 0x842 0x02...
Page 40 CHAPTER 1 OVERVIEW Table 1-17. USB Host Control Configuration Registers Name Offset Address Vendor ID register 0x00 Device ID register 0x02 Command register 0x04 Status register 0x06 Revision ID register 0x08 Class code base address register 0x09 Class code sub class register Class code programming interface register Cache line size register 0x0C...
Page 41 CHAPTER 1 OVERVIEW Table 1-18. Host Control Operational Registers Register Symbol Function Offset Address HcRevision HC revision register 0x00 HcControl HC control register 0x04 HcCommandStatus HC command register 0x08 HcInterruptStatus HC interrupt request detection register 0x0C HcInterruptEnable HC interrupt request enable register 0x10 HcInterruptDisable HC interrupt request disable register...
Page 42 CHAPTER 1 OVERVIEW Table 1-19. AC97U PCI Configuration Registers Register Symbol Function Offset Address Vendor ID register 0x00 to 0x01 Device ID register 0x02 to 0x03 PCICMD PCI command register 0x04 to 0x05 PCISTS PCI device status register 0x06 to 0x07 Revision ID register 0x08 CLASSC...
Page 43 CHAPTER 1 OVERVIEW Table 1-20. AC97U Operational Registers Register Symbol Function Offset Address INT_CLR/INT_STATUS Interrupt clear/status register 0x00 CODEC_WR Codec write register 0x04 CODEC_RD Codec read register 0x08 CODEC_REQ Codec slot request register 0x0C SLOT12_WR Slot 12 write register 0x10 SLOT12_RD Slot 12 read register 0x14...
Page 44: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS This chapter describes the pin functions of the V 4173. Pin Configuration • 304-pin plastic FBGA (19 × 19) µ PD31173F1-33-HN1 Bottom View Top View Index mark User’s Manual U14579EJ2V0UM...
Page 45 CHAPTER 2 PIN FUNCTIONS Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name CD22# KSCAN2/GPIO2 TEST2 BVD22# TEST0 KPORT3/GPIO11 ADAGND PWCCLK GND2 PWCLATCH GND2 ADDV RCVBE GND2 TESTC BVD21# IOWR2# TPX1/GPIO17 VS11# IORD2# VS12# CE11# SYNC GND2 CE12# KSCAN8/PS2CLK2 GND2...
Page 46 CHAPTER 2 PIN FUNCTIONS Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name GND3 C2D3 GND2 C1A3 C2D2 C2A13 C2D14 C2D1 C2A12 C2D13 C2D0 C2A11 C2D12 C1A21 C2A10 C2D11 C1A22 C1D10 GND3 C1A23 C1D11 GND2 C1A24 C1D12 C1A4 GND2 GND2...
Page 47 CHAPTER 2 PIN FUNCTIONS Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name GND2 BVD12# AA21 C2A0 GND2 INPACK1# AA22 C2A6 C2A2 C2A5 C2A1 READY1 C1D15 GND2 CD11# BVD11# WAIT1# PCLK GND2 SCLK AD30 GND2 CD12# AD27 AD28 AD31 AD22...
Page 48 CHAPTER 2 PIN FUNCTIONS Pin Identification ACLINKRST#: AC-Link Reset DAAV Analog Reference Voltage for AD(31:0): Address/Data Bus D/A Converter ADAGND: A/D Converter Analog Ground DEVSEL#: Device Select ADAV A/D Converter Analog V DN1, DN2: Data Negative ADAV Analog Reference Minus DP1, DP2: Data Positive Voltage for A/D Converter...
Page 49 CHAPTER 2 PIN FUNCTIONS SERR#: System Error TRDY#: Target Ready STOP#: Stop Power Supply for I/O Buffer SYNC: Synchronization Power Supply Internal Circuit TEST(3:0): Test VRCINT: Series Companion Chip TESTC: Test Clock Interrupt TPEN: Touch Panel Interface Enable VS11#, VS12#, TPX(1:0): Touch Panel Interface VS21#, VS22#:...
Page 50: Pin Function Lists
CHAPTER 2 PIN FUNCTIONS Pin Function Lists 2.2.1 PCI bus interface signals Table 2-1. PCI Bus Interface Signals Signal Name Function AD(31:0) This is a 32-bit bus that multiplexes the address bus and data bus. CBE(3:0)# This is a signal that multiplexes the bus command and byte enable signals. IDSEL This is an initialization device selection signal (for a PCI multifunction device).
Page 51: Pc Card Interface Signals
CHAPTER 2 PIN FUNCTIONS 2.2.4 PC card interface signals Table 2-4. PC Card Interface Signals Signal Name Function C1A(25:0) This is the PC card slot 1 address bus. C1D(15:0) This is the PC card slot 1 data bus. CE1(2:1)# This is the PC card slot 1 chip select signal. CD1(2:1)# This is the PC card slot 1 card detect signal.
Page 52 CHAPTER 2 PIN FUNCTIONS Table 2-5. Correspondence of Signal Names for Each PC Card Interface Mode (1/2) 4173 16-Bit PC Card Slot 1 Slot 2 Memory Card I/O Card C1A25 C2A25 C1A24 C2A24 C1A23 C2A23 C1A22 C2A22 C1A21 C2A21 C1A20 C2A20 C1A19 C2A19...
Page 53 CHAPTER 2 PIN FUNCTIONS Table 2-5. Correspondence of Signal Names for Each PC Card Interface Mode (2/2) 4173 16-Bit PC Card Slot 1 Slot 2 Memory Card I/O Card C1D5 C2D5 C1D4 C2D4 C1D3 C2D3 C1D2 C2D2 C1D1 C2D1 C1D0 C2D0 CE12# CE22#...
Page 54: Keyboard Interface Signals
CHAPTER 2 PIN FUNCTIONS 2.2.5 Keyboard interface signals Table 2-6. Keyboard Interface Signals Signal Name Function KPORT(7:0)/GPIO(15:8) These are keyboard scan data input signals. They are used to scan for pressed keys on the keyboard. When these are used as KPORT signals, external pull-down resistors are required. When these are not used as KPORT signals, they can be used as general-purpose I/O ports.
Page 55: Touch Panel Interface Signals
CHAPTER 2 PIN FUNCTIONS 2.2.7 Touch panel interface signals Table 2-8. Touch Panel Interface Signals Signal Name Function TPX(1:0)/GPIO(17:16) These are touch panel I/O signals. The coordinates at which the touch panel was pressed are detected by applying voltage to the X coordinate and inputting the voltage of the Y coordinate.
Page 56: Interrupt Interface Signal
CHAPTER 2 PIN FUNCTIONS 2.2.10 Interrupt interface signal Table 2-11. Interrupt Interface Signal Signal Name Function VRCINT This is an integrated interrupt request signal to the CPU. 2.2.11 Clock interface signals Table 2-12. Clock Interface Signals Signal Name Function PCLK This is the 33 MHz clock input signal.
Page 57: Power Supplies And Grounds
CHAPTER 2 PIN FUNCTIONS 2.2.13 Power supplies and grounds Table 2-15. A/D Converter Power Supplies and Grounds Signal Name Function ADAV This signal is for the dedicated analog power supply for the A/D converter. ADAGND This signal is for the dedicated analog ground for the A/D converter. ADDV This signal is for the dedicated digital power supply for the A/D converter.
Page 58: Pin Status And Recommended Connection Examples
CHAPTER 2 PIN FUNCTIONS Pin Status and Recommended Connection Examples Table 2-18 shows the status of the pins when the V 4173 is reset (when the PCIRST# signal is at low level) and examples of recommended, logically required pin processing. Table 2-18.
Page 59 CHAPTER 2 PIN FUNCTIONS Table 2-18. Pin Status and Recommended Connection Examples (2/4) Pin Name Drive Withstand Internal External Status After Note 1 Capacity (mA) Voltage (V) Processing Processing Reset − − CARDU1 C1A(25:23) Hi-Z − C1A(22:20) Pull-up Hi-Z − −...
Page 60 CHAPTER 2 PIN FUNCTIONS Table 2-18. Pin Status and Recommended Connection Examples (3/4) Pin Name Drive Withstand Internal External Status After Note 1 Capacity (mA) Voltage (V) Processing Processing Reset − − CARDU2 C2A(15:23) Hi-Z − C2A(22:20) Pull-up Hi-Z − −...
Page 61 CHAPTER 2 PIN FUNCTIONS Table 2-18. Pin Status and Recommended Connection Examples (4/4) Pin Name Drive Withstand Internal External Status After Capacity (mA) Voltage (V) Processing Processing Reset − Note 1 KIU/PS2U KPORT(7:0)/ Pull-up Hi-Z GPIO(15:8) − − Note 2 KSCAN11/PS2DATA1 Hi-Z −...
Page 62: Clock Oscillator Connection
CHAPTER 2 PIN FUNCTIONS Clock Oscillator Connection Figure 2-1. External Circuit of Clock Oscillator (a) Crystal oscillation (b) External clock 4173 4173 CLK48MX1 External clock CLK48MX1 Open CLK48MX2 CLK48MX2 Cautions 1. When using a clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance.
Page 63 CHAPTER 2 PIN FUNCTIONS Figure 2-2. Examples of Improperly Connected Resonators (a) Connection circuit wiring is too long (b) Signal lines are crossed GND CLK48MX1 CLK48MX2 GND CLK48MX1 CLK48MX2 (c) A high fluctuating current flows near (d) A current flows over the ground line of the oscillator the signal line (the potentials of points A, B, and C change) GND CLK48MX1 CLK48MX2...
Page 64: Chapter 3 Bcu (Bus Control Unit)
CHAPTER 3 BCU (BUS CONTROL UNIT) General The BCU controls the PIB (Peripheral Internal Bus), which is an internal bus. The DMAAU, DCU, CMU, ICU, GIU, PIU, AIU, KIU, PS2CH1, PS2CH2, and ADU are connected to the PIB. Register Set Table 3-1 lists the BCU configuration registers.
Page 65: Vid (Offset Address: 0X00 To 0X01)
Name VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 After reset Name Function 15:0 VID(15:0) Vendor ID 0x1033: NEC 3.2.2 DID (offset address: 0x02 to 0x03) Name DID15 DID14 DID13 DID12 DID11 DID10 DID9 DID8 After reset Name DID7 DID6...
Page 66: Pcicmd (Offset Address: 0X04 To 0X05)
CHAPTER 3 BCU (BUS CONTROL UNIT) 3.2.3 PCICMD (offset address: 0x04 to 0x05) Name FBTB_EN SERR_EN After reset Name AD_STEP PERR_EN VGA_P_ MEMW_ SP_CYC MASTER_ MEM_EN IO_EN SNOOP INV_EN After reset Name Function 15:10 Reserved. Write 0 to these bits. 0 is returned after a read. FBTB_EN Enables/disables fast Back to Back.
Page 67: Pcists (Offset Address: 0X06 To 0X07)
CHAPTER 3 BCU (BUS CONTROL UNIT) 3.2.4 PCISTS (offset address: 0x06 to 0x07) Name DETECT_ SIG_SERR SIG_ DEVSEL1 DEVSEL0 DETECT_ PERR MABORT TABORT TABOT D_PERR After reset Name FBTB_CAP After reset Name Function DETECT_PERR Data and address parity error detection. Cleared to 0 when 1 is written. 1: Detected 0: Not detected SIG_SERR...
Page 68: Rid (Offset Address: 0X08)
CHAPTER 3 BCU (BUS CONTROL UNIT) 3.2.5 RID (offset address: 0x08) Name RID7 RID6 RID5 RID4 RID3 RID2 RID1 RID0 After reset Name Function RID(7:0) Revision ID 3.2.6 CLASSC (offset address: 0x09 to 0x0B) Name CLASSC23 CLASSC22 CLASSC21 CLASSC20 CLASSC19 CLASSC18 CLASSC17 CLASSC16...
Page 69: Mlt (Offset Address: 0X0D)
CHAPTER 3 BCU (BUS CONTROL UNIT) 3.2.8 MLT (offset address: 0x0D) Name MLT7 MLT6 MLT5 MLT4 MLT3 MLT2 MLT1 MLT0 After reset Name Function MLT(7:4) Sets the latency timer. 1111: 30 PCLK (900 ns) 0010: 17 PCLK (510 ns) 0001: 16 PCLK (480 ns) 0000: 0 PCLK (0 ns) MLT(3:0) Write 0 to these bits.
Page 70: Badr (Offset Address: 0X10 To 0X13)
CHAPTER 3 BCU (BUS CONTROL UNIT) 3.2.11 BADR (offset address: 0x10 to 0x13) Name BADR31 BADR30 BADR29 BADR28 BADR27 BADR26 BADR25 BADR24 After reset Name BADR23 BADR22 BADR21 BADR20 BADR19 BADR18 BADR17 BADR16 After reset Name BADR15 BADR14 BADR13 BADR12 BADR11 BADR10 BADR9...
Page 71: Subvid (Offset Address: 0X2C To 0X2D)
CHAPTER 3 BCU (BUS CONTROL UNIT) 3.2.12 SUBVID (offset address: 0x2C to 0x2D) Name SUBVID15 SUBVID14 SUBVID13 SUBVID12 SUBVID11 SUBVID10 SUBVID9 SUBVID8 After reset Name SUBVID7 SUBVID6 SUBVID5 SUBVID4 SUBVID3 SUBVID2 SUBVID1 SUBVID0 After reset Name Function 15:0 SUBVID(15:0) Subsystem vendor ID This is a vendor identification number to be used for recognizing the system or option card.
Page 72: Intl (Offset Address: 0X3C)
CHAPTER 3 BCU (BUS CONTROL UNIT) 3.2.14 INTL (offset address: 0x3C) Name INTL7 INTL6 INTL5 INTL4 INTL3 INTL2 INTL1 INTL0 After reset Name Function INTL(7:0) Sets the interrupt request line. Since this function is not supported by the BCU, settings for these bits are invalid. Use the ICU to set the interrupt request line.
Page 73: Max_Lat (Offset Address: 0X3F)
CHAPTER 3 BCU (BUS CONTROL UNIT) 3.2.17 MAX_LAT (offset address: 0x3F) Name MAX_LAT7 MAX_LAT6 MAX_LAT5 MAX_LAT4 MAX_LAT3 MAX_LAT2 MAX_LAT1 MAX_LAT0 After reset Name Function MAX_LAT(7:0) Maximum delay time until a response is returned when the PCI bus usage right is requested.
Page 74: Idselnum (Offset Address: 0X41)
CHAPTER 3 BCU (BUS CONTROL UNIT) 3.2.19 IDSELNUM (offset address: 0x41) Name C2IDSEL1 C2IDSEL0 C1IDSEL1 C1IDSEL0 After reset Name Function Reserved. Write 0 to these bits. 0 is returned after a read. C2IDSEL(1:0) Selects the IDSEL signal of CARDU2 (PC card channel 2). 11: Reserved 10: Selects the AD25 signal as the IDSEL signal.
Page 75: Chapter 4 Dmaau (Dma Address Unit)
CHAPTER 4 DMAAU (DMA ADDRESS UNIT) General The DMAAU register controls the DMA addresses for the AIU. The DMA channel used for each unit can set a DMA start address as any half-word address in the physical address from 0x0000 0000 to 0xFFFF FFFE, and is retained in DRAM as a 2 KB block that starts at the address which is generated by masking the lower 10 bits of the DMA start address.
Page 76: Register Set
CHAPTER 4 DMAAU (DMA ADDRESS UNIT) Register Set Table 4-1 lists the DMAAU registers. Table 4-1. DMAAU Registers Address Register Symbol Function BASE + 0x000 AIUIBALREG AIU IN DMA Base Address Register Low BASE + 0x002 AIUIBAHREG AIU IN DMA Base Address Register High BASE + 0x004 AIUIALREG AIU IN DMA Address Register Low...
Page 77: Aiu In Dma Base Address Registers
CHAPTER 4 DMAAU (DMA ADDRESS UNIT) 4.2.1 AIU IN DMA base address registers (1) AIUIBALREG (base address + 0x000) Name AIUIBA15 AIUIBA14 AIUIBA13 AIUIBA12 AIUIBA11 AIUIBA10 AIUIBA9 AIUIBA8 After reset Name AIUIBA7 AIUIBA6 AIUIBA5 AIUIBA4 AIUIBA3 AIUIBA2 AIUIBA1 AIUIBA0 After reset Name Function 15:1...
Page 78: Aiu In Dma Address Registers
CHAPTER 4 DMAAU (DMA ADDRESS UNIT) 4.2.2 AIU IN DMA address registers (1) AIUIALREG (base address + 0x004) Name AIUIA15 AIUIA14 AIUIA13 AIUIA12 AIUIA11 AIUIA10 AIUIA9 AIUIA8 After reset Name AIUIA7 AIUIA6 AIUIA5 AIUIA4 AIUIA3 AIUIA2 AIUIA1 AIUIA0 After reset Name Function 15:0...
Page 79: Aiu Out Dma Base Address Registers
CHAPTER 4 DMAAU (DMA ADDRESS UNIT) 4.2.3 AIU OUT DMA base address registers (1) AIUOBALREG (base address + 0x008) Name AIUOBA15 AIUOBA14 AIUOBA13 AIUOBA12 AIUOBA11 AIUOBA10 AIUOBA9 AIUOBA8 After reset Name AIUOBA7 AIUOBA6 AIUOBA5 AIUOBA4 AIUOBA3 AIUOBA2 AIUOBA1 AIUOBA0 After reset Name Function 15:1...
Page 80: Aiu Out Dma Address Registers
CHAPTER 4 DMAAU (DMA ADDRESS UNIT) 4.2.4 AIU OUT DMA address registers (1) AIUOALREG (base address + 0x00C) Name AIUOA15 AIUOA14 AIUOA13 AIUOA12 AIUOA11 AIUOA10 AIUOA9 AIUOA8 After reset Name AIUOA7 AIUOA6 AIUOA5 AIUOA4 AIUOA3 AIUOA2 AIUOA1 AIUOA0 After reset Name Function 15:0...
Page 81: Chapter 5 Dcu (Dma Control Unit)
CHAPTER 5 DCU (DMA CONTROL UNIT) General The DCU register is used for DMA control. Specifically, it controls acknowledgment from the BCU that handles bus arbitration and DMA requests from the on-chip peripheral I/O unit (AIU). It also controls DMA enable/disable settings. DMA Priority Control When a conflict occurs between DMA requests sent from on-chip peripheral I/O unit, the following priority levels are used to resolve the conflict.
Page 82: Dmarstreg (Base Address + 0X020)
CHAPTER 5 DCU (DMA CONTROL UNIT) 5.3.1 DMARSTREG (base address + 0x020) Name After reset Name DMARST After reset Name Function 15:1 Reserved. Write 0 to these bits. 0 is returned after a read. DMARST Reset DMA controller 1: Reset 0: Normal This register is used to reset the DMA controller.
Page 83: Dmasenreg (Base Address + 0X024)
CHAPTER 5 DCU (DMA CONTROL UNIT) 5.3.3 DMASENREG (base address + 0x024) Name After reset Name DMASEN After reset Name Function 15:1 Reserved. Write 0 to these bits. 0 is returned after a read. DMASEN Enable DMA sequencer 1: Enable 0: Disable This register is used to enable/disable the DMA sequencer.
Page 84: Dmamskreg (Base Address + 0X026)
CHAPTER 5 DCU (DMA CONTROL UNIT) 5.3.4 DMAMSKREG (base address + 0x026) Name After reset Name DMAMSKA DMAMSKA After reset Name Function 15:4 Reserved. Write 0 to these bits. 0 is returned after a read. DMAMSKAIN Audio input DMA transfer enable/disable 1: Enable 0: Disable DMAMSKAOUT...
Page 85: Dmareqreg (Base Address + 0X028)
CHAPTER 5 DCU (DMA CONTROL UNIT) 5.3.5 DMAREQREG (base address + 0x028) Name After reset Name DRQAIN DRQAOUT After reset Name Function 15:4 Reserved. Write 0 to these bits. 0 is returned after a read. DRQAIN Audio input DMA transfer request 1: Request pending 0: No request DRQAOUT...
Page 86: Chapter 6 Cmu (Clock Mask Unit)
CHAPTER 6 CMU (CLOCK MASK UNIT) General As various input clocks are supplied from the CPU to each unit, a masking method enables power consumption to be curtailed in units that are not used. The units for which this masking method are used are the USBU, CARDU1, CARDU2, KIU, PIU, AIU, PS2CH1, PS2CH2, and AC97U units.
Page 87: Register Set
CHAPTER 6 CMU (CLOCK MASK UNIT) Register Set Table 6-1 lists the CMU registers. Table 6-1. CMU Registers Address Register Symbol Function BASE + 0x040 CMUCLKMSK CMU Clock Mask Register BASE + 0x042 CMUSRST CMU Soft Reset Register Remark BASE: Base address. This is set by using the BADR register of the BCU (see 3.2.11). These registers are described in detail below.
Page 88 CHAPTER 6 CMU (CLOCK MASK UNIT) (2/2) Name Function MSKCARD1 Supply/mask PCICLK to CARDU2 unit 1: Supply 0: Mask MSKUSB Supply/mask PCICLK to USBU unit 1: Supply 0: Mask MSKPS2CH2 Supply/mask TClock to PS2CH2 unit 1: Supply 0: Mask MSKPS2CH1 Supply/mask TClock to PS2CH1 unit 1: Supply 0: Mask...
Page 89: Cmusrst (Base Address + 0X042)
CHAPTER 6 CMU (CLOCK MASK UNIT) 6.2.2 CMUSRST (base address + 0x042) Name After reset Note Note Name AC97RST CARD2RST CARD1RST USBRST After reset Name Function 15:4 Reserved. Write 0 to these bits. 0 is returned after a read. AC97RST Soft reset to AC97U unit 1: Soft reset 0: Soft reset released...
Page 90: Chapter 7 Icu (Interrupt Control Unit)
CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) General The ICU collects interrupt requests from the various on-chip peripheral units and transfers these interrupt request signals to the CPU. The functions of the ICU’s internal blocks are briefly described below. • ADDECICU … Decodes read/write addresses from the CPU that are used for ICU registers. •...
Page 91 CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) Figure 7-1. Interrupt Control Outline Diagram Level 2 Level 1 dozepiuint GIULINTREG MGIULINTREG AND/OR GIUHINTREG MGIUHINTREG KIUINTREG AND/OR SYSINT1REG MKIUINTREG AIUINTREG AND/OR MAIUINTREG PIUINTREG AND/OR MPIUINTREG AC97int1 AC97int PS2CH1int VRCINT AND/OR PS2CH2int PCMCIA1int PCMCIA2int USBint MSYSINT1REG Interrupt status register...
Page 92 CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) The VRCINT signal (interrupt request signal) output timing and the timing of the status change of each interrupt status register are described below. In the ICU, the sampling clock differs depending on the interrupt source. The assignment of sampling clock and interrupt sources are shown in the following table.
Page 93: Register Set
CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) Figure 7-3. Time Lag Until Status Change Is Reflected in VRCINT Signal (When Sampling with PCLK) PCLK (input) SCLK (input) Internal interrupt source change Reflection in ICU status register VRCINT internal synchronization VRCINT (output) Remark a: The time between when the internal interrupt source changes and when this change is reflected in the ICU status register (MAX.
Page 94: Sysint1Reg (Base Address + 0X060)
CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) 7.2.1 SYSINT1REG (base address + 0x060) (1/2) Name DOZE AC97INTR1 AC97INTR GIUINTR PIUINTR After reset Name KIUINTR AIUINTR PIUINTR PS2CH1 PS2CH2 PCMCIA1 PCMCIA2 USBINTR INTR INTR INTR INTR After reset Name Function 15:14 Reserved. Write 0 to these bits. 0 is returned after a read. DOZEPIUINTR PIU interrupt request during Suspend mode 1: Occurred...
Page 95 CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) (2/2) Name Function PCMCIA1INTR PCMCIA1 interrupt request 1: Occurred 0: Normal PCMCIA2INTR PCMCIA2 interrupt request 1: Occurred 0: Normal USBINTR USB interrupt request 1: Occurred 0: Normal This register indicates when various interrupt requests occur in the V 4173 system.
Page 96: Piuintreg (Base Address + 0X062)
CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) 7.2.2 PIUINTREG (base address + 0x062) Name After reset Name PADCMD PADADP PADPAGE1 PADPAGE0 PADDLO PENCHG INTR INTR INTR INTR STINTR INTR After reset Name Function 15:7 Reserved. Write 0 to these bits. 0 is returned after a read. PADCMDINTR PIU command scan interrupt request.
Page 97: Aiuintreg (Base Address + 0X064)
CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) 7.2.3 AIUINTREG (base address + 0x064) Name INTMEND INTM INTMIDLE INTMST After reset Name INTSEND INTS INTSIDLE After reset Name Function 15:12 Reserved. Write 0 to these bits. 0 is returned after a read. INTMEND Audio input (MIC) DMA buffer 2 page interrupt request 1: Occurred...
Page 98: Kiuintreg (Base Address + 0X066)
CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) 7.2.4 KIUINTREG (base address + 0x066) Name After reset Name KDATLOST KDATRDY SCANINT After reset Name Function 15:3 Reserved. Write 0 to these bits. 0 is returned after a read. KDATLOST Key scan data lost interrupt request 1: Occurred 0: Normal KDATRDY...
Page 99: Giulintreg (Base Address + 0X068)
CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) 7.2.5 GIULINTREG (base address + 0x068) Name INTS15 INTS14 INTS13 INTS12 INTS11 INTS10 INTS9 INTS8 After reset Name INTS7 INTS6 INTS5 INTS4 INTS3 INTS2 INTS1 INTS0 After reset Name Function 15:0 INTS(15:0) Interrupt request input to GPIO(15:0) pin 1: Occurred 0: Normal This register indicates when various GIU-related interrupt requests occur.
Page 100: Msysint1Reg (Base Address + 0X06C)
CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) 7.2.7 MSYSINT1REG (base address + 0x06C) (1/2) Name DOZE AC97INTR1 AC97INTR GIUINTR PIUINTR After reset Name KIUINTR AIUINTR PIUINTR PS2CH1 PS2CH2 PCMCIA1 PCMCIA2 USBINTR INTR INTR INTR INTR After reset Name Function 15:14 Reserved. Write 0 to these bits. 0 is returned after a read. DOZEPIUINTR PIU interrupt enable during Suspend mode 1: Enabled...
Page 101 CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) (2/2) Name Function PCMCIA1INTR PCMCIA1 interrupt enable 1: Enabled 0: Disabled PCMCIA2INTR PCMCIA2 interrupt enable 1: Enabled 0: Disabled USBINTR USB interrupt enable 1: Enabled 0: Disabled This register is used to mask various interrupt requests that occur in the V 4173 system.
Page 102: Mpiuintreg (Base Address + 0X06E)
CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) 7.2.8 MPIUINTREG (base address + 0x06E) Name After reset Name PADCMD PADADP PADPAGE1 PADPAGE0 PADDLO PENCHG INTR INTR INTR INTR STINTR INTR After reset Name Function 15:7 Reserved. Write 0 to these bits. 0 is returned after a read. PADCMDINTR PIU command scan interrupt enable 1: Enabled...
Page 103: Maiuintreg (Base Address + 0X070)
CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) 7.2.9 MAIUINTREG (base address + 0x070) Name INTMEND INTM INTMIDLE INTMST After reset Name INTSEND INTS INTSIDLE After reset Name Function 15:12 Reserved. Write 0 to these bits. 0 is returned after a read. INTMEND Audio input (MIC) DMA buffer 2 page interrupt enable 1: Enabled...
Page 104: Mkiuintreg (Base Address + 0X072)
CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) 7.2.10 MKIUINTREG (base address + 0x072) Name After reset Name KDAT KDAT SCAN LOST After reset Name Function 15:3 Reserved. Write 0 to these bits. 0 is returned after a read. KDATLOST Key scan data lost interrupt enable 1: Enabled 0: Disabled KDATRDY...
Page 105: Mgiulintreg (Base Address + 0X074)
CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) 7.2.11 MGIULINTREG (base address + 0x074) Name INTS15 INTS14 INTS13 INTS12 INTS11 INTS10 INTS9 INTS8 After reset Name INTS7 INTS6 INTS5 INTS4 INTS3 INTS2 INTS1 INTS0 After reset Name Function 15:0 INTS(15:0) GPIO(15:0) pin interrupt input enable 1: Enabled 0: Disabled This register is used to mask various GIU-related interrupt requests.
Page 106: Notes For Register Setting
CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) Notes for Register Setting There is no register setting flow in relation to the ICU. With regard to the interrupt mask registers, the initial setting is “initial = 0 = mask” after setting. Therefore, enough masks must be cleared to provide sufficient interrupts for the CPU’s start-up processing.
Page 107: Chapter 8 Giu (General-Purpose I/O Unit)
CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) General The GIU controls the GPIO(20:0) pins. GPIO is a general-purpose port for which input and output are available. An interrupt request signal input function can be assigned to GPIO with input signal change (rising edge or falling edge of signal), low level, or high level used as the trigger.
Page 108: Register Set
CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) Register Set Table 8-2 lists the GIU registers. Table 8-2. GIU Registers Address Register Symbol Function BASE + 0x080 GIUDIRL GPIO I/O Select Register L BASE + 0x082 GIUDIRH GPIO I/O Select Register H BASE + 0x084 GIUPIODL GPIO Port I/O Data Register L...
Page 109: Giudirl (Base Address + 0X080)
CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.1 GIUDIRL (base address + 0x080) Name IOS15 IOS14 IOS13 IOS12 IOS11 IOS10 IOS9 IOS8 After reset Name IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 After reset Name Function 15:0 IOS(15:0) GPIO(15:0) pin I/O select 1: Output 0: Input This register is used to set I/O modes for GPIO(15:0) pins.
Page 110: Giudirh (Base Address + 0X082)
CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.2 GIUDIRH (base address + 0x082) Name After reset Name IOS20 IOS19 IOS18 IOS17 IOS16 After reset Name Function 15:5 Reserved. Write 0 to these bits. 0 is returned after a read. IOS(20:16) GPIO(20:16) pin I/O select 1: Output 0: Input This register is used to set I/O modes for GPIO(20:16) pins.
Page 111: Giupiodl (Base Address + 0X084)
CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.3 GIUPIODL (base address + 0x084) Name PIOD15 PIOD14 PIOD13 PIOD12 PIOD11 PIOD10 PIOD9 PIOD8 After reset Name PIOD7 PIOD6 PIOD5 PIOD4 PIOD3 PIOD2 PIOD1 PIOD0 After reset Name Function 15:0 PIOD(15:0) GPIO(15:0) pin output data specification 1: High 0: Low This register is used to read GPIO(15:0) pins and write data.
Page 112: Giupiodh (Base Address + 0X086)
CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.4 GIUPIODH (base address + 0x086) Name After reset Name PIOD20 PIOD19 PIOD18 PIOD17 PIOD16 After reset Name Function 15:5 Reserved. Write 0 to these bits. 0 is returned after a read. PIOD(20:16) GPIO(20:16) pin output data specification 1: High 0: Low This register is used to read GPIO(20:16) pins and write data.
Page 113: Giuintstatl (Base Address + 0X088)
CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.5 GIUINTSTATL (base address + 0x088) Name INTS15 INTS14 INTS13 INTS12 INTS11 INTS10 INTS9 INTS8 After reset Name INTS7 INTS6 INTS5 INTS4 INTS3 INTS2 INTS1 INTS0 After reset Name Function 15:0 INTS(15:0) Interrupt to GPIO(15:0) pins. Cleared to 0 when 1 is written. 1: Interrupt occurred 0: No interrupt This register indicates the interrupt status of GPIO(15:0) pins.
Page 114: Giuintstath (Base Address + 0X08A)
CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.6 GIUINTSTATH (base address + 0x08A) Name After reset Name INTS20 INTS19 INTS18 INTS17 INTS16 After reset Name Function 15:5 Reserved. Write 0 to these bits. 0 is returned after a read. INTS(20:16) Interrupt to GPIO(20:16) pins. Cleared to 0 when 1 is written. 1: Interrupt occurred 0: No interrupt This register indicates the interrupt status of GPIO(20:16) pins.
Page 115: Giuintenl (Base Address + 0X08C)
CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.7 GIUINTENL (base address + 0x08C) Name INTE15 INTE14 INTE13 INTE12 INTE11 INTE10 INTE9 INTE8 After reset Name INTE7 INTE6 INTE5 INTE4 INTE3 INTE2 INTE1 INTE0 After reset Name Function 15:0 INTE(15:0) Interrupt enable to GPIO(15:0) pins 1: Interrupt enable 0: Interrupt disable This register is used to set interrupt enable status for GPIO(15:0) pins.
Page 116: Giuinttypl (Base Address + 0X090)
CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.9 GIUINTTYPL (base address + 0x090) Name INTT15 INTT14 INTT13 INTT12 INTT11 INTT10 INTT9 INTT8 After reset Name INTT7 INTT6 INTT5 INTT4 INTT3 INTT2 INTT1 INTT0 After reset Name Function 15:0 INTT(15:0) Interrupt request detection trigger 1: Edge 0: Level This register is used to set the trigger to detect an interrupt request for GPIO(15:0) pins.
Page 117: Giuinttyph (Base Address + 0X092)
CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.10 GIUINTTYPH (base address + 0x092) Name After reset Name INTT20 INTT19 INTT18 INTT17 INTT16 After reset Name Function 15:5 Reserved. Write 0 to these bits. 0 is returned after a read. INTT(20:16) Interrupt request detection trigger 1: Edge 0: Level This register is used to set the trigger to detect an interrupt request for GPIO(20:16) pins.
Page 118: Giuintalsell (Base Address + 0X094)
CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.11 GIUINTALSELL (base address + 0x094) Name INTL15 INTL14 INTL13 INTL12 INTL11 INTL10 INTL9 INTL8 After reset Name INTL7 INTL6 INTL5 INTL4 INTL3 INTL2 INTL1 INTL0 After reset Name Function 15:0 INTL(15:0) Interrupt request detection level 1: High active 0: Low active This register is used to set the active level when using the level detection method for interrupts to GPIO(15:0)
Page 119: Giuintalselh (Base Address + 0X096)
CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.12 GIUINTALSELH (base address + 0x096) Name After reset Name INTL20 INTL19 INTL18 INTL17 INTL16 After reset Name Function 15:5 Reserved. Write 0 to these bits. 0 is returned after a read. INTL(20:16) Interrupt request detection level 1: High active 0: Low active This register is used to set the active level when using the level detection method for interrupts to GPIO(20:16)
Page 120: Giuinthtsell (Base Address + 0X098)
CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.13 GIUINTHTSELL (base address + 0x098) Name INTH15 INTH14 INTH13 INTH12 INTH11 INTH10 INTH9 INTH8 After reset Name INTH7 INTH6 INTH5 INTH4 INTH3 INTH2 INTH1 INTH0 After reset Name Function 15:0 INTH(15:0) GPIO(15:0) pin interrupt signal hold/through 1: Hold 0: Through This register is used to set whether or not interrupt signals to the GPIO(15:0) pins should be held.
Page 121: Giuinthtselh (Base Address + 0X09A)
CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.14 GIUINTHTSELH (base address + 0x09A) Name After reset Name INTH20 INTH19 INTH18 INTH17 INTH16 After reset Name Function 15:5 Reserved. Write 0 to these bits. 0 is returned after a read. INTH(20:16) GPIO(20:16) pin interrupt signal hold/through 1: Hold 0: Through This register is used to set whether or not interrupt signals to the GPIO(20:16) pins should be held.
Page 122 CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) The relationship between settings of GPIO interrupts enable/disable and hold/through is shown in Table 8-3. Table 8-3. Correspondences Between Interrupt Mask and Interrupt Hold Interrupt Setting of Setting of GIUINTEN Hold in GIU Notation to ICU Trigger GIUINTHTSEL Register Register...
Page 123: Selectreg (Base Address + 0X09E)
CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.15 SELECTREG (base address + 0x09E) Name After reset Name SEL3 SEL2 SEL1 SEL0 After reset Name Function 15:4 Reserved. Write 0 to these bits. 0 is returned after a read. SEL3 Function selection of TPEN/GPIO20, TPY(1:0)/GPIO(19:18), TPX(1:0)/GPIO(17:16) pins 1: Used as GPIO(20:16) pins 0: Used as TPEN, TPY(1:0), TPX(1:0) pins...
Page 124 CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) Table 8-4. Alternate Function Correspondence Table of V 4173 4173 Pin GPIO PS2CH1 PS2CH2 − − − TPEN/GPIO20 GPIO20 TPEN − − − TPY1/GPIO19 GPIO19 TPY1 − − − TPY0/GPIO18 GPIO18 TPY0 − − −...
Page 125: Chapter 9 Piu (Touch Panel Interface Unit)
CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) General The PIU uses an on-chip A/D converter and detects the X and Y coordinates of pen contact locations on the touch panel and scans the general-purpose A/D input port. Since the touch panel control circuit and the A/D converter (conversion precision: 12 bits) are both on-chip, the touch panel is connected directly to the V 4173.
Page 126: Block Diagrams
CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.1.1 Block diagrams Figure 9-1. PIU Peripheral Block Diagram 4173 Digital I/O buffer Touch panel TPX0 TPX1 TPY0 TPY1 TPEN touchen A/D converter ADIN 10 k Ω AUDIOIN Analog input buffer Remark When Tr1 is ON, pull down the TPY1 signal. When Tr1 is OFF, leave the TPY1 signal open.
Page 127 CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) • Touch panel A set of four pins are located at the edges of the X-axis and Y-axis resistance layers, and the two layers have high resistance when there is no pen contact and low resistance when there is pen contact. The resistance between the two edges of the resistance layers is about 1 kΩ.
Page 128 CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) Figure 9-3. PIU Internal Block Diagram 4173 (internal) Internal bus Internal bus Scan sequencer controller PIU registers Touch panel Touch panel interface controller A/D converter General-purpose A/D port, Audio input port The PIU includes three blocks: an internal bus controller, a scan sequencer, and a touch panel interface controller. (1) Internal bus controller The internal bus controller controls the internal bus, the PIU registers, and interrupts and performs serial/parallel conversion of data from the A/D converter.
Page 129: Scan Sequencer State Transition
CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) Scan Sequencer State Transition Figure 9-4. Scan Sequencer State Transition Diagram Disable Reset = 1 PIUPWR = 0 PIUPWR = 1 PIUSEQEN = 0 ADPSSTART = 1 Interval PIUSEQEN = 1 & ADPortScan NextScan ADPSSTART = 1 &...
Page 130 CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) (4) CmdScan state When in this state, the A/D converter operates using various settings. Voltage data from one port only is fetched based on a combination of the touch panel I/O signal setting (TPX(1:0), TPY(1:0)) and the selection of an input port (ADX, ADY, AUDIOIN, ADIN) connected to the A/D converter.
Page 131: Register Set
CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) Register Set Table 9-1 lists the PIU registers. Table 9-1. PIU Registers Address Register Symbol Function BASE + 0x0A2 PIUCNTREG PIU Control register BASE + 0x0A4 PIUINTREG PIU Interrupt cause register BASE + 0x0A6 PIUSIVLREG PIU Data sampling interval register BASE + 0x0A8...
Page 132: Piucntreg (Base Address + 0X0A2)
CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.3.1 PIUCNTREG (base address + 0x0A2) (1/2) Name PENSTC PADSTATE2 PADSTATE1 PADSTATE0 PADAT PADAT STOP START After reset Name PADSCAN PADSCAN PADSCAN PIUMODE1 PIUMODE0 PIUSEQEN PIUPWR PADRST STOP START TYPE After reset Name Function 15:14 Reserved.
Page 133 CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) (2/2) Name Function PIUMODE(1:0) PIU mode setting 11: Reserved 10: Reserved 01: Operate A/D converter using any command 00: Sample coordinate data PIUSEQEN Scan sequencer operation enable 1: Enable 0: Disable PIUPWR PIU power mode setting 1: Set PIU output as active and change to standby mode 0: Set panel to touch detection state and shift to PIU operation stop enabled mode PADRST...
Page 134 CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) Table 9-2. PIUCNTREG Register Bit Manipulation and States PIUCNTREG Bit Scan Sequencer’s State Manipulation Disable Standby WaitPenTouch PenDataScan 0 → 1 − Note 1 PADRST Disable Disable Disable 0 → 1 × × PIUPWR Standby 1 →...
Page 135: Piuintreg (Base Address + 0X0A4)
CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.3.2 PIUINTREG (base address + 0x0A4) Name After reset Name PADCMD PADADP PADPAGE1 PADPAGE0 PADDLOST PENCHG INTR INTR INTER INTER INTR INTR After reset Name Function Valid page ID bit (older valid page) 1: Valid data older than page 1 buffer data is retained 0: Valid data older than page 0 buffer data is retained 14:7...
Page 136: Piusivlreg (Base Address + 0X0A6)
CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) Caution In the Suspend mode, the V 4173 retains the touch panel state. Therefore, if the Suspend mode has been entered while the touch panel is touched, the contact state may be mistakenly recognized as having changed, when the Fullspeed mode returns.
Page 137: Piustblreg (Base Address + 0X0A8)
CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.3.4 PIUSTBLREG (base address + 0x0A8) Name After reset Name STABLE5 STABLE4 STABLE3 STABLE2 STABLE1 STABLE0 After reset Name Function 15:6 Reserved. Write 0 to these bits. 0 is returned after a read. STABLE(5:0) Panel applied voltage stabilization standby time (PenDataScan, CmdScan state) A/D scan timeout time (ADPortScan state)
Page 138: Piucmdreg (Base Address + 0X0Aa)
CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.3.5 PIUCMDREG (base address + 0x0AA) Name STABLEON TPYEN1 TPYEN0 TPXEN1 TPXEN0 After reset Name TPYD1 TPYD0 TPXD1 TPXD0 ADCMD3 ADCMD2 ADCMD1 ADCMD0 After reset Name Function 15:13 Reserved. Write 0 to these bits. 0 is returned after a read. STABLEON Touch panel applied voltage stabilization time set during command scan (STABLE(5:0) area of PIUSTBLREG register) enable...
Page 139: Piuascnreg (Base Address + 0X0B0)
CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.3.6 PIUASCNREG (base address + 0x0B0) Name After reset Name TPPSCAN ADPS START After reset Name Function 15:2 Reserved. Write 0 to these bits. 0 is returned after a read. Port selection for ADPortScan TPPSCAN 1: Select ADX, ADY (for touch panel) as A/D port 0: Select ADIN (general-purpose) as A/D port and AUDIOIN as audio input port...
Page 140 CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) Table 9-3. PIUASCNREG Register Bit Manipulation and States PIUASCNREG Bit Scan Sequencer’s State Manipulation Disable Standby WaitPenTouch PenDataScan Note 0 → 1 × × × ADPSSTART ADPortScan 1 → 0 × × × Disable 0 →...
Page 141: Piuamskreg (Base Address + 0X0B2)
CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.3.7 PIUAMSKREG (base address + 0x0B2) Name After reset Name AUDINM ADINM ADYM ADXM After reset Name Function 15:8 Reserved. Write 0 to these bits. 0 is returned after a read. AUDINM Audio input port mask 1: Mask 0: Normal Reserved.
Page 142: Piucivlreg (Base Address + 0X0Be)
CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.3.8 PIUCIVLREG (base address + 0x0BE) Name CHECK CHECK CHECK INTVAL10 INTVAL9 INTVAL8 After reset Name CHECK CHECK CHECK CHECK CHECK CHECK CHECK CHECK INTVAL7 INTVAL6 INTVAL5 INTVAL4 INTVAL3 INTVAL2 INTVAL1 INTVAL0 After reset Name Function 15:11...
Page 143: Piupbnmreg (Base Address + 0X0C0 To Base Address + 0X0Ce, Base Address + 0X0Dc To Base Address + 0X0De)
CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.3.9 PIUPBnmREG (base address + 0x0C0 to base address + 0x0CE, base address + 0x0DC to base address + 0x0DE) Remark n = 0, 1, m = 0 to 4 PIUPB00REG (base address + 0x0C0) PIUPB10REG (base address + 0x0C8) PIUPB01REG...
Page 144: Piuabnreg (Base Address + 0X0D0 To Base Address + 0X0D2)
CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.3.10 PIUABnREG (base address + 0x0D0 to base address + 0x0D2) Remark n = 0, 1 PIUAB0REG (base address + 0x0D0) PIUAB1REG (base address + 0x0D2) Name VALID PADDATA11 PADDATA10 PADDATA9 PADDATA8 After reset Name PADDATA7 PADDATA6...
Page 145: Status Transfer Flow
CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) Status Transfer Flow Be sure to reset the PIU before operating the scan sequencer. Setting initial values via a reset sets particular values for the sequence interval, etc., that are required. The following registers require initial settings. SCANINTVAL(10:0) area in PIUSITVLREG register STABLE(5:0) area in PIUSTBLREG register Interrupt mask cancellation settings are required for registers other than the PIU registers.
Page 146 CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) (3) Transfer flow for manual scan coordinate detection Disable state <1> PIUCNTREG register PIUPWR = 1 ↓ Standby state <2> PIUCNTREG register PIUMODE(1:0) = 00 PADSCANSTART = 1 <3> PIUCNTREG register PIUSEQEN = 1 ↓...
Page 147 CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) (7) Transfer flow when returning from Suspend mode (Disable state) Disable state <1> PIUCNTREG register PIUPWR = 1 ↓ Standby state <2> PIUCNTREG register PIUMODE(1:0) = 00 PADATSTART = 1 PADATSTOP = 1 <3>...
Page 148: Relationships Among Tpx, Tpy, Adx, Ady, Tpen, Adin, And Audioin Pins And States
CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) Relationships Among TPX, TPY, ADX, ADY, TPEN, ADIN, and AUDIOIN Pins and States Table 9-7. Relationships Among TPX, TPY, ADX, ADY, TPEN, ADIN, and AUDIOIN Pins and States State PADSTATE(2:0) TPX1(ADX), TPY1(ADY), TPEN AUDIOIN, TPX0 TPY0...
Page 149: Timing
CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) Timing 9.6.1 Touch/release detection timing Touch/release detection does not use the A/D converter but instead uses the voltage level of the TPY1 pin to determine the panel’s touch/release state. The following figure shows a touch/release detection timing diagram. Figure 9-6.
Page 150: Data Lost Generation Conditions
CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) Data Lost Generation Conditions The PIU issues a data lost interrupt when any of the following four conditions exist. Data for one coordinate has not been obtained within the interval period The A/D port scan has not been completed within the time set via PIUSTBLREG register Transfer of the next coordinate data has begun while valid data for both pages remains in the buffer The next data transfer starts while there is valid data in the ADPortScan buffer Once a data lost interrupt occurs, the sequencer is forcibly changed to the Standby state.
Page 151 CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) (3) When transfer of the next coordinate data has begun while valid data for both pages remains in the buffer (a) Cause This condition is caused when the data buffer contains two pages of valid data (both the data buffer page 1 and data buffer page 0 interrupts have occurred) but the valid data has not been processed.
Page 152: Chapter 10 Aiu (Audio Interface Unit)
CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.1 General The AIU supports speaker output and MIC input. The settings related to A/D converter and D/A converter are also performed by AIU. The resolution of the D/A converter used for a speaker is 10 bits, and the resolution of the A/D converter used for a microphone is 12 bits.
Page 153: Mdmadatreg (Base Address + 0X0E0)
CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.2.1 MDMADATREG (base address + 0x0E0) Name MDMA11 MDMA10 MDMA9 MDMA8 After reset Name MDMA7 MDMA6 MDMA5 MDMA4 MDMA3 MDMA2 MDMA1 MDMA0 After reset Name Function 15:12 Reserved. Write 0 to these bits. 0 is returned after a read. 11:0 MDMA(11:0) MIC input DMA data...
Page 154: Sodatreg (Base Address + 0X0E6)
CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.2.3 SODATREG (base address + 0x0E6) Name SODAT9 SODAT8 After reset Name SODAT7 SODAT6 SODAT5 SODAT4 SODAT3 SODAT2 SODAT1 SODAT0 After reset Name Function 15:10 Reserved. Write 0 to these bits. 0 is returned after a read. SODAT(9:0) Speaker output data This register is used to store 10-bit data for speaker output.
Page 155: Scntreg (Base Address + 0X0E8)
CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.2.4 SCNTREG (base address + 0x0E8) Name DAENAIU After reset Name SSTATE SSTOPEN After reset Name Function DAENAIU This is the speaker D/A (DAAV connection) enable bit. 1: ON 0: OFF 14:4 Reserved. Write 0 to these bits. 0 is returned after a read. SSTATE Indicates speaker operation state 1: In operation...
Page 156: Scnvrreg (Base Address + 0X0Ea)
CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.2.5 SCNVRREG (base address + 0x0EA) Name After reset Name SCNVR2 SCNVR1 SCNVR0 After reset Name Function 15:3 Reserved. Write 0 to these bits. 0 is returned after a read. SCNVR(2:0) D/A conversion rate 111: Reserved 101: Reserved 100: 8 ksps...
Page 157: Midatreg (Base Address + 0X0F0)
CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.2.6 MIDATREG (base address + 0x0F0) Name MIDAT11 MIDAT10 MIDAT9 MIDAT8 After reset Name MIDAT7 MIDAT6 MIDAT5 MIDAT4 MIDAT3 MIDAT2 MIDAT1 MIDAT0 After reset Name Function 15:12 Reserved. Write 0 to these bits. 0 is returned after a read. 11:0 MIDAT(11:0) MIC input data...
Page 158: Mcntreg (Base Address + 0X0F2)
CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.2.7 MCNTREG (base address + 0x0F2) Name ADENAIU After reset Name MSTATE MSTOPEN ADREQAIU After reset Name Function ADENAIU This is the MIC A/D (ADAV P connection) enable bit. 1: ON 0: OFF 14:4 Reserved.
Page 159: Mcnvrreg (Base Address + 0X0F4)
CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.2.8 MCNVRREG (base address + 0x0F4) Name After reset Name MCNVR2 MCNVR1 MCNVR0 After reset Name Function 15:3 Reserved. Write 0 to these bits. 0 is returned after a read. MCNVR(2:0) A/D conversion rate 111: Reserved 101: Reserved 100: 8 ksps...
Page 160: Dvalidreg (Base Address + 0X0F8)
CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.2.9 DVALIDREG (base address + 0x0F8) Name After reset Name SODATV SDMAV MIDATV MDMAV After reset Name Function 15:4 Reserved. Write 0 to these bits. 0 is returned after a read. SODATV This indicates when valid data has been stored in SODATREG register. 1: Valid data exists 0: No valid data SDMAV...
Page 161: Seqreg (Base Address + 0X0Fa)
CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.2.10 SEQREG (base address + 0x0FA) Name AIURST After reset Note Note Name AIUMEN AIUSEN After reset Name Function AIURST AIU reset via software 1: Reset 0: Normal 14:5 Reserved. Write 0 to these bits. 0 is returned after a read. Note AIUMEN MIC block operation enable, DMA enable...
Page 162: Intreg (Base Address + 0X0Fc)
CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.2.11 INTREG (base address + 0x0FC) Name MENDINTR MINTR MIDLEINTR MSTINTR After reset Name SENDINTR SINTR SIDLEINTR After reset Name Function 15:12 Reserved. Write 0 to these bits. 0 is returned after a read. MIC DMA 2 page interrupt.
Page 163: Operation Sequence
CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.3 Operation Sequence 10.3.1 Output (Speaker) (1) When using DMA transfer <1> Set D/A conversion rate (SCNVR(2:0) area in SCNVRREG register = any value) <2> Set output data area to DMAAU <3> DMA enable in DCU <4>...
Page 164 CHAPTER 10 AIU (AUDIO INTERFACE UNIT) Figure 10-1. Speaker Output and AUDIOOUT Pin AUDIOOUT <1> <2> <3> <4> <5> <6> <7> <8><9> <10> <11> Time (2) When not using DMA transfer <1> Enable clock supply to AIU in CMU <2> Set D/A conversion rate (SCNVR(2:0) area in SCNVRREG register = any value) <3>...
Page 165: Input (Mic)
CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.3.2 Input (MIC) <1> Set A/D conversion rate (MCNVR(2:0) area in MCNVRREG register = any value) <2> Set input data area in DMAAU <3> DMA enable in DCU <4> Set A/D converter’s ADAV P to ON (ADENAIU bit of MCNTREG register = 1) MIC power can be set ON and MIC operation can be enabled (AIUMEN bit = 1) without waiting for P resistor stabilization time (about 5 µ...
Page 166: Chapter 11 Kiu (Keyboard Interface Unit)
CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) 11.1 General The KIU includes 12 scan lines and 8 detection lines. The number of key inputs to be detected can be selected from 96/80/64, by switching the number of scan lines from 12/10/8. The register can be set to enable the 12 scan lines to be used as a general-purpose I/O port or PS/2 interface signals.
Page 167: Kiudatn (Base Address + 0X100 To Base Address + 0X10A)
CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) 11.2.1 KIUDATn (base address + 0x100 to base address + 0x10A) Remark n = 0 to 5 KIUDAT0 (base address + 0x100) KIUDAT1 (base address + 0x102) KIUDAT2 (base address + 0x104) KIUDAT3 (base address + 0x106) KIUDAT4 (base address + 0x108) KIUDAT5 (base address + 0x10A) Name...
Page 168 CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) The data in the KIUDAT00 to KIUDAT05 registers should be read out in the interval time between two key scan operations. Scan interval is set by the KIUWKI register. When data is not read before the next key scan operation starts, the key scan data lost interrupt occurs (see 11.2.6).
Page 169: Kiuscanrep (Base Address + 0X110)
CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) 11.2.2 KIUSCANREP (base address + 0x110) Name KEYEN STPREP5 STPREP4 After reset Name STPREP3 STPREP2 STPREP1 STPREP0 SCANSTP SCANSTART ATSTP ATSCAN After reset Name Function KEYEN Key scan enable 1: Enable 0: Disable 14:10 Reserved.
Page 170 CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) • Key scan stop The SCANSTP bit should be set to 1 when the KIU sequencer stops the key scan operation in Scanning or IntervalNextScan mode. When this bit is set to 1, the key scan operation stops. However, if this bit is set to 1 during a key scan operation, the KIU sequencer stops after the current set of key data is received.
Page 171: Kiuscans (Base Address + 0X112)
CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) 11.2.3 KIUSCANS (base address + 0x112) Name After reset Name SSTAT1 SSTAT0 After reset Name Function 15:2 Reserved. Write 0 to these bits. 0 is returned after a read. SSTAT(1:0) KIU sequencer status 11: Scanning 10: IntervalNextScan 01: WaitKeyIn 00: Stopped...
Page 172 CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) • WaitKeyIn: This is the state of waiting for key input in the key auto scan mode. When the ATSCAN bit of the KIUSCANREP register is set to 1 and the KIU sequencer is enabled, key input is Note waited for.
Page 173: Kiuwks (Base Address + 0X114)
CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) 11.2.4 KIUWKS (base address + 0x114) Name T3CNT4 T3CNT3 T3CNT2 T3CNT1 T3CNT0 T2CNT4 T2CNT3 After reset Name T2CNT2 T2CNT1 T2CNT0 T1CNT4 T1CNT3 T1CNT2 T1CNT1 T1CNT0 After reset Name Function Reserved. Write 0 to this bit. 0 is returned after a read. Wait time setting ((T3CNT(4:0) + 1) ×...
Page 174 CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) Figure 11-2. KSCAN Signal Status and KPORT Signal Sampling Timing T1CNT T2CNT T3CNT Hi-Z Hi-Z KSCAN1 (output) Hi-Z Hi-Z KSCAN0 (output) Sampling timing KPORT(7:0) (input) User’s Manual U14579EJ2V0UM...
Page 175: Kiuwki (Base Address + 0X116)
CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) 11.2.5 KIUWKI (base address + 0x116) Name WINTVL9 WINTVL8 After reset Name WINTVL7 WINTVL6 WINTVL5 WINTVL4 WINTVL3 WINTVL2 WINTVL1 WINTVL0 After reset Name Function 15:10 Reserved. Write 0 to these bits. 0 is returned after a read. Key scan interval time setting (WINTVL(9:0) ×...
Page 176: Kiuint (Base Address + 0X118)
CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) 11.2.6 KIUINT (base address + 0x118) Name After reset Name KDATLOST KDATRDY SCANINT After reset Name Function 15:3 Reserved. Write 0 to these bits. 0 is returned after a read. KDATLOST Key scan data lost interrupt. Cleared to 0 when 1 is written. 1: Yes 0: No KDATRDY...
Page 177: Kiurst (Base Address + 0X11A)
CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) 11.2.7 KIURST (base address + 0x11A) Name After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Name KIURST After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Name Function 15:1 Reserved. Write 0 to these bits. The value is undefined after a read. KIURST KIU reset.
Page 178: Scanline (Base Address + 0X11E)
CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) 11.2.8 SCANLINE (base address + 0x11E) Name After reset Name LINE1 LINE0 After reset Name Function 15:2 Reserved. Write 0 to these bits. 0 is returned after a read. LINE(1:0) KSCAN pin use/do not use setting 11: Do not use KSCAN pins for key scan (All the KSCAN pins are used as general-purpose I/O ports or PS/2 ports) 10: Use eight key scan pins (KSCAN(7:0))
Page 179 CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) Figure 11-4. Transition of Sequencer Status Reset < Stopped > (software reset) (software reset) KEYEN: SCANSTP: Note 1 (KEYEN = 0) (KEYEN = 0) SCANSTART: ATSTP: ATSCAN: (set KEYEN = 0) Note 2 (set KEYEN = 1) (software reset) Note 3 <...
Page 180 Figure 11-5. Basic Operation Timing Chart (1/2) (a) Auto Start/Auto Stop KSCAN11 Setting the KIUWKS register KIUSCANREP register setting KSCAN10 • ATSTART = 1 According to the alternate function pin setting Setting the KIUWKI register • ATSTP = 1 KSCAN9 •...
Page 181 Figure 11-5. Basic Operation Timing Chart (2/2) (b) Key Scan Start/Key Scan Stop KSCAN11 Setting the KIUWKS register KSCAN10 SCANLINE register setting According to the alternate • LINE(1:0) = 10 Setting the KIUWKI register function pin setting KSCAN9 KSCAN8 KSCAN7 KSCAN6 KSCAN5 KSCAN4...
Page 182: Chapter 12 Ps2U (Ps/2 Unit)
CHAPTER 12 PS2U (PS/2 UNIT) 12.1 General The PS2U controls the PS/2 interface with two channels, PS2CH1 and PS2CH2. The PS/2 interface performs bidirectional data transfers by using the PS2CLK1n and PS2DATA1n signals (n = 1, 2). The PS2U pins are alternate function pins that are shared with the KIU pins. Use the SELECTREG register of the GIU (see 8.2.15) to select the functions of the alternate function pins.
Page 183: Ps2Chndata (Base Address + 0X120, Base Address + 0X140)
CHAPTER 12 PS2U (PS/2 UNIT) 12.2.1 PS2CHnDATA (base address + 0x120, base address + 0x140) Remark n = 1, 2 PS2CH1DATA (base address + 0x120) PS2CH2DATA (base address + 0x140) Name After reset Name PSDATA7 PSDATA6 PSDATA5 PSDATA4 PSDATA3 PSDATA2 PSDATA1 PSDATA0 After reset...
Page 184: Ps2Chnctrl (Base Address + 0X122, Base Address + 0X142)
CHAPTER 12 PS2U (PS/2 UNIT) 12.2.2 PS2CHnCTRL (base address + 0x122, base address + 0x142) Remark n = 1, 2 PS2CH1CTRL (base address + 0x122) PS2CH2CTRL (base address + 0x142) Name After reset Name PERR RVEN INTEN PS2EN TEMT REMT After reset Name Function...
Page 185: Ps2Chnrst (Base Address + 0X124, Base Address + 0X144)
CHAPTER 12 PS2U (PS/2 UNIT) The INTEN bit controls whether detection of reception completion interrupt requests is enabled or disabled. If the INTEN bit is 1, when the reception of one group of data from the PS2DATAn pins is completed, the REMT bit is set to 1 and an interrupt request is reported to the CPU at the same time (n = 1, 2).
Page 186: Transmission Procedure
CHAPTER 12 PS2U (PS/2 UNIT) 12.3 Transmission Procedure Use the following procedure to transmit data. <1> Set the PS2EN bit of the PS2CHnCTRL register to 1 to disable reception. <2> After waiting 100 µ s, confirm whether any reception data exists. <3>...
Page 187: Chapter 13 Cardu1, Cardu2 (Pc Card Units)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.1 General The V 4173, which has two on-chip PC card unit (CARDU) channels for controlling PC cards that are compliant with the 1997 PC Card Standard, supports a total of two card slots. Caution The CARDU of the V 4173 does not support a 32-bit PC card (CardBus card).
Page 188: Configuration Register Set
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2 Configuration Register Set Table 13-1 lists the configuration registers. CARDU1 and CARDU2 each have these registers. Table 13-1. CARDU Configuration Registers (1/2) Offset Address Register Symbol Function 0x00 to 0x01 Vendor ID register 0x02 to 0x03 Device ID register 0x04 to 0x05...
Page 189 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) Table 13-1. CARDU Configuration Registers (2/2) Offset Address Register Symbol Function 0x3C INTL Interrupt line register 0x3D INTP Interrupt pin register 0x3E to 0x3F BRGCNT Bridge control register 0x40 to 0x41 SUBVID Subsystem vendor ID register 0x42 to 0x43 SUBID Subsystem ID register...
Page 190: Vid (Offset Address: 0X00 To 0X01)
Name VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 After reset Name Function 15:0 VID(15:0) Vendor ID 0x1033: NEC 13.2.2 DID (offset address: 0x02 to 0x03) Name DID15 DID14 DID13 DID12 DID11 DID10 DID9 DID8 After reset Name DID7 DID6...
Page 191: Pcicmd (Offset Address: 0X04 To 0X05)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.3 PCICMD (offset address: 0x04 to 0x05) (1/2) Name FBTB_EN SERR_EN After reset Name AD_STEP PERR_EN VGA_P_ MEMW_ SP_CYC MASTER_ MEM_EN IO_EN SNOOP INV_EN After reset Name Function 15:10 Reserved. Write 0 to these bits. 0 is returned after a read. FBTB_EN Enables/disables fast Back to Back.
Page 192 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) (2/2) Name Function MASTER_EN Controls bus master operation. 1: Operate as bus master on the PCI bus. 0: Do not operate as bus master on the PCI bus. MEM_EN Controls memory space. 1: Respond to a memory access to the PC card. 0: Do not respond to a memory access to the PC card.
Page 193: Pcists (Offset Address: 0X06 To 0X07)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.4 PCISTS (offset address: 0x06 to 0x07) Name DETECT_ SIG_SERR SIG_ DEVSEL1 DEVSEL0 DETECT_ PERR MABORT TABORT TABOT D_PERR After reset Name FBTB_CAP NEW_CAP After reset Name Function DETECT_PERR Data and address parity error detection. Cleared to 0 when 1 is written. 1: Detected 0: Not detected SIG_SERR...
Page 194: Rid (Offset Address: 0X08)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.5 RID (offset address: 0x08) Name RID7 RID6 RID5 RID4 RID3 RID2 RID1 RID0 After reset Name Function RID(7:0) Revision ID 13.2.6 CLASSC (offset address: 0x09 to 0x0B) Name CLASSC23 CLASSC22 CLASSC21 CLASSC20 CLASSC19 CLASSC18 CLASSC17...
Page 195: Mlt (Offset Address: 0X0D)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.8 MLT (offset address: 0x0D) Name MLT7 MLT6 MLT5 MLT4 MLT3 MLT2 MLT1 MLT0 After reset Name Function MLT(7:3) Sets the latency timer. 11111: 38 PCLK (1140 ns) 00010: 9 PCLK (270 ns) 00001: 8 PCLK (240 ns) 00000: 0 PCLK (0 ns) MLT(2:0)
Page 196: Csrbadr (Offset Address: 0X10 To 0X13)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.11 CSRBADR (offset address: 0x10 to 0x13) Name CSRBADR31 CSRBADR30 CSRBADR29 CSRBADR28 CSRBADR27 CSRBADR26 CSRBADR25 CSRBADR24 After reset Name CSRBADR23 CSRBADR22 CSRBADR21 CSRBADR20 CSRBADR19 CSRBADR18 CSRBADR17 CSRBADR16 After reset Name CSRBADR15 CSRBADR14 CSRBADR13 CSRBADR12 CSRBADR11 CSRBADR10 CSRBADR9 CSRBADR8 After reset Name...
Page 197: Secsts (Offset Address: 0X16 To 0X17)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.13 SECSTS (offset address: 0x16 to 0x17) Name S_DETECT_ S_SIG_ S_RV_ S_RV_ S_SIG_ S_DEVSEL1 S_DEVSEL0 S_DETECT_ PERR SERR MABORT TABORT TABOT D_PERR After reset Name S_FBTB_ After reset Name Function S_DETECT_PERR Data and address parity error detection. Cleared to 0 when 1 is written. 1: Detected 0: Not detected S_SIG_SERR...
Page 198: Pcibnum (Offset Address: 0X18)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.14 PCIBNUM (offset address: 0x18) Name PCIBNUM7 PCIBNUM6 PCIBNUM5 PCIBNUM4 PCIBNUM3 PCIBNUM2 PCIBNUM1 PCIBNUM0 After reset Name Function PCIBNUM(7:0) PCI bus number The value of this register is set and managed by software. Caution The CARDU of the V 4173 does not support a 32-bit PC card (CardBus card).
Page 199: Clt (Offset Address: 0X1B)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.17 CLT (offset address: 0x1B) Name CLT7 CLT6 CLT5 CLT4 CLT3 CLT2 CLT1 CLT0 After reset Name Function CLT(7:3) Sets the CardBus latency timer. 11111: 38 PCLK (1140 ns) 00010: 9 PCLK (270 ns) 00001: 8 PCLK (240 ns) 00000: 0 PCLK (0 ns) CLT(2:0)
Page 200: Memb0 (Offset Address: 0X1C To 0X1F)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.18 MEMB0 (offset address: 0x1C to 0x1F) Name MEMB031 MEMB030 MEMB029 MEMB028 MEMB027 MEMB026 MEMB025 MEMB024 After reset Name MEMB023 MEMB022 MEMB021 MEMB020 MEMB019 MEMB018 MEMB017 MEMB016 After reset Name MEMB015 MEMB014 MEMB013 MEMB012 MEMB011 MEMB010...
Page 201: Meml0 (Offset Address: 0X20 To 0X23)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.19 MEML0 (offset address: 0x20 to 0x23) Name MEML031 MEML030 MEML029 MEML028 MEML027 MEML026 MEML025 MEML024 After reset Name MEML023 MEML022 MEML021 MEML020 MEML019 MEML018 MEML017 MEML016 After reset Name MEML015 MEML014 MEML013 MEML012 MEML011 MEML010...
Page 202: Memb1 (Offset Address: 0X24 To 0X27)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.20 MEMB1 (offset address: 0x24 to 0x27) Name MEMB131 MEMB130 MEMB129 MEMB128 MEMB127 MEMB126 MEMB125 MEMB124 After reset Name MEMB123 MEMB122 MEMB121 MEMB120 MEMB119 MEMB118 MEMB117 MEMB116 After reset Name MEMB115 MEMB114 MEMB113 MEMB112 MEMB111 MEMB110...
Page 203: Meml1 (Offset Address: 0X28 To 0X2B)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.21 MEML1 (offset address: 0x28 to 0x2B) Name MEML131 MEML130 MEML129 MEML128 MEML127 MEML126 MEML125 MEML124 After reset Name MEML123 MEML122 MEML121 MEML120 MEML119 MEML118 MEML117 MEML116 After reset Name MEML115 MEML114 MEML113 MEML112 MEML111 MEML110...
Page 204: Iob0 (Offset Address: 0X2C To 0X2F)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.22 IOB0 (offset address: 0x2C to 0x2F) Name IOB031 IOB030 IOB029 IOB028 IOB027 IOB026 IOB025 IOB024 After reset Name IOB023 IOB022 IOB021 IOB020 IOB019 IOB018 IOB017 IOB016 After reset Name IOB015 IOB014 IOB013 IOB012 IOB011 IOB010...
Page 205: Iol0 (Offset Address: 0X30 To 0X33)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.23 IOL0 (offset address: 0x30 to 0x33) Name IOL031 IOL030 IOL029 IOL028 IOL027 IOL026 IOL025 IOL024 After reset Name IOL023 IOL022 IOL021 IOL020 IOL019 IOL018 IOL017 IOL016 After reset Name IOL015 IOL014 IOL013 IOL012 IOL011 IOL010...
Page 206: Iob1 (Offset Address: 0X34 To 0X37)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.24 IOB1 (offset address: 0x34 to 0x37) Name IOB131 IOB130 IOB129 IOB128 IOB127 IOB126 IOB125 IOB124 After reset Name IOB123 IOB122 IOB121 IOB120 IOB119 IOB118 IOB117 IOB116 After reset Name IOB115 IOB114 IOB113 IOB112 IOB111 IOB110...
Page 207: Iol1 (Offset Address: 0X38 To 0X3B)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.25 IOL1 (offset address: 0x38 to 0x3B) Name IOL131 IOL130 IOL129 IOL128 IOL127 IOL126 IOL125 IOL124 After reset Name IOL123 IOL122 IOL121 IOL120 IOL119 IOL118 IOL117 IOL116 After reset Name IOL115 IOL114 IOL113 IOL112 IOL111 IOL110...
Page 208: Intp (Offset Address: 0X3D)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.27 INTP (offset address: 0x3D) Name INTP7 INTP6 INTP5 INTP4 INTP3 INTP2 INTP1 INTP0 After reset Name Function INTP(7:0) PCI interrupt pin 0x01: Serial 13.2.28 BRGCNT (offset address: 0x3E to 0x3F) (1/2) Name POST_ MEM1_ MEM0_...
Page 209 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) (2/2) Name Function MABORT_MODE Controls operation when a master abort occurs in the PCI bus and CardBus. 1: For a delayed transaction, return a target abort. For a post transaction, set the SERR# signal to active when the SERR_EN bit is 1. 0: When reading, return all 1’s.
Page 210: Subvid (Offset Address: 0X40 To 0X41)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.29 SUBVID (offset address: 0x40 to 0x41) Name SUBVID15 SUBVID14 SUBVID13 SUBVID12 SUBVID11 SUBVID10 SUBVID9 SUBVID8 After reset Name SUBVID7 SUBVID6 SUBVID5 SUBVID4 SUBVID3 SUBVID2 SUBVID1 SUBVID0 After reset Name Function 15:0 SUBVID(15:0) Subsystem vendor ID This is a vendor identification number to be used for recognizing the system or option card.
Page 211: Pc16Badr (Offset Address: 0X44 To 0X47)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.31 PC16BADR (offset address: 0x44 to 0x47) Name PC16BADR PC16BADR PC16BADR PC16BADR PC16BADR PC16BADR PC16BADR PC16BADR After reset Name PC16BADR PC16BADR PC16BADR PC16BADR PC16BADR PC16BADR PC16BADR PC16BADR After reset Name PC16BADR PC16BADR PC16BADR PC16BADR PC16BADR PC16BADR...
Page 212: Syscnt (Offset Address: 0X80 To 0X83)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.32 SYSCNT (offset address: 0x80 to 0x83) (1/2) Name After reset Name BAD_VCC_ PCPCI_EN REQ_DISB ASSIGN2 ASSIGN1 ASSIGN0 After reset Name After reset Name SUB_ID_ ASYN_ PCI_ WR_EN INT_MODE CLK_RIN After reset Name Function 31:22 Reserved.
Page 213: Devcnt (Offset Address: 0X91)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) (2/2) Name Function ASYN_INT_MODE Synchronous/asynchronous setting for interrupt request samples from the PC card. 1: Sample interrupt requests other than for card insertion/removal asynchronously relative to the clock 0: Sample interrupt requests synchronously with the clock PCI_CLK_RIN PCI bus clock run control setting 1: Drive the primary CLKRUN# signal so that the PCICLK driven by CPU does not stop...
Page 214: Skdma0 (Offset Address: 0X94 To 0X97)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.34 SKDMA0 (offset address: 0x94 to 0x97) Name After reset Name After reset Name After reset Name DMA_PIN_ DMA_PIN_ CONFIG1 CONFIG0 After reset Name Function 31:2 Reserved. Write 0 to these bits. 0 is returned after a read. DMA_PIN_CONFIG(1:0) DMA request signal allocation control Caution The CARDU of the V...
Page 215: Skdma1 (Offset Address: 0X98 To 0X9B)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.35 SKDMA1 (offset address: 0x98 to 0x9B) Name After reset Name After reset Name DMA_ DMA_ DMA_ DMA_ DMA_ DMA_ DMA_ DMA_ BADR11 BADR10 BADR9 BADR8 BADR7 BADR6 BADR5 BADR4 After reset Name DMA_ DMA_ DMA_...
Page 216: Chipcnt (Offset Address: 0X9C)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.36 CHIPCNT (offset address: 0x9C) Name S_PREF_ DISB After reset Name Function Reserved. Write 0 to these bits. 0 is returned after a read. S_PREF_DISB Enables/disables prefetch reads from CardBus. 1: Disable 0: Enable Reserved.
Page 217: Capid (Offset Address: 0Xa0)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.38 CAPID (offset address: 0xA0) Name CAPID7 CAPID6 CAPID5 CAPID4 CAPID3 CAPID2 CAPID1 CAPID0 After reset Name Function CAPID(7:0) Capability ID 0x01: Power management function 13.2.39 NIP (offset address: 0xA1) Name NIP7 NIP6 NIP5 NIP4 NIP3...
Page 218: Pmc (Offset Address: 0Xa2 To 0Xa3)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.40 PMC (offset address: 0xA2 to 0xA3) Name PME_ PME_ PME_ PME_ PME_ SUPPORT4 SUPPORT3 SUPPORT2 SUPPORT1 SUPPORT0 SUPPORT SUPPORT After reset Name AUX_PWR_ PME_CLK VERSION2 VERSION1 VERSION0 SOURCE After reset Name Function PME_SUPPORT4 Enables the PME# signal (internal signal) to be active during a D3Cold state.
Page 219: Pmcsr (Offset Address: 0Xa4 To 0Xa5)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.41 PMCSR (offset address: 0xA4 to 0xA5) Name PME_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ PME_EN STATUS SCALE1 SCALE0 SEL3 SEL2 SEL1 SEL0 After reset Name PWR_ PWR_ STATE1 STATE0 After reset Name Function PME_STATUS PME# signal (internal signal) status.
Page 220: Data (Offset Address: 0Xa7)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.43 DATA (offset address: 0xA7) Name DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 After reset Name Function DATA(7:0) Write 0 to these bits. 0 is returned after a read. The CARDU unit does not support this function.
Page 221: Exca Register Set
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3 ExCA Register Set There are two methods of accessing these registers. Each access method is explained below. (1) Access according to a memory access from the primary side When all of the following conditions are satisfied, the ExCA registers can be accessed according to a memory access from the primary side.
Page 222 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) Figure 13-3. ExCA Extended Registers ExCA registers ExCA registers 0x16 ExCA extended 0x2F EXT_DATA registers 0x00 0x2E EXT_INDX User’s Manual U14579EJ2V0UM...
Page 223 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) Tables 13-2 and 13-3 list the ExCA registers. CARDU1 and CARDU2 each have the following ExCA registers. Table 13-2. ExCA Registers (1/2) Offset Address Register Symbol Function ExCA 0x800 0x00 ID_REV ID/revision register 0x801 0x01 IF_STATUS...
Page 224 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) Table 13-2. ExCA Registers (2/2) Offset Address Register Symbol Function ExCA 0x81B 0x1B MEM_WIN1_EAH Memory window 1 end address higher byte register 0x81C 0x1C MEM_WIN1_OAL Memory window 1 offset address lower byte register 0x81D 0x1D MEM_WIN1_OAH...
Page 225 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) Table 13-3. ExCA Extended Registers Offset Address Register Symbol Function ExCA Extension 0x840 0x00 MEM_WIN0_SAU Memory window 0 start address higher byte register 0x841 0x01 MEM_WIN1_SAU Memory window 1 start address higher byte register 0x842 0x02 MEM_WIN2_SAU...
Page 226: Id_Rev (Pci Offset Address: 0X800, Exca Offset Address: 0X00)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.1 ID_REV (PCI offset address: 0x800, ExCA offset address: 0x00) Name IF_TYPE1 IF_TYPE0 After reset Name Function IF_TYPE(1:0) Interface type 10: Supports 16-bit card Reserved. Write 0 to these bits. 0 is returned after a read. User’s Manual U14579EJ2V0UM...
Page 227: If_Status (Pci Offset Address: 0X801, Exca Offset Address: 0X01)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.2 IF_STATUS (PCI offset address: 0x801, ExCA offset address: 0x01) Name CARD_ READY CARD_WP CARD_ CARD_ DETECT2 DETECT1 DETECT1 DETECT0 After reset Undefined Undefined Undefined Undefined Undefined Undefined Name Function Reserved. Write 0 to these bits. 0 is returned after a read. CARD_PWR Supply status of V and V...
Page 228: Pwr_Cnt (Pci Offset Address: 0X802, Exca Offset Address: 0X02)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.3 PWR_CNT (PCI offset address: 0x802, ExCA offset address: 0x02) Name CARD_ VCC1 VCC0 VPP1 VPP0 OUT_EN After reset Name Function CARD_OUT_EN Enables/disables output to a 16-bit card 1: Enable 0: Disable Reserved. Write 0 to these bits. 0 is returned after a read. VCC(1:0) Sets V power supply level...
Page 229: Int_Gen_Cnt (Pci Offset Address: 0X803, Exca Offset Address: 0X03)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.4 INT_GEN_CNT (PCI offset address: 0x803, ExCA offset address: 0x03) Name RING_IND_ CARD_ CARD_ FUC_INT_ FUC_INT_ FUC_INT_ FUC_INT_ REST0 TYPE ROOT3 ROOT2 ROOT1 ROOT0 After reset Name Function RING_IND_EN Enables/disables Ring Indicate 1: Enable 0: Disable The CARDU unit does not support the Ring Indicate function.
Page 230: Card_Sc (Pci Offset Address: 0X804, Exca Offset Address: 0X04)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.5 CARD_SC (PCI offset address: 0x804, ExCA offset address: 0x04) Name CARD_DT_ RDY_CHG BAT_WAR_ BAT_DEAD _ST_CHG After reset Name Function Reserved. Write 0 to these bits. 0 is returned after a read. CARD_DT_CHG Detects change in the CDn1# signal and CDn2# signal (n = 1, 2) 1: Change occurred 0: No change occurred...
Page 231: Card_Sci (Pci Offset Address: 0X805, Exca Offset Address: 0X05)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.6 CARD_SCI (PCI offset address: 0x805, ExCA offset address: 0x05) Name CSC_INT_ CSC_INT_ CSC_INT_ CSC_INT_ CARD_DT_ RDY_EN BAT_WAR_ BAT_DEAD_ ROOT3 ROOT2 ROOT1 ROOT0 After reset Name Function CSC_INT_ROOT(3:0) Status interrupt request routing 1111: IRQ15 1110: IRQ14 Note 1101: IRQ13...
Page 232: Adr_Win_En (Pci Offset Address: 0X806, Exca Offset Address: 0X06)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.7 ADR_WIN_EN (PCI offset address: 0x806, ExCA offset address: 0x06) Name IO_WIN1_ IO_WIN0_ MEM_WIN4 MEM_WIN3 MEM_WIN2 MEM_WIN1 MEM_WIN0 After reset Name Function IO_WIN1_EN Enables/disables I/O window 1 access. 1: Enable 0: Disable IO_WIN0_EN Enables/disables I/O window 0 access.
Page 233: Io_Win_Cnt (Pci Offset Address: 0X807, Exca Offset Address: 0X07)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.8 IO_WIN_CNT (PCI offset address: 0x807, ExCA offset address: 0x07) Name IO_WIN1_ IO_WIN1_ IO_WIN0_ IO_WIN0_ DATA_SEL DATA_SIZE DATA_SEL DATA_SIZE After reset Name Function Reserved. Write 0 to these bits. 0 is returned after a read. IO_WIN1_DATA_SEL Determines the I/O window 1 data size 1: IOIS16# signal (corresponds to WP1 or WP2 signal of the V...
Page 234: Io_Win0_Sah (Pci Offset Address: 0X809, Exca Offset Address: 0X09)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.10 IO_WIN0_SAH (PCI offset address: 0x809, ExCA offset address: 0x09) Name IO_WIN0_ IO_WIN0_ IO_WIN0_ IO_WIN0_ IO_WIN0_ IO_WIN0_ IO_WIN0_ IO_WIN0_ SAH7 SAH6 SAH5 SAH4 SAH3 SAH2 SAH1 SAH0 After reset Name Function IO_WIN0_SAH(7:0) Sets the I/O window 0 start address higher byte 13.3.11 IO_WIN0_EAL (PCI offset address: 0x80A, ExCA offset address: 0x0A) Name IO_WIN0_...
Page 235: Io_Win1_Sal (Pci Offset Address: 0X80C, Exca Offset Address: 0X0C)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.13 IO_WIN1_SAL (PCI offset address: 0x80C, ExCA offset address: 0x0C) Name IO_WIN1_ IO_WIN1_ IO_WIN1_ IO_WIN1_ IO_WIN1_ IO_WIN1_ IO_WIN1_ IO_WIN1_ SAL7 SAL6 SAL5 SAL4 SAL3 SAL2 SAL1 SAL0 After reset Name Function IO_WIN1_SAL(7:0) Sets the I/O window 1 start address lower byte 13.3.14 IO_WIN1_SAH (PCI offset address: 0x80D, ExCA offset address: 0x0D) Name IO_WIN1_...
Page 236: Io_Win1_Eah (Pci Offset Address: 0X80F, Exca Offset Address: 0X0F)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.16 IO_WIN1_EAH (PCI offset address: 0x80F, ExCA offset address: 0x0F) Name IO_WIN1_ IO_WIN1_ IO_WIN1_ IO_WIN1_ IO_WIN1_ IO_WIN1_ IO_WIN1_ IO_WIN1_ EAH7 EAH6 EAH5 EAH4 EAH3 EAH2 EAH1 EAH0 After reset Name Function IO_WIN1_EAH(7:0) Sets the I/O window 1 end address higher byte 13.3.17 MEM_WIN0_SAL (PCI offset address: 0x810, ExCA offset address: 0x10) Name MEM_...
Page 237: Mem_Win0_Eal (Pci Offset Address: 0X812, Exca Offset Address: 0X12)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.19 MEM_WIN0_EAL (PCI offset address: 0x812, ExCA offset address: 0x12) Name MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ WIN0_EAL7 WIN0_EAL6 WIN0_EAL5 WIN0_EAL4 WIN0_EAL3 WIN0_EAL2 WIN0_EAL1 WIN0_EAL0 After reset Name Function MEM_WIN0_EAL(7:0) Sets the memory window 0 end address lower byte 13.3.20 MEM_WIN0_EAH (PCI offset address: 0x813, ExCA offset address: 0x13) Name MEM_...
Page 238: Mem_Win0_Oah (Pci Offset Address: 0X815, Exca Offset Address: 0X15)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.22 MEM_WIN0_OAH (PCI offset address: 0x815, ExCA offset address: 0x15) Name MEM_ MEM_WIN0 MEM_WIN0 MEM_WIN0 MEM_WIN0 MEM_WIN0 MEM_WIN0 MEM_WIN0 WIN0_WP _REGSET _OAH5 _OAH4 _OAH3 _OAH2 _OAH1 _OAH0 After reset Name Function MEM_WIN0_WP Enables/disables the memory window 0 write protect setting 1: Enable 0: Disable MEM_WIN0_REGSET...
Page 239: Mem_Win1_Sal (Pci Offset Address: 0X818, Exca Offset Address: 0X18)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.24 MEM_WIN1_SAL (PCI offset address: 0x818, ExCA offset address: 0x18) Name MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ WIN1_SAL7 WIN1_SAL6 WIN1_SAL5 WIN1_SAL4 WIN1_SAL3 WIN1_SAL2 WIN1_SAL1 WIN1_SAL0 After reset Name Function MEM_WIN1_SAL(7:0) Sets the memory window 1 start address lower byte 13.3.25 MEM_WIN1_SAH (PCI offset address: 0x819, ExCA offset address: 0x19) Name MEM_WIN1...
Page 240: Mem_Win1_Eah (Pci Offset Address: 0X81B, Exca Offset Address: 0X1B)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.27 MEM_WIN1_EAH (PCI offset address: 0x81B, ExCA offset address: 0x1B) Name MEM_ MEM_ MEM_ MEM_ WIN1_EAH3 WIN1_EAH2 WIN1_EAH1 WIN1_EAH0 After reset Name Function Reserved. Write 0 to these bits. 0 is returned after a read. MEM_WIN1_EAH(3:0) Sets the memory window 1 end address higher bits (A(23:20)) 13.3.28 MEM_WIN1_OAL (PCI offset address: 0x81C, ExCA offset address: 0x1C)
Page 241: Glo_Cnt (Pci Offset Address: 0X81E, Exca Offset Address: 0X1E)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.30 GLO_CNT (PCI offset address: 0x81E, ExCA offset address: 0x1E) Name FUN_INT_ INT_WB_ CSC_INT_ After reset Name Function Reserved. Write 0 to these bits. 0 is returned after a read. FUN_INT_LEV Sets the trigger for function interrupt requests to the host 1: Level mode 0: Edge mode Since the CARDU unit only supports parallel mode for PCI interrupts, this bit setting...
Page 242: Mem_Win2_Sah (Pci Offset Address: 0X821, Exca Offset Address: 0X21)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.32 MEM_WIN2_SAH (PCI offset address: 0x821, ExCA offset address: 0x21) Name MEM_WIN2 MEM_ MEM_ MEM_ MEM_ _DSIZE WIN2_SAH3 WIN2_SAH2 WIN2_SAH1 WIN2_SAH0 After reset Name Function MEM_WIN2_DSIZE Sets the memory window 2 data size 1: 16 bits 0: 8 bits Reserved.
Page 243: Mem_Win2_Oal (Pci Offset Address: 0X824, Exca Offset Address: 0X24)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.35 MEM_WIN2_OAL (PCI offset address: 0x824, ExCA offset address: 0x24) Name MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ WIN2_OAL7 WIN2_OAL6 WIN2_OAL5 WIN2_OAL4 WIN2_OAL3 WIN2_OAL2 WIN2_OAL1 WIN2_OAL0 After reset Name Function MEM_WIN2_OAL(7:0) Sets the memory window 2 offset address lower byte 13.3.36 MEM_WIN2_OAH (PCI offset address: 0x825, ExCA offset address: 0x25) Name MEM_...
Page 244: Mem_Win3_Sah (Pci Offset Address: 0X829, Exca Offset Address: 0X29)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.38 MEM_WIN3_SAH (PCI offset address: 0x829, ExCA offset address: 0x29) Name MEM_WIN3 MEM_WIN3 MEM_WIN3 MEM_WIN3 MEM_WIN3 _DSIZE _SAH3 _SAH2 _SAH1 _SAH0 After reset Name Function MEM_WIN3_DSIZE Sets the memory window 3 data size 1: 16 bits 0: 8 bits Reserved.
Page 245: Mem_Win3_Oal (Pci Offset Address: 0X82C, Exca Offset Address: 0X2C)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.41 MEM_WIN3_OAL (PCI offset address: 0x82C, ExCA offset address: 0x2C) Name MEM_WIN3 MEM_WIN3 MEM_WIN3 MEM_WIN3 MEM_WIN3 MEM_WIN3 MEM_WIN3 MEM_WIN3 _OAL7 _OAL6 _OAL5 _OAL4 _OAL3 _OAL2 _OAL1 _OAL0 After reset Name Function MEM_WIN3_OAL(7:0) Sets the memory window 3 offset address lower byte 13.3.42 MEM_WIN3_OAH (PCI offset address: 0x82D, ExCA offset address: 0x2D) Name MEM_WIN3...
Page 246: Ext_Data (Exca Offset Address: 0X2F)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.44 EXT_DATA (ExCA offset address: 0x2F) Name EXT_DATA7 EXT_DATA6 EXT_DATA5 EXT_DATA4 EXT_DATA3 EXT_DATA2 EXT_DATA1 EXT_DATA0 After reset Name Function EXT_DATA(7:0) Sets the extended data Caution Read/write according to a memory access from the primary side is not supported. 13.3.45 MEM_WIN4_SAL (PCI offset address: 0x830, ExCA offset address: 0x30) Name MEM_WIN4...
Page 247: Mem_Win4_Eal (Pci Offset Address: 0X832, Exca Offset Address: 0X32)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.47 MEM_WIN4_EAL (PCI offset address: 0x832, ExCA offset address: 0x32) Name MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ WIN4_EAL7 WIN4_EAL6 WIN4_EAL5 WIN4_EAL4 WIN4_EAL3 WIN4_EAL2 WIN4_EAL1 WIN4_EAL0 After reset Name Function MEM_WIN4_EAL(7:0) Sets the memory window 4 end address lower byte 13.3.48 MEM_WIN4_EAH (PCI offset address: 0x833, ExCA offset address: 0x33) Name MEM_...
Page 248: Mem_Win4_Oah (Pci Offset Address: 0X835, Exca Offset Address: 0X35)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.50 MEM_WIN4_OAH (PCI offset address: 0x835, ExCA offset address: 0x35) Name MEM_ MEM_WIN4 MEM_WIN4 MEM_WIN4 MEM_WIN4 MEM_WIN4 MEM_WIN4 MEM_WIN4 WIN4_WP _REGSET _OAH5 _OAH4 _OAH3 _OAH2 _OAH1 _OAH0 After reset Name Function MEM_WIN4_WP Enables/disables the memory window 4 write protect setting 1: Enable 0: Disable MEM_WIN4_REGSET...
Page 249: Io_Win1_Oal (Pci Offset Address: 0X838, Exca Offset Address: 0X38)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.53 IO_WIN1_OAL (PCI offset address: 0x838, ExCA offset address: 0x38) Name IO_WIN1_ IO_WIN1_ IO_WIN1_ IO_WIN1_ IO_WIN1_ IO_WIN1_ IO_WIN1_ IO_WIN1_ OAL7 OAL6 OAL5 OAL4 OAL3 OAL2 OAL1 OAL0 After reset Name Function IO_WIN1_OAL(7:0) Sets the I/O window 1 offset address lower bytes (A(7:0)) 13.3.54 IO_WIN1_OAH (PCI offset address: 0x839, ExCA offset address: 0x39) Name IO_WIN1_...
Page 250: Mem_Win1_Sau (Pci Offset Address: 0X841, Exca Extended Offset Address: 0X01)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.56 MEM_WIN1_SAU (PCI offset address: 0x841, ExCA extended offset address: 0x01) Name MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ WIN1_SAU7 WIN1_SAU6 WIN1_SAU5 WIN1_SAU4 WIN1_SAU3 WIN1_SAU2 WIN1_SAU1 WIN1_SAU0 After reset Name Function MEM_WIN1_SAU(7:0) Sets the memory window 1 start address higher bytes (A(31:24)) 13.3.57 MEM_WIN2_SAU (PCI offset address: 0x842, ExCA extended offset address: 0x02) Name...
Page 251: Mem_Win4_Sau (Pci Offset Address: 0X844, Exca Extended Offset Address: 0X04)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.59 MEM_WIN4_SAU (PCI offset address: 0x844, ExCA extended offset address: 0x04) Name MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ WIN4_SAU7 WIN4_SAU6 WIN4_SAU5 WIN4_SAU4 WIN4_SAU3 WIN4_SAU2 WIN4_SAU1 WIN4_SAU0 After reset Name Function MEM_WIN4_SAU(7:0) Sets the memory window 4 start address higher bytes (A(31:24)) 13.3.60 IO_SETUP_TIM (PCI offset address: 0x880, ExCA extended offset address: 0x05) Name...
Page 252: Io_Cmd_Tim (Pci Offset Address: 0X881, Exca Extended Offset Address: 0X06)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.61 IO_CMD_TIM (PCI offset address: 0x881, ExCA extended offset address: 0x06) Name IO_CMD_ IO_CMD_ IO_CMD_ IO_CMD_ IO_CMD_ IO_CMD_ IO_CMD_ IO_CMD_ TIM7 TIM6 TIM5 TIM4 TIM3 TIM2 TIM1 TIM0 After reset Name Function IO_CMD_TIM(7:0) Sets the I/O window command timing 0xFF: 256 clock pulses (7680 ns) 0xFE: 255 clock pulses (7650 ns)
Page 253: Mem0_Setup_Tim (Pci Offset Address: 0X884, Exca Extended Offset Address: 0X09)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.63 MEM0_SETUP_TIM (PCI offset address: 0x884, ExCA extended offset address: 0x09) Name MEM0_SET MEM0_SET MEM0_SET MEM0_SET MEM0_SET MEM0_SET MEM0_SET MEM0_SET UP_TIM7 UP_TIM6 UP_TIM5 UP_TIM4 UP_TIM3 UP_TIM2 UP_TIM1 UP_TIM0 After reset Name Function MEM0_SETUP_TIM(7:0) Sets the memory window setup timing 0 0xFF: 256 clock pulses (7680 ns) 0xFE: 255 clock pulses (7650 ns)
Page 254: Mem0_Hold_Tim (Pci Offset Address: 0X886, Exca Extended Offset Address: 0X0B)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.65 MEM0_HOLD_TIM (PCI offset address: 0x886, ExCA extended offset address: 0x0B) Name MEM0_ MEM0_ MEM0_ MEM0_ MEM0_ MEM0_ MEM0_ MEM0_ HOLD_TIM7 HOLD_TIM6 HOLD_TIM5 HOLD_TIM4 HOLD_TIM3 HOLD_TIM2 HOLD_TIM1 HOLD_TIM0 After reset Name Function MEM0_HOLD_TIM(7:0) Sets the memory window hold timing 0 0xFF: 256 clock pulses (7680 ns) 0xFE: 255 clock pulses (7650 ns)
Page 255: Mem1_Cmd_Tim (Pci Offset Address: 0X889, Exca Extended Offset Address: 0X0E)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.67 MEM1_CMD_TIM (PCI offset address: 0x889, ExCA extended offset address: 0x0E) Name MEM1_ MEM1_ MEM1_ MEM1_ MEM1_ MEM1_ MEM1_ MEM1_ CMD_TIM7 CMD_TIM6 CMD_TIM5 CMD_TIM4 CMD_TIM3 CMD_TIM2 CMD_TIM1 CMD_TIM0 After reset Name Function MEM1_CMD_TIM(7:0) Sets the memory window command timing 1 0xFF: 256 clock pulses (7680 ns) 0xFE: 255 clock pulses (7650 ns)
Page 256: Mem_Tim_Sel1 (Pci Offset Address: 0X88C, Exca Extended Offset Address: 0X11)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.69 MEM_TIM_SEL1 (PCI offset address: 0x88C, ExCA extended offset address: 0x11) Name MEM_WIN3 MEM_WIN3 MEM_WIN2 MEM_WIN2 MEM_WIN1 MEM_WIN1 MEM_WIN0 MEM_WIN0 _TIMSEL1 _TIMSEL0 _TIMSEL1 _TIMSEL0 _TIMSEL1 _TIMSEL0 _TIMSEL1 _TIMSEL0 After reset Name Function MEM_WIN3_TIMSEL(1:0) Selects the memory window 3 timing 00: Timing 0 Other: Timing 1...
Page 257: Mem_Win_Pwen (Pci Offset Address: 0X891, Exca Extended Offset Address: 0X16)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.71 MEM_WIN_PWEN (PCI offset address: 0x891, ExCA extended offset address: 0x16) Name POSTWEN After reset Name Function Reserved. Write 0 to these bits. 0 is returned after a read. POSTWEN Enables/disables the memory window post write cycle 1: Enable 0: Disable Caution The setting of POSTWEN bit is common for all windows.
Page 258: Cardbus Socket Register Set
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.4 CardBus Socket Register Set When all of the following conditions are satisfied, the CardBus socket registers can be accessed according to a memory access from the primary side. • The higher 20 bits of the address match the higher 20 bits of the CSRBADR register. •...
Page 259: Skt_Ev (Offset Address: 0X000)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.4.1 SKT_EV (offset address: 0x000) (1/2) Name After reset Name After reset Name After reset Name POW_ CCD2_EV CCD1_EV CSTSCHG_ CYC_EV After reset Name Function 31:4 Reserved. Write 0 to these bits. 0 is returned after a read. POW_CYC_EV Whether or not a change to 1 is to be detected in the POW_UP bit of the SKT_PRE_STATE register.
Page 260 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) (2/2) Name Function • For a 16-bit memory card CSTSCHG_EV Whether or not a change to 0 is to be detected in the BVD1 signal (corresponds to the BVD11# or BVD21# signal of the V 4173) or BVD2 signal (corresponds to the BVD12# or BVD22# signal of the V 4173) and a change to 1 is to be detected in...
Page 261: Skt_Mask (Offset Address: 0X004)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.4.2 SKT_MASK (offset address: 0x004) Name After reset Name After reset Name After reset Name POW_ CCD_MSK1 CCD_MSK0 CSC_MSK CYC_MSK After reset Name Function 31:4 Reserved. Write 0 to these bits. 0 is returned after a read. POW_CYC_MSK Controls interrupt requests according to the POW_CYC_EN bit of the SKT_EV register...
Page 262: Skt_Pre_State (Offset Address: 0X008)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.4.3 SKT_PRE_STATE (offset address: 0x008) (1/2) Name YV_SKT XV_SKT 3V_SKT 5V_SKT After reset Name After reset Name YV_CARD_ XV_CARD_ 3V_CARD_ 5V_CARD_ BAD_VCC_ DATA_ LOST After reset Note Name NOT_A_ READY CB_CARD_ R2_CARD_ POW_UP CCD20 CCD10 CSTSCHG...
Page 263 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) (2/2) Name Function 3V_CARD_DT Detects a 3 V card 1: Detect a card that is operating at 3 V 0: Detect a card that is not operating at 3 V 5V_CARD_DT Detects a 5 V card 1: Detect a card that is operating at 5 V 0: Detect a card that is not operating at 5 V BAD_VCC_REQ...
Page 264: Skt_Force_Ev (Offset Address: 0X00C)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.4.4 SKT_FORCE_EV (offset address: 0x00C) (1/2) Name After reset Name After reset Name CVS_TEST YV_CARD XV_CARD 3V_CARD 5V_CARD BAD_VCC_ DATA_LOST After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Name NOT_A_ CB_CARD R2_CARD POW_UP CCD20 CCD10...
Page 265 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) (2/2) Name Function CB_CARD The value written to this bit becomes the value of the CB_CARD_DT bit of the SKT_PRE_STATE register. However, the value is ignored if there is a card. R2_CARD The value written to this bit becomes the value of the R2_CARD_DT bit of the SKT_PRE_STATE register.
Page 266: Skt_Cnt (Offset Address: 0X010)
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.4.5 SKT_CNT (offset address: 0x010) (1/2) Name After reset Name After reset Name After reset Name STP_CLK_ VCC_CNT2 VCC_CNT1 VCC_CNT0 VPP_CNT2 VPP_CNT1 VPP_CNT0 After reset Name Function 31:8 Reserved. Write 0 to these bits. 0 is returned after a read. STP_CLK_EN Enables/disables clock stopping according to the clock run protocol 1: Enable...
Page 267 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) (2/2) Name Function VPP_CNT(2:0) Controls the V power supply 111: Reserved 110: Reserved 101: V = Y.Y V 100: V = X.X V 011: V = 3.3 V 010: V = 5 V 001: V = 12 V 000: V...
Page 268: Pc Card Unit Operation
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.5 PC Card Unit Operation This section provides supplementary information about PC card unit operation. 13.5.1 16-bit PC card support Each CARDU unit has five memory windows and two I/O windows for 16-bit PC cards. (1) Memory window Memory mapping can map from the 4 GB address space of a PCI system to the 64 MB address space within a card.
Page 269 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) (2) I/O window I/O mapping can map from the first 64 KB address space of the 4 GB address space of a PCI system to the 64 KB address space within a card. The size of each I/O window is 2 KB to 64 KB. Table 13-6 shows the registers related to I/O windows.
Page 270: Interrupts
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.5.2 Interrupts Status interrupt requests of a PC card unit and function interrupt requests from a PC card are reported to the host by using PCI interrupts (parallel). Table 13-7 shows the sources of interrupts and their masking methods. Table 13-7.
Page 271: Power Supply Interface
CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.5.3 Power supply interface The PC card unit has three serial signals, which are compatible with TI’s TPS2202A, for controlling the socket power supplies (V and V ). The VCC_CNT(2:0) and VPP_CNT(2:0) areas of the SKT_CNT register within the CardBus socket registers are monitored, and when there is a change in their values, the power supply control circuit operates and outputs serial signals (PWCDATA, PWCCLK, PWCLATCH).
Page 272 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) Table 13-10. CARDU2 (Slot 2) V Settings VPP_CNT(2:0) PWCDATA Request Voltage (V) Supply Voltage (V) Bit 4 Bit 5 (slot 2) (slot 2) Hi-Z Hi-Z − Hi-Z − Hi-Z Remark Hi-Z: High impedance Table 13-11.
Page 273 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) Figure 13-5. Power Supply Control Serial Signal (PWCDATA, PWCCLK, PWCLATCH) Timing (a) Register setting → → → → PWCCLK output PCLK (input) VPP_CNT, VCC_CNT Change in CARDU1 setting PWCCLK (output) (b) Register data latch → → → → PWCDATA output 36PCLK CARDU1 can be set CARDU2_clk...
Page 274: Chapter 14 Usbu (Universal Serial Bus Unit)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) The USBU of the V 4173, which is a USB host controller, is compliant with OPEN HCI Specification Release 1.0. The USBU supports power management functions such as PCI/USB-side clock stopping functions. It is also equipped with two downstream ports.
Page 275: Usb Host Control Configuration Registers
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.2 USB Host Control Configuration Registers To set the hardware resources to be used by a device, the device characteristics, and device operations, the PCI local bus (internal PCI bus of the V 4173) accesses the USB host control configuration registers.
Page 276: Register Set
Table 14-1. USB Host Control Configuration Registers Offset Register Name Bits Reset Value Contents Address 0x00 Vendor ID register 15:0 0x1033 Vendor ID (NEC) 0x02 Device ID register 31:16 0x0035 Device ID of this macro (USBU) 0x04 Command register 15:0 0x0000 See 14.2.2.
Page 277: Command Register (Offset Address: 0X04)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.2.2 Command register (offset address: 0x04) Name Fast back- SERR# to-back enable enable After reset Name Wait cycle Parity Error Memory Special Memory I/O space control response palette write and Cycles Master space snoop Invalidate enable...
Page 278: Status Register (Offset Address: 0X06)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.2.3 Status register (offset address: 0x06) Name Detected Signaled Received Received Signal DEVSEL DEVSEL Data Parity parity error system master target target timing timing Error error abort abort abort detected After reset Name Fast back- 66 MHz to-back...
Page 279: Base Address Register (Offset Address: 0X10)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.2.4 Base address register (offset address: 0x10) Name Base Base Base Base Base Base Base Base address address address address address address address address (MSB) (MSB) (MSB) (MSB) (MSB) (MSB) (MSB) (MSB) After reset Name Base Base...
Page 280: Power Management Register (Offset Address: 0Xe0)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.2.5 Power management register (offset address: 0xE0) (1/2) Name After reset Name Wakeup_ Enable After reset Name Wakeup_ Status After reset Name ID Write PC_mode REQ_ Status Power Power Mask Enable Change Status Status Standby After reset...
Page 281 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (2/2) Name Function REQ_Enable Controls REQ# signal output timing. 1: PCICLK (internal clock) asynchronous output 0: PCICLK synchronous output Reserved. Write 0 to these bits. 0 is returned after a read. Status Change Standby Device status relative to power status transition control.
Page 282: Operational Registers
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3 Operational Registers The USBU (USB host controller, HC) has on-chip operational registers, which are windows for communicating with the host CPU. These registers, which are mapped to a 4 KB range of the system’s 4 GB main memory space, are used by the host controller driver (HCD).
Page 283: Hcrevision (Offset Address: 0X00)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.2 HcRevision (offset address: 0x00) Name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Name...
Page 284: Hccontrol (Offset Address: 0X04)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.3 HcControl (offset address: 0x04) (1/2) Name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined...
Page 285 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (2/2) Name Function Interrupt Routing Route of interrupt request generated due to an event registered in the HcInterruptStatus register 1: SMI# signal (internal signal) output 0: USBINT# signal (internal signal) output HCFS Host Controller Functional Status for USB USB operation mode 11: UsbSuspend 10: UsbOperational...
Page 286: Hccommandstatus (Offset Address: 0X08)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.4 HcCommandStatus (offset address: 0x08) (1/2) Name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Name R/W (HCD)
Page 287 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (2/2) Name Function Control List Filled Whether or not a TD exists within the control list. 1: Exists 0: Does not exist Host Controller Reset HC software reset Set (1) by the HCD and cleared (0) by the HC. User’s Manual U14579EJ2V0UM...
Page 288: Hcinterruptstatus (Offset Address: 0X0C)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.5 HcInterruptStatus (offset address: 0x0C) (1/2) Name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Name R/W (HCD)
Page 289 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (2/2) Name Function Unrecoverable Error Detection of system error not related to the USB 1: Detected 0: Normal Resume Detected Detection of resume signal 1: Detected 0: Normal Start of Frame This bit is set at the start of a frame. This bit is cleared (0) when 0 is written. Writeback Done Head This bit is set (1) when the contents of the HcDoneHead register are written to the Note...
Page 290: Hcinterruptenable (Offset Address: 0X10)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.6 HcInterruptEnable (offset address: 0x10) (1/2) Name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Name R/W (HCD)
Page 291 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (2/2) Name Function Frame Number Overflow Interrupt request due to Frame Number Overflow 1: Enable 0: Disable Unrecoverable Error Interrupt request due to Unrecoverable Error 1: Enable 0: Disable Resume Detected Interrupt request due to Resume Detected 1: Enable 0: Disable Start of Frame...
Page 292: Hcinterruptdisable (Offset Address: 0X14)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.7 HcInterruptDisable (offset address: 0x14) (1/2) Name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Name R/W (HCD)
Page 293 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (2/2) Name Function Unrecoverable Error Interrupt request due to Unrecoverable Error 1: Disable Resume Detected Interrupt request due to Resume Detected 1: Disable Start of Frame Interrupt request due to Start of Frame 1: Disable Writeback Done Head Interrupt request due to HcDoneHead Writeback...
Page 294: Hchcca (Offset Address: 0X18)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.8 HcHCCA (offset address: 0x18) Name HCCA HCCA HCCA HCCA HCCA HCCA HCCA HCCA R/W (HCD) R/W (HC) After reset Name HCCA HCCA HCCA HCCA HCCA HCCA HCCA HCCA R/W (HCD) R/W (HC) After reset Name HCCA...
Page 295: Hcperiodcurrented (Offset Address: 0X1C)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.9 HcPeriodCurrentED (offset address: 0x1C) Name PCED PCED PCED PCED PCED PCED PCED PCED R/W (HCD) R/W (HC) After reset Name PCED PCED PCED PCED PCED PCED PCED PCED R/W (HCD) R/W (HC) After reset Name PCED...
Page 296: Hccontrolheaded (Offset Address: 0X20)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.10 HcControlHeadED (offset address: 0x20) Name CHED CHED CHED CHED CHED CHED CHED CHED R/W (HCD) R/W (HC) After reset Name CHED CHED CHED CHED CHED CHED CHED CHED R/W (HCD) R/W (HC) After reset Name CHED...
Page 297: Hccontrolcurrented (Offset Address: 0X24)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.11 HcControlCurrentED (offset address: 0x24) Name CCED CCED CCED CCED CCED CCED CCED CCED R/W (HCD) R/W (HC) After reset Name CCED CCED CCED CCED CCED CCED CCED CCED R/W (HCD) R/W (HC) After reset Name CCED...
Page 298: Hcbulkheaded (Offset Address: 0X28)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.12 HcBulkHeadED (offset address: 0x28) Name BHED BHED BHED BHED BHED BHED BHED BHED R/W (HCD) R/W (HC) After reset Name BHED BHED BHED BHED BHED BHED BHED BHED R/W (HCD) R/W (HC) After reset Name BHED...
Page 299: Hcbulkcurrented (Offset Address: 0X2C)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.13 HcBulkCurrentED (offset address: 0x2C) Name BCED BCED BCED BCED BCED BCED BCED BCED R/W (HCD) R/W (HC) After reset Name BCED BCED BCED BCED BCED BCED BCED BCED R/W (HCD) R/W (HC) After reset Name BCED...
Page 300: Hcdonehead (Offset Address: 0X30)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.14 HcDoneHead (offset address: 0x30) Name R/W (HCD) R/W (HC) After reset Name R/W (HCD) R/W (HC) After reset Name R/W (HCD) R/W (HC) After reset Name R/W (HCD) R/W (HC) After reset Name Function 31:0...
Page 301: Hcfminterval (Offset Address: 0X34)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.15 HcFmInterval (offset address: 0x34) Name FSMPS FSMPS FSMPS FSMPS FSMPS FSMPS FSMPS R/W (HCD) R/W (HC) After reset Name FSMPS FSMPS FSMPS FSMPS FSMPS FSMPS FSMPS FSMPS R/W (HCD) R/W (HC) After reset Name R/W (HCD) R/W (HC)
Page 302: Hcfmremaining (Offset Address: 0X38)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.16 HcFmRemaining (offset address: 0x38) Name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Name R/W (HCD)
Page 303: Hcfmnumber (Offset Address: 0X3C)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.17 HcFmNumber (offset address: 0x3C) Name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Name...
Page 304: Hcperiodicstart (Offset Address: 0X40)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.18 HcPeriodicStart (offset address: 0x40) Name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Name...
Page 305: Hclsthreshold (Offset Address: 0X44)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.19 HcLSThreshold (offset address: 0x44) Name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Name...
Page 306: Hcrhdescriptora (Offset Address: 0X48)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.20 HcRhDescriptorA (offset address: 0x48) (1/2) Name POTPGT POTPGT POTPGT POTPGT POTPGT POTPGT POTPGT POTPGT R/W (HCD) R/W (HC) Note Note Note Note Note Note Note Note After reset Name R/W (HCD) R/W (HC) After reset Undefined Undefined...
Page 307 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (2/2) Name Function Device Type Indicates that the root hub is not a compound device. No Power Switching Denial of power application switching 1: If the HC is on, the port power is also always applied. 0: The port power can be on or off.
Page 308: Hcrhdescriptorb (Offset Address: 0X4C)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.21 HcRhDescriptorB (offset address: 0x4C) (1/2) Name PPCM PPCM PPCM PPCM PPCM PPCM PPCM PPCM R/W (HCD) R/W (HC) Note Note Note Note Note Note Note Note After reset Name PPCM PPCM PPCM PPCM PPCM PPCM...
Page 309 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (2/2) Name Function 15:3 Reserved. Write 0 to these bits. 0 is returned after a read. Device Removable Connection of device to port 2 1: Connected 0: Not connected Device Removable Connection of device to port 1 1: Connected 0: Not connected Reserved.
Page 310: Hcrhstatus (Offset Address: 0X50)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.22 HcRhStatus (offset address: 0x50) (1/2) Name CRWE R/W (HCD) R/W (HC) Note 1 After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Name OCIC Note 2 R/W (HCD) R/W (HC) Note 1 Note 1 After reset Undefined...
Page 311 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (2/2) Name Function CRWE Clean Remote Wakeup Enable 1: Clear the RWE bit of the HcControl register to 0. 0: No change 30:18 Reserved. Write 0 to these bits. Since the values of these bits are undefined after a reset, initialize them by using software.
Page 312: Hcrhportstatus1, 2 (Offset Address: 0X54, 0X58)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.23 HcRhPortStatus1, 2 (offset address: 0x54, 0x58) (1/4) Name R/W (HCD) R/W (HC) After reset Name PRSC POCIC PSSC PESC R/W (HCD) R/W (HC) Note 1 Note 1 Note 1 Note 1 Note 1 After reset Name Note 2...
Page 313 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (2/4) Name Function 31: 21 Reserved. Write 0 to these bits. 0 is returned after a read. PRSC Port Reset Status Change This bit is set (1) due to the completion of a reset. It is cleared (0) when 1 is written by the HCD.
Page 314 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (3/4) Name Function <For writing> Set Port Power This bit is set to 1 at the following times. • When the PSM bit of the HcRhDescriptorA register is 0 and the SGP bit of the HcRhStatus register becomes 1 •...
Page 315 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (4/4) Name Function <For writing> Set Port Suspend This bit is set (1) when the CCS bit is 1 and 1 is written by the HCD. It is cleared (0) when the PSSC bit is set (1) or the PRSC bit is set (1), the HCFS area of the HcControl register is 01, or the port power is off.
Page 316: Usb Specifications
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.4 USB Specifications This section describes communication functions and operations using the USB and the structure of the interface data that is used. For details, see Open HCI Specification Release 1.0. 14.4.1 General The Universal Serial Bus (USB) is a serial bus for exchanging data between a host computer and various types of peripheral devices.
Page 317 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) Figure 14-4. Low-Speed Device Cable and Resistor Connections Full-speed or low- Low-speed USB transceiver speed USB Non-twisted unshielded cable transceiver D− D− Maximum cable length is 3 meters R1 = 15 k Ω ± 5% R2 = 1.5 k Ω...
Page 318: Host Controller Communication Methods
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.4.2 Host controller communication methods The host controller (HC) and host controller driver (HCD) communicate by using the following two routes. 1. Operational registers 2. HCCA (Host Controller Communication Area) For communication that is performed by using the operational registers contained in the HC, the HC is the PCI target device.
Page 319 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) Although ED lists are classified into four types (bulk, control, interrupt, and isochronous), three ED list header pointers are maintained (the isochronous type is excluded). The IsochronousED list is simply linked after the InterruptEDs.
Page 320 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) Figure 14-7 shows how OpenHCI allocates bandwidth. The HC selects the list to process based on a priority order algorithm. Control/bulk list processing has priority until the value of the FR area of the HcFmRemaining register from the beginning of the frame is the same as the value of the PS area of the HcPeriodicStart register.
Page 321: Ed (Endpoint Descriptor)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.4.3 ED (Endpoint Descriptor) An ED is always located in system memory in units of 16 bytes. When the HC checks an ED list and finds a linked TD, it executes the transfers indicated there. When the HCD must change the value of the HeadP area of an ED, the HCD sets (1) the K bit of the ED to disable all ED list processing having the same transfer type as the ED to be deleted so that the HC will not access the ED.
Page 322: Ed Fields
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.4.5 ED fields Table 14-3 shows details about the ED fields. Table 14-3. ED Fields (1/2) Field Name Function Function Address USB address of the function that includes the endpoint controlled by this ED Endpoint Number Endpoint address within the function Direction...
Page 323: Td (Transfer Descriptor)
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) Table 14-3. ED Fields (2/2) Field Name Function Toggle Carry This bit is a data toggle carry bit. When a TD is retired, this bit is always written using the final data toggle value (LSB of the T area) that was used by the retired TD. This field is not used by an isochronous endpoint.
Page 324: Generaltd Fields
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.4.8 GeneralTD fields Table 14-4 shows details about the GeneralTD fields. Table 14-4. GeneralTD Fields (1/2) Field Name Function Buffer Rounding 1: The final data packet will not fill the defined buffer even if no error occurs. 0: The defined data buffer must be completely filled by the final data packet from the endpoint indicated by the TD.
Page 325 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) Table 14-4. GeneralTD Fields (2/2) Field Name Function Current Buffer Pointer Indicates the next physical address in memory to be accessed by a transmission/reception for the endpoint. When this area is 0, it indicates either a data packet of length zero or that all bytes were transferred.
Page 326: Isochronoustd Format
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.4.9 IsochronousTD format An IsochronousTD is used only for isochronous endpoint. When the F bit of an ED is 1, all TDs that are linked to the ED always use this format, and the TDs are always located in system memory in units of 32 bytes. Figure 14-12.
Page 327: Isochronoustd Fields
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.4.10 IsochronousTD fields Table 14-5 shows details about the IsochronousTD fields. Table 14-5. IsochronousTD Fields Field Name Function Starting Frame Lower 16 bits of the frame number that is sent by the first data packet of the IsochronousTD Delay Interrupt Time until an interrupt request is issued after this IsochronousTD processing is completed Frame Count...
Page 328: Hcca Format
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.4.12 HCCA format Table 14-6 shows the HCCA format. Table 14-6. HCCA Format Offset Size Field Name Function Address (Bytes) HccaInterruptTable Pointer to an InterruptED 0x80 HccaFrameNumber Displays the current frame number. This value is updated by the HC before periodic list processing begins in the frame.
Page 329: Hc State Transitions
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.4.14 HC state transitions The HC has four states. These states are UsbOperational, UsbReset, UsbSuspend, and UsbResume. The current state is indicated in the HCFS area of the HcControl register. The HCD can execute the transitions between the USB states shown in Figure 14-13.
Page 330: List Service Flow
CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.4.15 List service flow Figure 14-14 shows the list service flow. Figure 14-14. List Service Flow Start Is list enabled? Synchronous list? Hc_Current ED = 0 ? Read head pointer BLF, CLF = 1 ? HeadP = 0 ? Isochronous Set Hc_Current ED...
Page 331 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) The list service flow is executed after the HC determines the kind of list that must be serviced. A list is periodically disabled by the HCD to switch the ED. Therefore, when processing lists, the HC first checks whether or not the target list is enabled according to the BLE, CLE, and PLE bits of the HcControl register.
Page 332 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) Figure 14-16 shows the TD service flow. When processing an IsochronousTD, the HC first calculates the relative frame number to decide whether to send a packet in the current frame. This relative frame number is used to select Offset(R) and Offset(R+1) (R = 0, 2, 4, 6).
Page 333 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) Figure 14-16. TD Service Flow Start Isochronous Compare Number with Frame in ED Frame Number > BE area value? FrameNumber < 0? Calculate Packet Addr and Size Retire TD PID = OUT? Perform SOF check Read Packet from memory...
Page 334 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) When processing a GeneralTD, the HC obtains the next memory address from the CBP area. For a transmission to or reception from the CurrentBufferPointer address of the data, the data many not fit in a single physical page and may span multiple pages.
Page 335 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) Figure 14-17. Transfer Completed Queue Operation HeadP NextTD NextTD HcDoneHead HeadP NextTD NextTD Remark 1 to 3: Operation sequence →: Writing of data User’s Manual U14579EJ2V0UM...
Page 336: Chapter 15 Ac97U (Ac97 Unit)
CHAPTER 15 AC97U (AC97 UNIT) 15.1 General The AC97U is a digital controller that is compliant with the Audio Codec ’97 Revision 2.1. It is used for connecting with an external Codec through an AC-Link. 15.2 Configuration Register Set Table 15-1 lists the AC97U PCI configuration registers. Table 15-1.
Page 337: Vid (Offset Address: 0X00 To 0X01)
Name VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 After reset Name Function 15:0 VID(15:0) Vendor ID 0x1033: NEC 15.2.2 DID (offset address: 0x02 to 0x03) Name DID15 DID14 DID13 DID12 DID11 DID10 DID9 DID8 After reset Name DID7 DID6...
Page 338: Pcicmd (Offset Address: 0X04 To 0X05)
CHAPTER 15 AC97U (AC97 UNIT) 15.2.3 PCICMD (offset address: 0x04 to 0x05) Name FBTB_EN SERREN After reset Name AD_STEP PERREN VGA_P_ MEMW_ SP_CYC MASTER_ MEM_EN IO_EN SNOOP INV_EN After reset Name Function 15:10 Reserved. Write 0 to these bits. 0 is returned after a read. FBTB_EN Enables/disables fast Back to Back.
Page 339: Pcists (Offset Address: 0X06 To 0X07)
CHAPTER 15 AC97U (AC97 UNIT) 15.2.4 PCISTS (offset address: 0x06 to 0x07) Name DETECT_ SIG_SERR SIG_TABOT DEVSEL1 DEVSEL0 DETECT_ PERR MABORT TABORT D_PERR After reset Name FBTB_CAP UDF_SPT 66M_CAP After reset Name Function DETECT_PERR Data and address parity error detection. Cleared to 0 when 1 is written. 1: Detected 0: Normal SIG_SERR...
Page 340: Rid (Offset Address: 0X08)
CHAPTER 15 AC97U (AC97 UNIT) 15.2.5 RID (offset address: 0x08) Name RID7 RID6 RID5 RID4 RID3 RID2 RID1 RID0 After reset Name Function RID(7:0) Revision ID 15.2.6 CLASSC (offset address: 0x09 to 0x0B) Name CLASSC23 CLASSC22 CLASSC21 CLASSC20 CLASSC19 CLASSC18 CLASSC17 CLASSC16 After reset...
Page 341: Mlt (Offset Address: 0X0D)
CHAPTER 15 AC97U (AC97 UNIT) 15.2.8 MLT (offset address: 0x0D) Name MLT7 MLT6 MLT5 MLT4 MLT3 MLT2 MLT1 MLT0 After reset Name Function MLT(7:4) Sets the latency timer. 1111: 30 PCLK (900 ns) 0010: 17 PCLK (510 ns) 0001: 16 PCLK (480 ns) 0000: 0 PCLK (0 ns) MLT(3:0) Write 0 to these bits.
Page 342: Baseadr (Offset Address: 0X10 To 0X13)
CHAPTER 15 AC97U (AC97 UNIT) 15.2.11 BASEADR (offset address: 0x10 to 0x13) Name BASEADR BASEADR BASEADR BASEADR BASEADR BASEADR BASEADR BASEADR After reset Name BASEADR BASEADR BASEADR BASEADR BASEADR BASEADR BASEADR BASEADR After reset Name BASEADR BASEADR BASEADR BASEADR BASEADR BASEADR BASEADR9 BASEADR8...
Page 343: Svid (Offset Address: 0X2C To 0X2D)
CHAPTER 15 AC97U (AC97 UNIT) 15.2.12 SVID (offset address: 0x2C to 0x2D) Name SVID15 SVID14 SVID13 SVID12 SVID11 SVID10 SVID9 SVID8 After reset Name SVID7 SVID6 SVID5 SVID4 SVID3 SVID2 SVID1 SVID0 After reset Name Function 15:0 SVID(15:0) Subsystem vendor ID This is a vendor identification number to be used for recognizing the system or option card.
Page 344: Exromadr (Offset Address: 0X30 To 0X33)
CHAPTER 15 AC97U (AC97 UNIT) 15.2.14 EXROMADR (offset address: 0x30 to 0x33) Name EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR After reset Name EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR After reset Name EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR...
Page 345: Intp (Offset Address: 0X3D)
CHAPTER 15 AC97U (AC97 UNIT) 15.2.16 INTP (offset address: 0x3D) Name INTP7 INTP6 INTP5 INTP4 INTP3 INTP2 INTP1 INTP0 After reset Name Function INTP(7:0) PCI interrupt pin 0x01: Serial (equipped with INTA# signal) 15.2.17 MIN_GNT (offset address: 0x3E) Name MIN_GNT7 MIN_GNT6 MIN_GNT5 MIN_GNT4...
Page 346: Operational Register Set
CHAPTER 15 AC97U (AC97 UNIT) 15.3 Operational Register Set Table 15-2 lists the AC97U operational registers. The AC97U operational registers are mapped to the I/O space. Table 15-2. AC97U Operational Registers Offset Address Register Symbol Function 0x00 INT_CLR/INT_STATUS Interrupt clear/status register 0x04 CODEC_WR Codec write register...
Page 347: Int_Clr/Int_Status (Offset Address: 0X00)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.1 INT_CLR/INT_STATUS (offset address: 0x00) (1/2) Name INTR After reset Name After reset Name IOSTS STSDAT STSADR ACLINK_CK After reset Name CODECGPI ACLINK DAC1END DAC2END DAC3END ADC1END ADC2END ADC3END After reset Name Function INTR Master interrupt request status 1: Any of bits 11 to 9 and bits 7 to 0 of this register are 1 0: All of bits 11 to 9 and bits 7 to 0 of this register are 0 30:12...
Page 348 CHAPTER 15 AC97U (AC97 UNIT) (2/2) Name Function ACLINK_CK AC-Link clock request interrupt request, or clock request interrupt request from Codec side during a suspend state 1: Interrupt requested 0: No interrupt requested Writing 1 for this bit clears to 0 the interrupt request signal that was set. CODECGPI Interrupt request when 1 was set for the AC97 input data slot 12 bit 0 1: Interrupt requested...
Page 349: Codec_Wr (Offset Address: 0X04)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.2 CODEC_WR (offset address: 0x04) Name WRDY After reset Name WADDR6 WADDR5 WADDR4 WADDR3 WADDR2 WADDR1 WADDR0 After reset Name WDAT15 WDAT14 WDAT13 WDAT12 WDAT11 WDAT10 WDAT9 WDAT8 After reset Name WDAT7 WDAT6 WDAT5 WDAT4 WDAT3 WDAT2 WDAT1...
Page 350: Codec_Rd (Offset Address: 0X08)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.3 CODEC_RD (offset address: 0x08) Name RRDYA RRDYD After reset Name RADDR6 RADDR5 RADDR4 RADDR3 RADDR2 RADDR1 RADDR0 After reset Name RDAT15 RDAT14 RDAT13 RDAT12 RDAT11 RDAT10 RDAT9 RDAT8 After reset Name RDAT7 RDAT6 RDAT5 RDAT4 RDAT3 RDAT2...
Page 351: Codec_Req (Offset Address: 0X0C)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.4 CODEC_REQ (offset address: 0x0C) Name After reset Name After reset Name SLOT3_REQ SLOT4_REQ After reset Name SLOT5_REQ SLOT6_REQ SLOT7_REQ SLOT8_REQ SLOT9_REQ SLOT10_REQ SLOT11_REQ SLOT12_REQ After reset Name Function 31:10 Reserved. Write 0 to these bits. 0 is returned after a read. SLOT3_REQ Codec input data slot 1 bit 11 (slot 3 request) SLOT4_REQ...
Page 352: Slot12_Wr (Offset Address: 0X10)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.5 SLOT12_WR (offset address: 0x10) Name WRDY_SLOT After reset Name LOOP WSLOT1219 WSLOT1218 WSLOT1217 WSLOT1216 After reset Name WSLOT1215 WSLOT1214 WSLOT1213 WSLOT1212 WSLOT1211 WSLOT1210 WSLOT129 WSLOT128 After reset Name WSLOT127 WSLOT126 WSLOT125 WSLOT124 WSLOT123 WSLOT122 WSLOT121 WSLOT120 After reset...
Page 353: Slot12_Rd (Offset Address: 0X14)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.6 SLOT12_RD (offset address: 0x14) Name RRDY_ SLOT After reset Name RSLOT1219 RSLOT1218 RSLOT1217 RSLOT1216 After reset Name RSLOT1215 RSLOT1214 RSLOT1213 RSLOT1212 RSLOT1211 RSLOT1210 RSLOT129 RSLOT128 After reset Name RSLOT127 RSLOT126 RSLOT125 RSLOT124 RSLOT123 RSLOT122 RSLOT121 RSLOT120 After reset...
Page 354: Ctrl (Offset Address: 0X18)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.7 CTRL (offset address: 0x18) (1/2) Name SRC_RAM_ SRC_CNVT SRC_ FILTER_ON After reset Note Name MICENB DAC3ENB ADC3ENB After reset Note Name DAC2ENB ADC2ENB DAC1ENB ADC1ENB After reset Name DAC1FORM2 DAC1FORM1 DAC1FORM0 ADC1FORM2 ADC1FORM1 ADC1FORM0 After reset Name Function...
Page 355 CHAPTER 15 AC97U (AC97 UNIT) (2/2) Name Function ADC3ENB Enables/disables ADC3 (LINE1) slot 1: Enable 0: Disable DAC2ENB Enables/disables DAC2 (PCMR) slot 1: Enable 0: Disable ADC2ENB Enables/disables ADC2 (PCMR) slot 1: Enable 0: Disable DAC1ENB Enables/disables DAC1 (PCML) slot 1: Enable 0: Disable Note...
Page 356: Aclink_Ctrl (Offset Address: 0X1C)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.8 ACLINK_CTRL (offset address: 0x1C) Name ck_stop_on sync_on After reset Name sync_time7 sync_time6 sync_time5 sync_time4 sync_time3 sync_time2 sync_time1 sync_time0 After reset Name aclink_rst_on After reset Name aclink_rst_ aclink_rst_ aclink_rst_ aclink_rst_ aclink_rst_ aclink_rst_ aclink_rst_ aclink_rst_ time7 time6 time5 time4...
Page 357 CHAPTER 15 AC97U (AC97 UNIT) Figure 15-1. SYNC Signal Set 1 in the sync_on bit The sync_on bit is automatically cleared SYNC (sync_time (7:0) + 2) × 33 MHz Figure 15-2. reset_b Signal (Internal Signal) Set 1 in the aclink_rst_on bit The aclink_rst_on bit is automatically cleared reset_b...
Page 358: Src_Ram_Data (Offset Address: 0X20)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.9 SRC_RAM_DATA (offset address: 0x20) Name After reset Name After reset Name SRC_RAM_ SRC_RAM_ SRC_RAM_ SRC_RAM_ SRC_RAM_ SRC_RAM_ SRC_RAM_ SRC_RAM_ DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 After reset Name SRC_RAM_ SRC_RAM_ SRC_RAM_ SRC_RAM_ SRC_RAM_ SRC_RAM_ SRC_RAM_...
Page 359: Int_Mask (Offset Address: 0X24)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.10 INT_MASK (offset address: 0x24) (1/2) Name MMASK After reset Name After reset Name MASK_ MASK_ MASK_ MASK_ IOSTS STSDAT STSADR ACLINK_CK After reset Name MASK_ MASK_ MASK_ MASK_ MASK_ MASK_ MASK_ MASK_ CODECGPI ACLINK DAC1END DAC2END DAC3END...
Page 360 CHAPTER 15 AC97U (AC97 UNIT) (2/2) Name Function MASK_ACLINK_CK Enables/disables AC-Link clock request interrupt or enables/disables clock request interrupt from Codec side during a suspend state 1: Enable 0: Disable MASK_CODECGPI Enables/disables interrupt when 1 was set for the AC97 input data slot 12 bit 0 1: Enable 0: Disable MASK_ACLINK...
Page 361: Dac1_Ctrl (Offset Address: 0X30)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.11 DAC1_CTRL (offset address: 0x30) Name DAC1_ DAC1_ ENABLE STATUS After reset Name After reset Name After reset Name After reset Name Function DAC1_ENABLE DAC1 DMA control 1: Enable 0: Disable DAC1_STATUS DAC1 AC-Link transfer status 1: Transfer in progress 0: Transfer ended 29:0...
Page 362: Dac1L (Offset Address: 0X34)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.12 DAC1L (offset address: 0x34) Name After reset Name After reset Name DAC1L15 DAC1L14 DAC1L13 DAC1L12 DAC1L11 DAC1L10 DAC1L9 DAC1L8 After reset Name DAC1L7 DAC1L6 DAC1L5 DAC1L4 DAC1L3 DAC1L2 DAC1L1 DAC1L0 After reset Name Function 31:16 Reserved.
Page 363: Dac1_Baddr (Offset Address: 0X38)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.13 DAC1_BADDR (offset address: 0x38) Name DAC1_ DAC1_ DAC1_ DAC1_ DAC1_ DAC1_ DAC1_ DAC1_ BADDR31 BADDR30 BADDR29 BADDR28 BADDR27 BADDR26 BADDR25 BADDR24 After reset Name DAC1_ DAC1_ DAC1_ DAC1_ DAC1_ DAC1_ DAC1_ DAC1_ BADDR23 BADDR22 BADDR21 BADDR20 BADDR19...
Page 364: Dac2_Ctrl (Offset Address: 0X3C)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.14 DAC2_CTRL (offset address: 0x3C) Name DAC2_ DAC2_ ENABLE STATUS After reset Name After reset Name After reset Name After reset Name Function DAC2_ENABLE DAC2 DMA control 1: Enable 0: Disable DAC2_STATUS DAC2 AC-Link transfer status 1: Transfer in progress 0: Transfer ended 29:0...
Page 365: Dac2L (Offset Address: 0X40)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.15 DAC2L (offset address: 0x40) Name After reset Name After reset Name DAC2L15 DAC2L14 DAC2L13 DAC2L12 DAC2L11 DAC2L10 DAC2L9 DAC2L8 After reset Name DAC2L7 DAC2L6 DAC2L5 DAC2L4 DAC2L3 DAC2L2 DAC2L1 DAC2L0 After reset Name Function 31:16 Reserved.
Page 366: Dac2_Baddr (Offset Address: 0X44)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.16 DAC2_BADDR (offset address: 0x44) Name DAC2_ DAC2_ DAC2_ DAC2_ DAC2_ DAC2_ DAC2_ DAC2_ BADDR31 BADDR30 BADDR29 BADDR28 BADDR27 BADDR26 BADDR25 BADDR24 After reset Name DAC2_ DAC2_ DAC2_ DAC2_ DAC2_ DAC2_ DAC2_ DAC2_ BADDR23 BADDR22 BADDR21 BADDR20 BADDR19...
Page 367: Dac3_Ctrl (Offset Address: 0X48)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.17 DAC3_CTRL (offset address: 0x48) Name DAC3_ DAC3_ ENABLE STATUS After reset Name After reset Name After reset Name After reset Name Function DAC3_ENABLE DAC3 DMA control 1: Enable 0: Disable DAC3_STATUS DAC3 AC-Link transfer status 1: Transfer in progress 0: Transfer ended 29:0...
Page 368: Dac3L (Offset Address: 0X4C)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.18 DAC3L (offset address: 0x4C) Name After reset Name After reset Name DAC3L15 DAC3L14 DAC3L13 DAC3L12 DAC3L11 DAC3L10 DAC3L9 DAC3L8 After reset Name DAC3L7 DAC3L6 DAC3L5 DAC3L4 DAC3L3 DAC3L2 DAC3L1 DAC3L0 After reset Name Function 31:16 Reserved.
Page 369: Dac3_Baddr (Offset Address: 0X50)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.19 DAC3_BADDR (offset address: 0x50) Name DAC3_ DAC3_ DAC3_ DAC3_ DAC3_ DAC3_ DAC3_ DAC3_ BADDR31 BADDR30 BADDR29 BADDR28 BADDR27 BADDR26 BADDR25 BADDR24 After reset Name DAC3_ DAC3_ DAC3_ DAC3_ DAC3_ DAC3_ DAC3_ DAC3_ BADDR23 BADDR22 BADDR21 BADDR20 BADDR19...
Page 370: Adc1_Ctrl (Offset Address: 0X54)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.20 ADC1_CTRL (offset address: 0x54) Name ADC1_ ENABLE After reset Name After reset Name After reset Name After reset Name Function ADC1_ENABLE ADC1 DMA control 1: Enable 0: Disable 30:0 Reserved. Write 0 to these bits. 0 is returned after a read. User’s Manual U14579EJ2V0UM...
Page 371: Adc1L (Offset Address: 0X58)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.21 ADC1L (offset address: 0x58) Name After reset Name After reset Name ADC1L15 ADC1L14 ADC1L13 ADC1L12 ADC1L11 ADC1L10 ADC1L9 ADC1L8 After reset Name ADC1L7 ADC1L6 ADC1L5 ADC1L4 ADC1L3 ADC1L2 ADC1L1 ADC1L0 After reset Name Function 31:16 Reserved.
Page 372: Adc1_Baddr (Offset Address: 0X5C)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.22 ADC1_BADDR (offset address: 0x5C) Name ADC1_ ADC1_ ADC1_ ADC1_ ADC1_ ADC1_ ADC1_ ADC1_ BADDR31 BADDR30 BADDR29 BADDR28 BADDR27 BADDR26 BADDR25 BADDR24 After reset Name ADC1_ ADC1_ ADC1_ ADC1_ ADC1_ ADC1_ ADC1_ ADC1_ BADDR23 BADDR22 BADDR21 BADDR20 BADDR19...
Page 373: Adc2_Ctrl (Offset Address: 0X60)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.23 ADC2_CTRL (offset address: 0x60) Name ADC2_ ENABLE After reset Name After reset Name After reset Name After reset Name Function ADC2_ENABLE ADC2 DMA control 1: Enable 0: Disable 30:0 Reserved. Write 0 to these bits. 0 is returned after a read. User’s Manual U14579EJ2V0UM...
Page 374: Adc2L (Offset Address: 0X64)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.24 ADC2L (offset address: 0x64) Name After reset Name After reset Name ADC2L15 ADC2L14 ADC2L13 ADC2L12 ADC2L11 ADC2L10 ADC2L9 ADC2L8 After reset Name ADC2L7 ADC2L6 ADC2L5 ADC2L4 ADC2L3 ADC2L2 ADC2L1 ADC2L0 After reset Name Function 31:16 Reserved.
Page 375: Adc2_Baddr (Offset Address: 0X68)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.25 ADC2_BADDR (offset address: 0x68) Name ADC2_ ADC2_ ADC2_ ADC2_ ADC2_ ADC2_ ADC2_ ADC2_ BADDR31 BADDR30 BADDR29 BADDR28 BADDR27 BADDR26 BADDR25 BADDR24 After reset Name ADC2_ ADC2_ ADC2_ ADC2_ ADC2_ ADC2_ ADC2_ ADC2_ BADDR23 BADDR22 BADDR21 BADDR20 BADDR19...
Page 376: Adc3_Ctrl (Offset Address: 0X6C)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.26 ADC3_CTRL (offset address: 0x6C) Name ADC3_ ENABLE After reset Name After reset Name After reset Name After reset Name Function ADC3_ENABLE ADC3 DMA control 1: Enable 0: Disable 30:0 Reserved. Write 0 to these bits. 0 is returned after a read. User’s Manual U14579EJ2V0UM...
Page 377: Adc3L (Offset Address: 0X70)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.27 ADC3L (offset address: 0x70) Name After reset Name After reset Name ADC3L15 ADC3L14 ADC3L13 ADC3L12 ADC3L11 ADC3L10 ADC3L9 ADC3L8 After reset Name ADC3L7 ADC3L6 ADC3L5 ADC3L4 ADC3L3 ADC3L2 ADC3L1 ADC3L0 After reset Name Function 31:16 Reserved.
Page 378: Adc3_Baddr (Offset Address: 0X74)
CHAPTER 15 AC97U (AC97 UNIT) 15.3.28 ADC3_BADDR (offset address: 0x74) Name ADC3_ ADC3_ ADC3_ ADC3_ ADC3_ ADC3_ ADC3_ ADC3_ BADDR31 BADDR30 BADDR29 BADDR28 BADDR27 BADDR26 BADDR25 BADDR24 After reset Name ADC3_ ADC3_ ADC3_ ADC3_ ADC3_ ADC3_ ADC3_ ADC3_ BADDR23 BADDR22 BADDR21 BADDR20 BADDR19...
Page 379: Ac97 Interface Configuration
CHAPTER 15 AC97U (AC97 UNIT) 15.4 AC97 Interface Configuration Figure 15-3 shows the AC97 interface configuration. Figure 15-3. AC97 Interface Configuration PCI bus 4173 PCI bridge Flip bus AC97U AC-Link AC97 Codec User’s Manual U14579EJ2V0UM...
Page 380: Ac97U Function Overview
CHAPTER 15 AC97U (AC97 UNIT) 15.5 AC97U Function Overview 15.5.1 Block diagram Figure 15-4 shows a block diagram of the AC97U. Figure 15-4. AC97U Block Diagram 4173 Flip bus AC97U Host interface DMA control Interrupt control Cache buffer SRC control AC-Link SDATAOUT BCLK (12.228 MHz)
Page 381: Ac-Link Interface Support Format
CHAPTER 15 AC97U (AC97 UNIT) 15.5.2 AC-Link interface support format The AC97U only supports the slots shown in Figure 15-5 among those in the AC97 guidelines. Figure 15-5. AC97U-Supported Slots µ 48 kHz (20.8 s) Slot number SYNC LINE1 SDATAOUT RFU RFU RFU RFU ADDR DATA...
Page 382: Dma Control
CHAPTER 15 AC97U (AC97 UNIT) (2) Data transfer On the PCI bus, 32-bit (word) data transfers are performed in units of 4 words. The first transfer after transfers are enabled is a 4-word burst transfer performed two times consecutively to fill the double buffer. Subsequently, the buffers are filled alternately by requesting the next data whenever one buffer becomes empty.
Page 383: Interrupt Control
CHAPTER 15 AC97U (AC97 UNIT) 15.5.5 Interrupt control Figure 15-9 shows interrupt control. Figure 15-9. Interrupt Control Interrupt source INTR Set 1 in INT_CLR/INT_STATUS register Interrupt request mask Various types of interrupt requests (INT_MSK register) 15.5.6 SRC (sample rate converter) This section explains the converter and filter functions.
Page 384 CHAPTER 15 AC97U (AC97 UNIT) (2) Converter function Figure 15-11 shows the converter function when data is output. When data is input, 48 Kss data is input from the AC-Link and converted to data of various rates in the reverse of the process shown for data output.
Page 385 CHAPTER 15 AC97U (AC97 UNIT) (3) Filter function A 32-order FIR filter is used as the filter function. Figure 15-12. Filter Function Codec 48k Waveform data 4k to 48k Converter Filter Record data 4k to 48k Codec 48k The output equation is as follows. y(x_0) = (a_−31 ×...
Page 386: Ac-Link Interface Data Transfer Format
CHAPTER 15 AC97U (AC97 UNIT) 15.6 AC-Link Interface Data Transfer Format Figure 15-13 shows the AC-Link interface data transfer format. Figure 15-13. AC-Link Interface Data Transfer Format µ 48 kHz (20.8 s) Slot number SYNC LINE1 SDATAOUT RFU RFU RFU RFU ADDR DATA CTRL...
Page 387 CHAPTER 15 AC97U (AC97 UNIT) (1) SDATAOUT slot 0: TAG Function Valid Frame When any of bits 14 to 10 or bit 3 is 1, 1 is set for this bit. Slot1 Valid bit When a write operation is performed for the CODEC_WR register, 1 is set for this bit. Slot2 Valid bit When a write operation is performed for the CODEC_WR register, 1 is set for this bit.
Page 388 CHAPTER 15 AC97U (AC97 UNIT) (4) SDATAOUT slot 3: PCML (PCM Playback Left Channel) Function 19:4 PCM Playback Left Data Outputs the result of the calculation (filter or rate conversion) that was performed on the data that was input from memory due to a DMA for DAC1. These bits are fixed at 0.
Page 389 CHAPTER 15 AC97U (AC97 UNIT) (8) SDATAIN slot 0: TAG Function Valid Frame When any of bits 14 to 10 or bit 3 is 1, this bit becomes 1. Slot1 Valid bit When 1 is entered for this bit, an interrupt request is generated. Slot2 Valid bit When 1 is entered for this bit, an interrupt request is generated.
Page 390 CHAPTER 15 AC97U (AC97 UNIT) (9) SDATAIN slot 1: STATUSADDR (Status Address Port) Function Unused 18:12 Control Register Index The value of this area is displayed in the RADDR(6:0) area of the CODEC_RD register. Slot3 Request: PCM Left Channel The value of this bit is displayed in the SLOT3_REQ bit of the CODEC_REQ register. Slot4 Request: PCM Right Channel The value of this bit is displayed in the SLOT4_REQ bit of the CODEC_REQ register.
Page 391 CHAPTER 15 AC97U (AC97 UNIT) (12) SDATAIN slot 4: PCMR (PCM Record Right Channel) Function 19:4 PCM Record Right Data This area is output to memory due to a DMA for ADC2. Unused (13) SDATAIN slot 5: LINE1ADC (Optional Modem Line1 ADC) Function 19:4 Optional Modem Line1 ADC Data...
Page 392: Data Output To Codec
CHAPTER 15 AC97U (AC97 UNIT) 15.7 Data Output to Codec (1) Data output to slot 1 or 2 The following steps <1> and <2> are repeated due to data output to slot 1 or 2. <1> Confirm that the WRDY bit of the CODEC_WR register in the operational registers is 0 (When it is 1, writing is enabled for slots 1 and 2).
Page 393: Data Input From Codec
CHAPTER 15 AC97U (AC97 UNIT) 15.8 Data Input from Codec (1) Slot 1 data input Data is read due to slot 1 data input by repeating the following steps (a) and (b). (a) Read data according to an interrupt request <1>...
Page 394: Dma Transfer
CHAPTER 15 AC97U (AC97 UNIT) (4) Slot 3, 4, 5, or 6 data input A DMA to the following cache buffers is started for slot 3, 4, 5, or 6 data input. • Slot 3: ADC1 Note • Slot 4: ADC2 •...
Page 395 CHAPTER 15 AC97U (AC97 UNIT) <4> To continue to perform DMA operations, set the next transfer base address and transfer count. <5> When the DMAs have executed the specified number of transfers, an interrupt request is generated and the DMA start bit is automatically cleared to 0. Slot Interrupt Status Bit Register...
Page 396 CHAPTER 15 AC97U (AC97 UNIT) The data length that is transferred to the buffer within the AC97U by a single DMA is 32 bits × 4 (= 16 bits × 8). The data that is used in a single transfer with the Codec is 16 bits among these bits. The following table shows the relationship between the CTRL register settings and data transfer counts.
Page 397 CHAPTER 15 AC97U (AC97 UNIT) <2> The DMA operation is started by setting 1 in the DMA start bit in the operational registers. Slot Start Bit Register 3, 6 ADC1_CTRL ADC1_ENABLE ADC2_CTRL ADC2_ENABLE ADC3_CTRL ADC3_ENABLE <3> Set the following items in the CTRL register in the operational registers. •...
Page 398 CHAPTER 15 AC97U (AC97 UNIT) • The counters for the base address and transfer count are separate from the registers. The register values are loaded in the counters only when the start bit is set to 1 and the DMA end interrupt request is generated. Therefore, if the next base address and transfer count are set in advance after the start bit was set to 1 or the DMA end interrupt request was generated, DMA operations can be performed continuously by loading the setting values after the DMA that is currently being processed ends.
Page 399: Special Interrupts
CHAPTER 15 AC97U (AC97 UNIT) 15.10 Special Interrupts This section explains bits 8 to 6 of the INT_CLR/INT_STATUS register in the operational registers. (1) Bit 8: ACLINK_CK An interrupt request is generated when there is a clock request from the Codec side during a suspend state. (2) Bit 7: CODECGPI An interrupt request is generated when valid data is input to AC97 input data slot 12 and bit 0 of slot 12 is 1.
Page 400: Ac97U Suspend Transition Procedure
CHAPTER 15 AC97U (AC97 UNIT) 15.11 AC97U Suspend Transition Procedure The procedure for setting the AC97U to suspend mode is shown below. <1> Issue a power down mode/power save mode command for the Codec. <2> Set the ck_stop_on bit of the ACLINK_CTRL register in the operational registers to 1. <3>...
Page 401: Filter Ram
CHAPTER 15 AC97U (AC97 UNIT) 15.12 Filter RAM To use the filter function with DMA transfers, the coefficients for the calculation must be set in advance in the filter RAM. The method of setting this RAM is described below. The RAM has two blocks. One is for data output (DAC) and the other is for data input (ADC). One block is 16 bits ×...
Page 402: Appendix A Cautions
APPENDIX A CAUTIONS A.1 Adjusting Skew of PCI Clock 4173 (4 ns, refer to µ µ µ µ PD31173 (V If the hold time of the PCLK signal of the V 4173) Data Sheet) cannot be satisfied, bring forward the rising edge of the PCI clock as illustrated in Figure A-1. Evaluate the PCI clock block. If necessary, insert a circuit that adjusts the skew of PCLK to the PCLK pin of the V 4173.
Page 403: Appendix B Restrictions
APPENDIX B RESTRICTIONS Version 3.1 of the V 4173 has the following restrictions. Consult NEC for the restrictions on products other than version 3.1. B.1 Noise During Operation of AC97 B.1.1 Phenomenon If playback or recording is performed with the AC97U, noise is superimposed on the sound.
Page 404: Erroneous Recognition Of Pc Card
APPENDIX B RESTRICTIONS B.2 Erroneous Recognition of PC Card B.2.1 Phenomenon The CEn1#, CEn2#, and OEn# pins output a low level for about 10 ms after the power supply to the card has been turned on (the supply voltage is set by the VCC(1:0) and VPP(1:0) areas of the PWR_CNT register). Some CF cards that quickly clear a power-on reset recognize this as a request for IDE mode by mistake, and enter the IDE mode.
Page 405: Preventive Measures
APPENDIX B RESTRICTIONS B.2.2 Preventive measures The CF card can be prevented from entering the IDE mode by adding the external circuit shown in Figure B-3. Figure B-3. Example of Circuit Preventing Shift to IDE Mode Card power supply GPIO 4173 CF card Note...
Page 406: Pulling Up Pc Card Pins
APPENDIX B RESTRICTIONS B.3 Pulling up PC Card Pins B.3.1 Phenomenon The C1A(22:20), C1A(15:14), WP1, C2A(22:20), C2A(15:14), and WP2 pins are always high when the power supply to the card is off. This is because the C1A(22:20), C1A(15:14), WP1, C2A(22:20), C2A(15:14), and WP2 pins are pulled up by an internal 50 kΩ...
Page 407: Incorrect Playback With Aiu
APPENDIX B RESTRICTIONS B.4 Incorrect Playback with AIU B.4.1 Phenomenon If recording and playback are simultaneously performed with the AIU, illegal data may be output during playback and thus playback may not be correctly executed. B.4.2 Preventive measures (1) Do not set the AIUMEN and AIUSEN bits of the SEQREG register to 1 at the same time. (2) Recording and playback can be performed simultaneously by using an interrupt and I/O read by the CPU as a substitute for DMA, without using recording DMA.
Page 408: Appendix C Index
APPENDIX C INDEX BIST............69, 195, 341 BRGCNT ............... 208 A/D converter unit ............ 27 Bulk transfers............317 A/D port scan ............149 Bus control unit..........26, 64 AC97U ............. 27, 336 Bus topology............316 AC97U operational registers......43, 346 BUSCNT..............
Page 409 APPENDIX C INDEX DAC3L ..............368 GIUINTSTATL ............113 DATA ..............220 GIUINTTYPH............117 Data lost..............150 GIUINTTYPL ............116 DCU ..............27, 81 GIULINTREG ............99 DCU registers ............ 30, 81 GIUPIODH..............112 DEVCNT ..............213 GIUPIODL ..............111 DID............65, 190, 337 GLO_CNT ..............241 DMA address unit ..........
Page 410 APPENDIX C INDEX Interrupt control outline diagram ......91 MEM_TIM_SEL1 ........... 256 Interrupt control unit ........... 27, 90 MEM_TIM_SEL2 ........... 256 Interrupt source............92 MEM_WIN_PWEN..........257 Interrupt transfers........... 317 MEM_WIN0_EAH ..........237 INTL ............72, 207, 344 MEM_WIN0_EAL........... 237 INTP............72, 208, 345 MEM_WIN0_OAH..........
Page 411 APPENDIX C INDEX MGIUHINTREG ............. 105 PS2CH1RST ............185 MGIULINTREG ............105 PS2CH2 registers..........34, 182 MIC ................ 165 PS2CH2CTRL ............184 MIDATREG ............157 PS2CH2DATA............183 MIN_GNT............72, 345 PS2CH2RST ............185 MKIUINTREG ............104 PS2U ..............27, 182 MLT............69, 195, 341 PWR_CNT..............228 MPIUINTREG ............102 MSYSINT1REG .............
Page 412 APPENDIX C INDEX Touch panel interface controller......128 Touch panel interface unit........ 27, 125 Touch/release detection......... 149 Transfer Descriptor ..........323 Universal serial bus unit........27, 274 USB host control configuration registers..........40, 275, 276 USB host control configuration space....275 USBU ...............
Page 413 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

This manual is also suitable for:

Vrc4173 Upd31173