NEC VRC4171A User Manual
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NEC VRC4171A User Manual

NEC VRC4171A User Manual

Companion chip for vr41xx family mips risc microprocessors
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User's Manual
V
4171A
Companion Chip
TM
RC
for V
41xx
Family MIPS® RISC Microprocessors
TM
R
Document no. U13275EU2V0UM00
Published October 1998
©1998 NEC Electronics Inc. All rights reserved. Printed in U.S.A.

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Summary of Contents for NEC VRC4171A

  • Page 1 User’s Manual 4171A Companion Chip for V 41xx Family MIPS® RISC Microprocessors Document no. U13275EU2V0UM00 Published October 1998 ©1998 NEC Electronics Inc. All rights reserved. Printed in U.S.A.

  • Page 3: Table Of Contents

    Contents 1. INTRODUCTION ......... . . 2.
  • Page 4 Contents Address Window Enable Register ....... . . 7-27 I/O Control Register ..........7-28 I/O Address Start Low-Byte Register .
  • Page 5 Contents Hardware Cursor Color 1A Register ....... 7-65 Hardware Cursor Color 1B Register ....... 7-66 Hardware Cursor Origin Register .
  • Page 6 Contents 4171 Companion Chip User’s Manual...

  • Page 7: Introduction

    Introduction The V 4171A is a companion chip to NEC’s 64-bit V 41xx family of MIPS® RISC microprocessors. Together, these two devices form the essential engine for most Windows® CE-based handheld products. Processor Interface • LCD module: *RD, *WR, *LCDCS and LCDRDY signals from the V 41xx •...
  • Page 8 Introduction Figure 1-1. Internal Block Diagram pc_addr_o[25:12] A_ADR[25:12] sa[25:0] pc_cd_i[2:1] *A_CD[2:1] SA[25:0] sa[25:0] sd[7:0] pc_bvd_i[2:1] A_BVD[2:1] pc_vs_i[2:1] *A_VS[2:1] SD[15:0] sd[15:0] exca_reg_r_dat[7:0] pc_wait_I *A_WAIT *SBHE sbhe pc_rdy_busy_I A_RDY/*A_BSY *SIORD siord_I pc_wp_iocs16_I A_WP *SIOWR siowr_I Slot A pc_crst_o A_RESET *SMRD smemrd_I pc_reg_I_o *A_REG *SMWR smemwr_I...

  • Page 9: Pin Functions

    Pin Functions The V 4171A companion chip has 208 total pins (Figure 2-1): • 188 signal pins • 20 power/ground pins Table 2-1. Clock Pins Name Type Drive Function Description – Crystal input Frequency operation ranges up to 50 MHz. Lower frequency crystals can be used for lower resolution LCD panels or lower bits/pixel displays to minimize overall power consumption.
  • Page 10 Pin Functions Figure 2-1. Pin Configuration 208-pin LQFP (28 mm x 28 mm with 0.5 mm pin pitch) MFP[8] *RESET MFP[7] *A_CD[2] MFP[6] *A_CD[1] MFP[5] *A_VS[2] MFP[4] *A_VS[1] MFP[3] *A_VCCEN[1] MFP[2] *A_VCCEN[0] MFP[1] A_VPPEN[1] MFP[0] A_VPPEN[0] A_BVD[2] MCLK/NC A_BVD[1] VPBIAS A_RESET VPLCDBL *SPKROUT...
  • Page 11 Pin Functions Table 2-2. System Bus Interface Pins Name Type Drive Function Description SA[25:0] 85–86, – System address bus inputs 26-bit addresses 116–129, 132–141 SD[15:0] 88–103 6 mA System data bus inputs 16-bit data *SBHE – System byte high enable input Active low *SIORD I–S...
  • Page 12 Pin Functions Table 2-3. LCD Graphics Controller Pins Name Type Drive Function Description I–S – Read command input Active low; asserted by the V 41xx to indicate a read cycle for RAM, ROM, or video memory I–S – Write command input Active low;...
  • Page 13 Pin Functions Table 2-4. PC Card Controller Pins (Partial) Name Type Drive Function Description A_RESET O–T/5V 6 mA Reset output Active high A_ADR 165-178 O–T/5V 6 mA Address bus [25:12] A_BVD 145-144 I–S/5V – Battery voltage detect inputs Active high [2:1] *A_CD[2:1] 152-153...
  • Page 14 Pin Functions Table 2-6. Multifunction Pins Name Type Drive Single Slot Dual Slots A: PC Card A: PC Card A: PC Card A: PC Card B: PC Card B: CompactFlash B: Miniature Card With External Without With Without With External OR External OR External OR External OR...
  • Page 15 Pin Functions Table 2-7. External Buffer Signals A: PC Card A: PC Card A: PC Card A: PC Card B: None B: PC Card B: CompactFlash B: Miniature Card — A_ADR[11:0] — — A_D[15:0] A_D[15:0] A_D[15:0] *A_OE *A_OE *A_OE *A_WE *A_WE *A_WE *A_IOR...
  • Page 16 Pin Functions 4171A Companion Chip User’s Manual...

  • Page 17: Main Clock Control

    Main Clock Control Figure 3-1. Internal and External Clock Control b[10] of Reg[05Fch] MCLK VMCLK 4171A only b[12] of Reg[05Feh] b[8:6] of b[5:3] of Reg[05Feh] Reg[05Feh] ÷1, ÷1, ÷2, ÷2, ÷3, ÷3, ÷4, ÷4, Oscillator Master Clock VCLK ÷5, ÷5, Cell ÷6, ÷6,...
  • Page 18 Main Clock Control Table 3-1. Main Clock Control Specifications Clock Type Name Description External X1/X2 Crystal input to generate clocks for the display controller CRYL_INH Crystal oscillation inhibit signal MCLK External clock input for video memory clock BUSCLK 8-MHz system bus clock (actual frequency depends on bit setting inside the V 41xx CPU) Internal...

  • Page 19: Card Controllers

    Card Controllers Two independent card controllers in the V 4171A are designed to work with a variety of commercially available memory cards: • 68-pin PC Card (compliant with ExCA or the PCMCIA/JEIDA release 2.1 specification) • 50-pin CompactFlash card or 68-pin CompactFlash card with PC Card adapter •...
  • Page 20 Card Controllers Each card controller interfaces directly to either a synchronous or asynchronous ISA-compatible bus or equivalent (Figure 4-1). Card status information, accessible through the interface status register of each slot, includes the following types of information: • Detection of card insertion or removal •...

  • Page 21: System Memory

    Card Controllers Each card controller implements power management for its own card socket via programmed options in the Power/RESETDRV Control register. Power sequencing delays specified by ExCA and PCMCIA release 2.1 are implemented in hardware. When the memory and I/O windows are disabled and the socket is empty, each card controller automatically enters a lower-power-consuming state, the lowest level of which can be achieved by disabling all I/O and memory windows, tri-stating all output buffers, and removing power to the card socket.

  • Page 22: Access Of Card I/O Addresses

    Card Controllers Access of Card I/O addresses are accessed if all of these conditions are met. Card I/O Addresses The I/O address mapping window is enabled. The system I/O address is greater than or equal to the System I/O Address Mapping Start register A[15:0];...

  • Page 23: Lcd Controller

    LCD Controller The LCD controller is designed to work with a variety of STN and TFT color or monochrome LCD panels. It consists of the fundamental blocks shown in Figure 5-1. Figure 5-1. LCD Block Diagram Write Interface Buffer Unit Display Memory/ Frame Buffer Memory Frame...
  • Page 24 LCD Controller The palette RAM contains the color palette used for color display (Table 5-1). It is orga- nized as 256 addresses by 18 bits (6 bits each for red, green, and blue color). The dithering engine is used for color STN panels to provide the appearance of more colors by modulating the data as it is being written to the panel during a frame of refresh.

  • Page 25: Hardware Cursor

    LCD Controller For formats of 5 and 6 bits per pixel, the upper used address bits are available for use as segments that make multiple simultaneous palettes available. This feature allows applications to switch palettes by reloading the on-chip palette, resulting in smoother transitions between applications that may only use a subset of the 256 color address locations available.
  • Page 26 LCD Controller 4171A Companion Chip User’s Manual...
  • Page 27 Address Decoding Table 6-1. Address Map Memory Type Starting Address Ending Address Display memory 0x0A000000 0x0A7FFFFF LCD control registers 0x0A800000 0x0AFFFFFF PC Card registers 0x15000000 0x15FFFFFF Display memory is decoded by the LCD chip select signal. The V 41xx CPU hardware decodes the fixed address for LCD display memory.

  • Page 28: Address Mapping/Decoding

    Address Mapping/Decoding 4171A Companion Chip User’s Manual...

  • Page 29: Registers

    Registers This section contains detailed information about the V 4171A’s registers. Table 7-1. Top-Level Register Summary (16-Bit Accesses Only) Register Name Address Signal Description Configuration register I 05FEh Configuration register II 05FCh Interrupt Status register 05FAh GPIO/*PCS Control/Data register 05EEh 05ECh *PCS[0] Upper addresses A[25:16] start register...
  • Page 30 Registers Table 7-3. 8-Bit PC Card Controller Index Register Register Name Slot A Slot B Identification and Revision register 0000h 0040h Interface Status Register 0001h 0041h Power and RESETDRV Control register 0002h 0042h Interrupt and General Control register 0003h 0043h Card Status Change register 0004h 0044h...
  • Page 31 Registers Table 7-3. 8-Bit PC Card Controller Index Register (continued) Register Name Slot A Slot B Card Memory Offset Address 3 Low-Byte register 002Ch 006Ch Card Memory Offset Address 3 High-Byte register 002Dh 006Dh Card Voltage Select register 002Fh 006Fh System Memory Address 4 Mapping Start Low-Byte register 0030h 0070h...
  • Page 32 Registers Table 7-4. 16-Bit LCD Register Summary (continued) Register Name Address Reserved 0034h Reserved 0036h Reserved 0038h Reserved 003Ah Reserved 003Ch Reserved 003Eh RAM Write Address register 0040h RAM Write Port 0 register 0042h RAM Write Port 1 register 0044h RAM Read Address register 0046h RAM Read Port 0 register...

  • Page 33: Top-Level Registers

    Registers Top-Level Registers Top-level registers [05xxh] are accessed through 16-bit operations; byte access is not supported . All reserved bits are set to zero upon hardware reset and should always be written to zero to ensure proper device operation. Configuration Register I Name Configuration Register I Type...
  • Page 34 Registers Table 7-5. Configuration Register 1 (continued) D8–D6 VMCLK_DIV Default = 0 for all bits [2:0] Divider from master clock to generate VMCLK 111 = master clock divide by 8 110 = master clock divide by 7 101 = master clock divide by 6 100 = master clock divide by 5 011 = master clock divide by 4 010 = master clock divide by 3...

  • Page 35: Configuration Register Ii

    Registers Configuration Register II Configuration Register II Name Type Identification and Revision Register Register Address 05FCh Bits D15–D12 D9–D4 D3–D2 SIL_REV Reserved MCLK_EN Reserved STBCTL[1:0] IOCH_R1 Reserved Table 7-6. Configuration Register II Bits Name Description D15–D12 SIL_REV Default = 0010 (V 4171A) and 0001 (V 4171) Silicon revision # = 0010...

  • Page 36: Interrupt Status Register

    Registers Interrupt Status Register Name Interrupt Status Register Type Read/Write Register Address 05Fah Bits IRQ[15] IRQ[14] Reserved IRQ[12] IRQ[11] IRQ[10] IRQ[9] Reserved IRQ[7] Reserved IRQ[5] IRQ[4] IRQ[3] IRQ_A IRQ_B Reserved Table 7-7. Interrupt Status Register Bit(s) Name Description D15–D14 IRQ[15:14] Default = 0 for all bits Status of interrupt request 15 and 14 1 = valid...

  • Page 37: Gpio/*Pcs Control/Data Register

    Registers GPIO/*PCS Control/Data Register Name GPIO/*PCS Control/Data Register Type Read/Write Register Address 05EEh Bits D13–D12 D11–D10 EN_PCS1 EN_PCS0 PCS1_CTL[1:0] PCS0_CTL[1:0] Reserved Reserved GPIO_DIR3 GPIO_DIR2 GPIO_DIR1 GPIO_DIR0 GPIO_DAT3 GPIO_DAT2 GPIO_DAT1 GPIO_DAT0 Table 7-8. GPIO/*PCS Control/Data Register Bit(s) Name Description EN_PCS1 Default = 0 1 = enable *PCS[1] function EN_PCS0 Default = 0...
  • Page 38 Registers Table 7-8. GPIO/*PCS Control/Data Register (continued) GPIO_DIR0 Default = 0 0 = input mode for GPIO[0] pin 1 = output mode for GPIO[0] pin GPIO_DAT3 Default = 0 Data value for GPIO[3] pin GPIO_DAT2 Default = 0 Data value for GPIO[2] pin GPIO_DAT1 Default = 0 Data value for GPIO[1] pin...
  • Page 39 Registers Programmable Chip *PCS1 and *PCS0 are independent functions controlled by bits D13–D10 of the GPIO/*PCS Select (PCS) Function control/data register [05EEh]. To enable *PCS: Set b[15:14] of Configuration Register I to either “01” or “10.” Set b[15] of GPIO/*PCS Control/Data Register to “1” to enable *PCS[1]. Set b[14] of GPIO/*PCS Control/Data Register to “1”...

  • Page 40: Pcs[0] Upper Starting Address A[25:16] Register

    Registers *PCS[0] Upper Starting Address Name *PCS[0] Upper Starting Address A[25:16] Register A[25:16] Register Type Read/Write Register Address 05ECh Bits D15–D10 D9–D8 D7–D0 Reserved PCS0_STARTA[25:24] PCS0_STARTA[23:16] Table 7-10. *PCS[0] Upper Starting Address A[25:16] Register Bits Name Description D15–D10 Reserved Default = 0 for all bits D9–D0 PCS0_STARTA[25:16] Default = 0 for all bits...

  • Page 41: Pcs[0] Lower Starting Address A[15:0] Register

    Registers *PCS[0] Lower Starting Address A[15:0] Register *PCS[0] Lower Starting Address A[15:0] Register Name Type Read/Write Register Address 05EAh Bits D15–D0 PCS0_STARTA[15:0] Table 7-11. *PCS[0] Lower Starting Address A[15:0] Register Bits Name Description D15–D0 PCS0_STARTA[15:0] Default = 0 for all bits Programmable chip select starting address value 4171A Companion Chip User’s Manual 7-13...

  • Page 42: Pcs[0] Upper Stopping Address A[25:16] Register

    Registers *PCS[0] Upper Stopping Address A[25:16] *PCS[0] Upper Stopping Address A[25:16] Register Name Register Type Read/Write Register Address 05E8h Bits D15–D10 D9–D8 D7–D0 Reserved PCS0_STOPA[25:24] PCS0_STOPA[23:16] Table 7-12. *PCS[0] Upper Stopping Address A[25:16] Register Bits Name Description D15–D10 Reserved Default = 0 for all bits D9–D0 PCS0_STOPA[25:16] Default = 0 for all bits...

  • Page 43: Pcs[0] Lower Stopping Address A[15:0] Register

    Registers *PCS[0] Lower Stopping Address A[15:0] Register Name *PCS[0] Lower Stopping Address A[15:0] Register Type Read/Write Register Address 05E6h Bits D15–D0 PCS0_STOPA[15:0] Table 7-13. *PCS[0] Lower Stopping Address A[15:0] Register Bits Name Description D15–D0 PCS0_STOPA[15:0] Default = 0 for all bits Programmable chip select stopping address value 4171A Companion Chip User’s Manual 7-15...

  • Page 44: Pcs[1] Upper Starting Address A[25:16] Register

    Registers *PCS[1] Upper Starting Address *PCS[1] Upper Starting Address A[25:16] Register Name A[25:16] Register Type Read/Write Register Address 05E4h Bits D15–D10 D9–D8 D7–D0 Reserved PCS1_STARTA[25:24] PCS1_STARTA[23:16] Table 7-14. *PCS[1] Upper Starting Address A[25:16] Register Bits Name Description D15–D10 Reserved Default = 0 for all bits D9–D0 PCS1_STARTA[25:16] Default = 0 for all bits...

  • Page 45: Pcs[1] Lower Starting Address A[15:0] Register

    Registers *PCS[1] Lower Starting Address A[15:0] *PCS[1] Lower Starting Address A[15:0] Register Name Register Type Read/Write Register Address 05E2h Bits D15–D0 PCS1_STARTA[15:0] Table 7-15. *PCS[1] Lower Starting Address A[15:0] Register Bits Name Description D15–D0 PCS1_STARTA[15:0] Default = 0 for all bits Programmable chip select starting address value 4171A Companion Chip User’s Manual 7-17...

  • Page 46: Pcs[1] Upper Stopping Address A[25:16] Register

    Registers *PCS[1] Upper Stopping Address Name *PCS[1] Upper Stopping Address A[25:16] Register A[25:16] Register Type Read/Write Register Address 05DEh Bits D15–D10 D9–D8 D7–D0 Reserved PCS1_STOPA[25:24] PCS1_STOPA[23:16] Table 7-16. *PCS[1] Upper Stopping Address A[25:16] Register Bits Name Description D15–D10 Reserved Default = 0 for all bits D9–D0 PCS1_STOPA[25:16] Default = 0 for all bits...

  • Page 47: Pcs[1] Lower Stopping Address A[15:0] Register

    Registers *PCS[1] Lower Stopping Address A[15:0] Register *PCS[1] Lower Stopping Address A[15:0] Register Name Type Read/Write Register Address 05DCh Bits D15–D0 PCS1_STOPA[15:0] Table 7-17. *PCS[1] Lower Stopping Address A[15:0] Register Bit(s) Name Description D15–D0 PCS1_STOPA Default = 0 for all bits [15:0] Programmable chip select stopping address for A[15:0] bits 4171A Companion Chip User’s Manual...

  • Page 48: Pc Card Registers

    Registers PC Card Registers Identification and Revision Register Name Identification and Revision Register Type Read only Register Address (Slot A) Index Base + 00h Register Address (Slot B) Index Base + 40h Bits IFTYP1 IFTYP0 Reserved Reserved REV3 REV2 REV1 REV0 Table 7-18.

  • Page 49: Interface Status Register

    Registers Interface Status Register Interface Status Register Name Type Read only Register Address (Slot A) Index Base + 01h Register Address (Slot B) Index Base + 41h Bits Reserved PWRON RDY/*BSY BVD2 BVD1 Table 7-19. Interface Status Register Bit(s) Name Description Reserved Default = 1...

  • Page 50: Power And Resetdrv Control Register

    Registers Power and RESETDRV Control Register Name Power and RESETDRV Control Register Type Read/Write Register Address (Slot A) Index Base + 02h Index Base + 42h Register Address (Slot B) Bits Reserved Reserved WPREN Reserved Reserved VPPSEL1 VPPSEL0 Table 7-20. Power and RESETDRV Control Register Bit(s) Name...

  • Page 51: Interrupt And General Control Register

    Registers Interrupt and General Control Register Name Interrupt and General Control Register Type Read/Write Register Address (Slot A) Index Base + 03h Index Base + 43h Register Address (Slot B) Bits RI_EN CRDRST CRDTYP Reserved IRQSEL3 IRQSEL2 IRQSEL1 IRQSEL0 Table 7-21. Interrupt and General Control Register Bit(s) Name...

  • Page 52: Card Status Change Register

    Registers Card Status Change Register Name Card Status Change Register Type Read-Only Register Address (Slot A) Index Base + 04h Index Base + 44h Register Address (Slot B) Bits Reserved Reserved Reserved Reserved CD_CHG RDY_CHG BAT_WARN BAT_DEAD Table 7-22. Card Status Change Register Bit(s) Name Description...

  • Page 53: Card Status Change Interrupt Configuration Register

    Registers Card Status Change Interrupt Configuration Name Card Status Change Interrupt Configuration Register Register Type Read/Write Register Address (Slot A) Index Base + 05h Index Base + 45h Register Address (Slot B) Bits SIRQS3 SIRQS2 SIRQS1 SIRQS0 CD_EN RDY_EN BWARN_EN BDEAD_EN Table 7-23.
  • Page 54 Registers Table 7-23. Card Status Change Interrupt Configuration Register (continued) BDEAD_EN Default = 0 Battery Dead Enable /*STSCHG bit 0 = Disables the card status change interrupt when a battery dead condition (memory card) or active *STSCHG (I/O card) is detected 1 = For memory PC Cards, enables a card status change interrupt when a battery dead condition is detected.

  • Page 55: Address Window Enable Register

    Registers Address Window Enable Register Address Window Enable Register Name Type Read/Write Register Address (Slot A) Index Base + 06h Register Address (Slot B) Index Base + 46h Bits IOWEN1 IOWEN0 Reserved MWEN4 MWEN3 MWEN2 MWEN1 MWEN0 Table 7-24. Address Window Enable Register Bit(s) Name Description...

  • Page 56: I/O Control Register

    Registers I/O Control Register Name I/O Control Register Type Read/Write Register Address (Slot A) Index Base + 07h Index Base + 47h Register Address (Slot B) Bits Reserved W1_IOWS IO1_CS16MD IO1DSZ Reserved W0_IOWS IO0_CS16MD IO0DSZ Table 7-25. I/O Control Register Bit(s) Name Description...

  • Page 57: I/O Address Start Low-Byte Register

    Registers I/O Address Start Low-Byte Register I/O Address Start Low-Byte Register Name Type Read/Write Register Address (Slot A) Window 0: Index Base + 08h Window 1: Index Base + 0Ch Register Address (Slot B) Window 0: Index Base + 48h Window 1: Index Base + 4Ch Bits STARTAL7...

  • Page 58: I/O Address Start High-Byte Register

    Registers I/O Address Start High-Byte Register Name I/O Address Start High-Byte Register Type Read/Write Register Address (Slot A) Window 0: Index Base + 09h Window 1: Index Base + 0Dh Register Address (Slot B) Window 0: Index Base + 49h Window 1: Index Base + 4Dh Bits STARTAH15...

  • Page 59: I/O Address Stop Low-Byte Register

    Registers I/O Address Stop Low-Byte Register Name I/O Address Stop Low-Byte Register Type Read/Write Register Address (Slot A) Window 0: Index Base + 0Ah Window 1: Index Base + 0Eh Register Address (Slot B) Window 0: Index Base + 4Ah Window 1: Index Base + 4Eh Bits STOPAL7...

  • Page 60: I/O Address Stop High-Byte Register

    Registers I/O Address Stop High-Byte Register I/O Address Stop High-Byte Register Name Type Read/Write Register Address (Slot A) Window 0: Index Base + 0Bh Window 1: Index Base + 0Fh Register Address (Slot B) Window 0: Index Base + 4Bh Window 1: Index Base + 4Fh Bits STOPAH15...

  • Page 61: System Memory Address Mapping Start Low-Byte Register

    Registers System Memory Address Mapping Start Name System Memory Address Mapping Start Low-Byte Register Low-Byte Register Type Read/Write Register Address (Slot A) Window 0: Index Base + 10h Window 1: Index Base + 18h Window 2: Index Base + 20h Window 3: Index Base + 28h Window 4: Index Base + 30h Register Address (Slot B)
  • Page 62 Registers To access a range from 0 to 32K, set the card memory offset address value to a negative value (offset). For example, A25–A12 = 3FF8h. 3FF800h + 8000h = 4000000. Overflow bit A26 is discarded, resulting in a PC Card address of 0000000. Set a positive value (offset) in the card memory offset address value to achieve positive (higher) PC Card memory access ranges.

  • Page 63: System Memory Address Mapping Start High-Byte Register

    Registers System Memory Address Mapping Start Name System Memory Address Mapping Start High-Byte Register High-Byte Register Type Read/Write Register Address (Slot A) Window 0: Index Base + 11H Window 1: Index Base + 19H Window 2: Index Base + 21H Window 3: Index Base + 29H Window 4: Index Base + 31H Register Address (Slot B)

  • Page 64: System Memory Address Mapping Stop Low-Byte Register

    Registers System Memory Address Mapping Stop Name System Memory Address Mapping Stop Low-Byte Register Low-Byte Register Type Read/Write Register Address (Slot A) Window 0: Index Base + 12h Window 1: Index Base + 1Ah Window 2: Index Base + 22h Window 3: Index Base + 2Ah Window 4: Index Base + 32h Register Address (Slot B)

  • Page 65: System Memory Address Mapping Stop High-Byte Register

    Registers System Memory Address Mapping Stop Name System Memory Address Mapping Stop High-Byte Register High-Byte Register Type Read/Write Register Address (Slot A) Window 0: Index Base + 13h Window 1: Index Base + 1Bh Window 2: Index Base + 23h Window 3: Index Base + 2Bh Window 4: Index Base + 33h Register Address (Slot B)

  • Page 66: Card Memory Offset Address Low-Byte Register

    Registers Card Memory Offset Address Name Card Memory Offset Address Low-Byte Register Low-Byte Register Type Read/Write Register Address (Slot A) Window 0: Index Base + 14H Window 1: Index Base + 1CH Window 2: Index Base + 24H Window 3: Index Base + 2CH Window 4: Index Base + 34H Register Address (Slot B) Window 0: Index Base + 54H...

  • Page 67: Card Memory Offset Address High-Byte Register

    Registers Card Memory Offset Address Name Card Memory Offset Address High-Byte Register High-Byte Register Type Read/Write Register Address (Slot A) Window 0: Index Base + 15H Window 1: Index Base + 1DH Window 2: Index Base + 25H Window 3: Index Base + 2DH Window 4: Index Base + 35H Register Address (Slot B) Window 0: Index Base + 55H...

  • Page 68: Card Detect And General Control Register

    Registers Card Detect and General Control Register Name Card Detect and General Control Register Type Read/Write Register Address (Slot A) Index Base + 16H Register Address (Slot B) Index Base + 56H Bits Reserved Reserved SWCDINT CDRSMEN Reserved Reserved CFGRSTEN DLY16INH Table 7-36.
  • Page 69 Registers Table 7-36. Card Detect and General Control Register (continued) CFGRSTEN Default = 0 Configuration Reset Enable bit 1 = When this bit is set to “1,” and both the *CD[2:1] inputs go high, a reset pulse is generated to reset the slot configuration registers to their default state.

  • Page 70: Global Control Register

    Registers Global Control Register Name Global Control Register Type Read/Write Register Address (Slot A) Index Base + 1EH Register Address (Slot B IIndex Base + 5EH Bits Reserved Reserved Reserved CLRPMIRQ IRQPM_EN EXWRBK Reserved Reserved Table 7-37. Global Control Register Bit(s) Name Description...

  • Page 71: Card Voltage Sense Register

    Registers Card Voltage Sense Register Name Card Voltage Sense Register Type Read/Write Register Address (Slot A) Index Base + 1FH Register Address (Slot B) Index Base + 5FH Bits Reserved Reserved Reserved Reserved Reserved Reserved *VS2 *VS1 Table 7-38. Card Voltage Sense Register Bit(s) Name Description...

  • Page 72: Card Voltage Select Register

    Registers Card Voltage Select Register Name Card Voltage Select Register Type Read/Write Register Address (Slot A) Index Base + 2FH Index Base + 6FH Register Address (Slot B) Bits Reserved Reserved Reserved Reserved Reserved Reserved VCCEN1 VCCEN0 Table 7-39. Card Voltage Select Register Bit(s) Name Description...

  • Page 73: Lcd Registers

    Registers LCD Registers Panel Select Register Name Panel Select Register Type Read/Write Register Address 0000h Bits D15–D7 D5–D4 Reserved HALF_DUAL Reserved 8_STN P_COLOR_SEL DUAL_PANEL PANELTYPE Table 7-40. Panel Select Register Bit(s) Name Description D15–D7 Reserved Default = 0 for all bits HALF_DUAL Default = 0 Half Dual Panel Select...

  • Page 74: Panel Control Register

    Registers Panel Control Register Name Panel Control Register Type Read/Write Register Address 0002h Bits D15-D13 D7–D3 D2–D0 Reserved EN_WAVE FLM_POL LP_POL OFF_SHCLK Reserved COLOR_DEPTH Table 7-41. Panel Control Register Bit(s) Name Description D15–D12 Reserved Default = 0 EN_WAVE Default = 0 1 = enable wave equation (gray level is generated from RGB and output to the G channel) FLM_POL...

  • Page 75: Power Mode Control Register

    Registers Power Mode Control Register Name Power Mode Control Register Type Read/Write Register Address 0004h Bits D15–D6 Reserved SEL_REF PWR_DWN BACKLIGHT_ON EN_VDD EN_PANEL EN_VEE Table 7-42. Power Mode Control Register Bit(s) Name Description D15–D6 Reserved Default = 0 SEL_REF Default = 0 Self refresh enable 1 = Enable PWR_DWN...

  • Page 76: Vmclk Enable Register

    Registers VMCLK Enable Register Name VMCLK Enable Register Type Read/Write Register Address 0006h Bits D15–D1 Reserved ENABLE_VMCLK Table 7-43. VMCLK Enable Register Bit(s) Name Description D15–D1 Reserved Default = 0 ENABLE_VMCLK Default = 1 1 = Enable VMCLK clock in the LCD controller 7-48 4171A Companion Chip User’s Manual...

  • Page 77: Vclk Enable Register

    Registers VCLK Enable Register Name VCLK Enable Register Type Read/Write Register Address 0008h Bits D15–D1 Reserved EN_VCLK Table 7-44. VCLK Enable Register Bit(s) Name Description D15–D1 Reserved Default = 0 EN_VCLK Default = 1 1 = Enable VCLK clock 4171A Companion Chip User’s Manual 7-49...

  • Page 78: Video Fifo/Memory Interface Control Register

    D7–D5 Reserved VRAS_CTL VCAS_CTL SCREEN_OFF DRAM_OFF FIFO_THD MEMSIZE MEM_CONF Reserved FIFO_DEP (VRC4171A) Table 7-45. Video FIFO/Memory Interface Control Register Bit(s) Name Description D15–D13 Reserved Default = 0 VRAS_CTL Default = 0 0 = *VRAS [1:0] low to *VCAS [1:0] low has three MCLK periods 1 = *VRAS [1:0] low to *VCAS [1:0] low has two MCLK periods D11–D10...

  • Page 79: Pixel Adjustment / Vertical Half Register

    Registers Pixel Adjustment / Vertical Half Register Name Pixel Adjustment / Vertical Half Register Type Read/Write Register Address 000Ch Bits D15–D13 D12–D11 D10–D0 TFT_ADJ Reserved VERT_HALF Table 7-46. Pixel Adjustment / Vertical Half Register Bit(s) Name Description D15–D13 TFT_ADJ Default = 00 TFT pixel adjustment for starting display D12–D11 Reserved...

  • Page 80: Horizontal Display Register

    Registers Horizontal Display Register Horizontal Display Register Name Type Read/Write Register Address 0010h Bits D15-D8 D7-D0 HORIZ_DISP_END HORIZ_TOTAL Table 7-48. Horizontal Display Register Bit(s) Name Description D15-D8 HORIZ_DISP Default = 0 for all bits _END (Note) Horizontal Display End Value = (H /8) –...

  • Page 81: Horizontal Retrace Control Register

    Registers Horizontal Retrace Control Register Name Horizontal Retrace Control Register Type Read/Write Register Address 0012h Bits D15–D8 D7–D0 HORIZ_RETEND HORIZ_RETSRT Table 7-49. Horizontal Retrace Control Register Bit(s) Name Description D15–D8 HORIZ_ Default = 0 RETEND (Note) Horizontal Retrace End Value = (H _porch + H DISP FRONT...

  • Page 82: Vertical Display End Register

    Registers Vertical Display End Register Name Vertical Display End Register Type Read/Write Register Address 0014h Bits D15–D11 D10–D0 Reserved VERT_END Table 7-50. Vertical Display End Register Bit(s) Name Description D15–D11 Reserved Default = 0 for all bits D10–D0 VERT_END Default = 0 for all bits Vertical Display End Value = V –...

  • Page 83: Vertical Display Total Register

    Registers Vertical Display Total Register Name Vertical Display Total Register Type Read/Write Register Address 0016h Bits D15–D11 D10–D0 Reserved VERT_TOTAL Table 7-51. Vertical Display Total Register Bit(s) Name Description D15–D11 Reserved Default = 0 for all bits D10–D0 VERT_TOTAL Default = 0 for all bits Vertical Total Value = V –...

  • Page 84: Vertical Retrace Start Register

    Registers Vertical Retrace Start Register Vertical Retrace Start Register Name Type Read/Write Register Address 0018h Bits D15–D11 D10–D0 Reserved VERT_RETST Table 7-52. Vertical Retrace Start Register Bit(s) Name Description D15–D11 Reserved Default = 0 for all bits D10–D0 VERT_RETST Default = 0 for all bits Vertical Retrace Start Value = V _porch...

  • Page 85: Vertical Retrace End Register

    Registers Vertical Retrace End Register Name Vertical Retrace End Register Type Read/Write Register Address 001Ah Bits D15–D10 D9–D7 D6–D4 D3–D0 Reserved VERT_END_SKIP VERT_SKIP VERT_RETEND Table 7-53. Vertical Retrace End Register Bit(s) Name Description D15–D10 Reserved Default = 0 for all bits D9–D7 VERT_END_ Default = 0 for all bits...

  • Page 86: Starting Address Register

    Registers Starting Address Register Starting Address Register Name Type Read/Write Register Address 001Ch Bits D15–D0 START_ADDR Table 7-54. Starting Address Register Bit(s) Name Description D15–D0 START_ADDR Address is combined with Offset Register (001Eh) bits [14:12] to form the frame memory starting address for display. Frame Memory Starting Address[17:2];...

  • Page 87: Offset Register

    Registers Offset Register Name Offset Register Type Read/Write Register Address 001Eh Bits D14–D12 D11–D10 D9–D0 Reserved A_OVERFLOW Reserved SCREEN_WIDTH Table 7-55. Offset Register Bit(s) Name Description Reserved Default = 0 D14–D12 A_OVERFLOW Default = 0 for all bits Frame Memory Starting Address[20:18] D11–D10 Reserved Default = 00...

  • Page 88: Hardware Cursor Control Register

    Registers Hardware Cursor Control Register Hardware Cursor Control Register Name Type Read/Write Register Address 0020h Bits D15-D3 Reserved CURSOR Reserved EN_CURSOR Table 7-57. Hardware Cursor Control Register Bit(s) Name Description D15-D3 Reserved Default = 0 for all bits CURSOR Default = 0 Hardware Cursor Pattern Select Reserved Default = 0...

  • Page 89: Hardware Cursor X Position Register

    Registers Hardware Cursor X Position Register Name Hardware Cursor X Position Register Type Read/Write Register Address 0022h Bits D15–D11 D10–D0 Reserved CURSOR_XPOST Table 7-59. Hardware Cursor X Position Register Bit(s) Name Description D15–D11 Reserved Default = 0 for all bits D10–D0 CURSOR_ Default = 0...

  • Page 90: Hardware Cursor Y Position Register

    Registers Hardware Cursor Y Position Register Hardware Cursor Y Position Register Name Type Read/Write Register Address 0024h Bits D15–D11 D10–D0 Reserved CURSOR_YPOST Table 7-60. Hardware Cursor Y Position Register Bit(s) Name Description D15–D11 Reserved Default = 0 for all bits D10–D0 CURSOR_ 0 = sets hardware cursor at top line (default)

  • Page 91: Hardware Cursor Color 0A Register

    Registers Hardware Cursor Color 0A Register Name Hardware Cursor Color 0A Register Type Read/Write Register Address 0026h Bits D15–D14 D13–D8 D7–D6 D5–D0 Reserved RED_0 Reserved GREEN_0 Table 7-61. Hardware Cursor Color 0A Register Bit(s) Name Description D15–D14 Reserved Default = 0 for all bits D13–D8 RED_0 Default = 0...

  • Page 92: Hardware Cursor Color 0B Register

    Registers Hardware Cursor Color 0B Register Hardware Cursor Color 0B Register Name Type Read/Write Register Address 0028h Bits D15–D6 D5–D0 Reserved BLUE_0 Table 7-63. Hardware Cursor Color 0B Register Bit(s) Name Description D15–D6 Reserved Default = 0 for all bits D5–D0 BLUE_0 Default = 0...

  • Page 93: Hardware Cursor Color 1A Register

    Registers Hardware Cursor Color 1A Register Name Hardware Cursor Color 1A Register Type Read/Write Register Address 002Ah Bits D15–D14 D13–D8 D7–D6 D5–D0 Reserved RED_1 Reserved GREEN_1 Table 7-64. Hardware Cursor Color 1A Register Bit(s) Name Description D15–D14 Reserved Default = 0 for all bits D13–D8 RED_1 Default = 0 for all bits...

  • Page 94: Hardware Cursor Color 1B Register

    Registers Hardware Cursor Color 1B Register Hardware Cursor Color 1B Register Name Type Read/Write Register Address 002Ch Bits D15–D6 D5–D0 Reserved BLUE_1 Table 7-65. Hardware Cursor Color 1B Register Bit(s) Name Description D15–D6 Reserved Default = 0 for all bits D5–D0 BLUE_1 Default = 0 for all bits...

  • Page 95: Hardware Cursor Origin Register

    Registers Hardware Cursor Origin Register Name Hardware Cursor Origin Register Type Read/Write 002Eh Register Address Bits D15–D14 D13–D8 D7–D6 D5–D0 Reserved Y_ORIGIN Reserved X_ORIGIN Table 7-66. Hardware Cursor Origin Register Bit(s) Name Description D15–D14 Reserved Default = 0 for all bits D13–D8 Y_ORIGIN Default = 0 for all bits...

  • Page 96: Ram Write Address Register

    Registers RAM Write Address Register RAM Write Address Register Name Type Write-Only (16-Bit Access Only) Register Address 0040h Bits D15–D8 D7–D0 Reserved RAM_W_ADDR Table 7-67. RAM Write Address Register to 18-Bit Palette RAM Bit(s) Name Description D15–D8 Reserved Default = 0 for all bits D7–D0 RAM_W_ADDR RAM write address...

  • Page 97: Ram Write Port Register 0

    Registers RAM Write Port Register 0 Name RAM Write Port Register 0 Type Write-Only (16-Bit Access Only) Register Address 0042h Bits D15–D14 D13–D8 D7–D6 D5–D0 Reserved RED_W_REG Reserved GREEN_W_REG Table 7-68. RAM Write Port Register 0 Bit(s) Name Description D15–D14 Reserved Default = 0 for all bits D13–D8...
  • Page 98 Registers RAM Write Port Register 1 RAM Write Port Register 1 Name Type Write-Only (16-Bit Access Only) Register Address 0044h Bits D15–D6 D5–D0 Reserved BLUE_W_REG Table 7-69. RAM Write Port Register 1 Bit(s) Name Description D15–D6 Reserved Default = 0 for all bits D5–D0 BLUE_W_REG Default = 0 for all bits...

  • Page 99: Ram Read Address Register

    Registers RAM Read Address Register Name RAM Read Address Register Type Write-Only (16-Bit Access Only) Register Address 0046h Bits D15–D8 D7–D0 Reserved RAM_R_ADDR Table 7-70. RAM Read Address Register Bit(s) Name Description D15–D8 Reserved Default = 0 for all bits D7–D0 RAM_R_ADDR Default = 0 for all bits...
  • Page 100 Registers RAM Read Port Register 0 RAM Read Port Register 0 Name Type Read-Only Register Address 0048h Bits D15–D14 D13–D8 D7–D6 D5–D0 Reserved RED_R_REG Reserved GREEN_R_REG Table 7-71. RAM Read Port Register 0 Bit(s) Name Description D15–D14 Reserved Default = 0 for all bits D13–D8 RED_R_REG Default = 0 for all bits...
  • Page 101 Registers RAM Read Port Register 1 Name RAM Read Port Register 1 Type Read-Only Register Address 004Ah Bits D15–D6 D5–D0 Reserved BLUE_R_REG Table 7-72. RAM Read Port Register 1 Bit(s) Name Description D15–D6 Reserved Default = 0 for all bits D5–D0 BLUE_R_REG Default = 0 for all bits...

  • Page 102: Scratch Pad Register 0

    Registers Scratch Pad Register 0 Name Scratch Pad Register 0 Type Read/Write Register Address 0050h Bits D15–D0 Reserved Table 7-73. Scratch Pad Register 0 Bit(s) Name Description D15–D0 Reserved Default = 0 for all bits 7-74 4171A Companion Chip User’s Manual...
  • Page 103 Registers Scratch Pad Register 1 Name Scratch Pad Register 1 Type Read/Write Register Address 0052h Bits D15–D0 Reserved Table 7-74. Scratch Pad Register 1 Bit(s) Name Description D15–D0 Reserved Default = 0 for all bits 4171A Companion Chip User’s Manual 7-75...
  • Page 104 Registers Hardware Cursor The hardware cursor supports a 32 x 32 x 2 user-defined pattern that is stored in the upper 512 bytes of frame memory. The cursor pattern has two bits to select the display mode of a pixel. Each bit corresponds to a plane.
  • Page 105 Registers For indexed modes (1, 2, 4, 5, 6 and 8 bpp), the inverted color is the 1’s complement of the index number generated from the original video pixel display information. This inverted index number must have a color previously programmed into the 18-bit color RAM palette data. If not previously programmed, color might revert to black (0000) or some odd color.
  • Page 106 Registers As shown in Table 7-76, the pattern continues through address 00-0xFF, for a total of 256 bytes (32 x 32 x 2 bits = 256 bytes). Table 7-76. Hardware Cursor Pattern Address Mapping Bytes Description 0–3 Plane 0 pixel bit for cursor scan line 1 4–7 Plane 1 pixel bit for cursor scan line 1 8–B...
  • Page 107 Registers Table 7-78. Hardware Cursor Data Value for Four Display Modes Horizontal Scan Line Byte 1 Address Byte 2 Address Byte 3 Address Byte 4 Address Plane 0 0x00 0x01 0x02 0x03 Plane 1 0x04 0x05 0x06 0x07 Plane 0 0x08 0x09 0x0A...

  • Page 108: Hardware Cursor

    Registers There are two hardware cursor patterns available in register 0xAA800020 (Table 7-81). Table 7-81. Hardware Cursor Patterns in Register 0xAA800020 0000 (0x01) 0xAA1FFE00 – EFF Pattern 0 0000 (0x05) 0xAA1FFF00 – FFF Pattern 1 0000 (0x00) Hardware Cursor Disabled In indexed modes, the cursor color data is programmed as an 8-bit index pointer into the 18-bit palette RAM for color data selection output to the LCD screen.
  • Page 109 Registers Write the RED_GREEN palette values to address 0xAA800042. Write the blue value to address 0xAA800044. The palette values are 6-bit numbers; the upper two unused bits are floating “don't care” values and can be either 1 or 0. Mask them when reading from addresses 0xAA800048 and 0xAA80004A.

  • Page 110: Starting Address Of Displayed Memory

    Registers Example Programs Starting Address of Displayed Memory Hardware Starting Address offset from ZERO beginning of frame buffer memory. // Set in the Frame buffer memory starting address offset from ZERO set_start_addr(int buffer_offset) short reg_upper2, reg_lower16, tmp2, tmp16; // print("Starting address offset "); putnum(buffer_offset); buffer_offset >>= 2;...

  • Page 111: System Iimplementation

    System Implementation This section contains detailed diagrams for system configuration. 4171A Companion Chip User’s Manual...
  • Page 112 System Implementation Figure 8-1. Single Slot: PC Card or CompactFlash with 68-Pin Adapter *A_WE *A_OE *A_IOW *A_IOR A_D[15:0] Slot A A_ADR[25:0] *A_CE[2:1] PC Card A_RESET SA[25:0] or 68-Pin *A_REG Compact *A_CD[2:1] SD[15:0] Flash A_BVD[2:1] *A_VS[2:1] with *SBHE *A_WAIT Adaptor *SIORD A_RDY/*A_BSY Interface *SIOWR...
  • Page 113 System Implementation Figure 8-2. Single Slot with 50-Pin CompactFlash *A_WE => *CF_WE *A_OE => *CF_OE *A_IOW => *CF_IOW *A_IOR => *CF_IOR A_D[15:0] => CF_D[15:0] A_ADR[10:0] => CF_ADR[10:0] Slot A SA[25:0] *A_CE[2:1] => *CF_CE[2:1] A_RESET => CF_RESET 50-Pin SD[15:0] *A_REG => *CF_REG Compact *A_CD[2:1] =>...
  • Page 114 System Implementation Figure 8-3. Dual Slots with Two PC Cards without External OR Gate *SMWR *A_WE *SMRD *A_OE *SIOWR *A_IOW *SIORD *A_IOR SA[25:0] SA[11:0] A_ADR[11:0] *A_ENBUF SD[15:0] SD[15:0] A_D[15:0] Slot A A_DBUFDIR 68-Pin *A_DBUFEN[1:0] Compact Flash A_ADR[25:12] with *A_CE[2:1] Adapter A_RESET Interface *A_REG...
  • Page 115 System Implementation Figure 8-4. Dual Slots with Two PC Cards and External OR Gate *SMWR *A_WE *SMRD *A_OE *SIOWR *A_IOW *SIORD *A_IOR SA[25:0] SA[11:0] A_ADR[11:0] *A_ENBUF SD[15:0] SD[15:0] A_D[15:0] Slot A A_DBUFDIR PCMCIA *A_CE[2] or 68-Pin Compact *A_CE[1] Flash with A_ADR[25:12] Adaptor *A_CE[2:1]...
  • Page 116 System Implementation Figure 8-5. Dual Slots: PC Card or 50-Pin CompactFlash without External OR Gate *SMWR *A_WE *SMRD *A_OE *SIOWR *A_IOW *SIORD *A_IOR SA[25:0] *A_ENBUF SD[15:0] SD[15:0] SD[15:0] A_D[15:0] Slot A A_DBUFDIR PCMCIA *A_DBUFEN[2:1] or 68-Pin Compact A_ADR[25:0] Flash *A_CE[2:1] with A_RESET Adaptor...
  • Page 117 System Implementation Figure 8-6. Dual Slots: PC Card and 50-Pin CompactFlash with External OR Gate *SMWR *A_WE *SMRD *A_OE *SIOWR *A_IOW *SIORD *A_IOR SA[25:0] *A_ENBUF SD[15:0] SD[15:0] A_D[15:0] A_DBUFDIR Slot A *A_CE[2] PCMCIA or 68-pin *A_CE[1] Compact Flash A_ADR[25:0] with *A_CE[2:1] Adaptor A_RESET...
  • Page 118 System Implementation Figure 8-7. Dual Slots: PC Card and 60-Pin Miniature Card *SMWR *A_WE *SMRD *A_OE *SIOWR *A_IOW *SIORD *A_IOR SA[25:0] SA[11:0] A_ADR[11:0] SD[15:0] A_D[15:0] SD[15:0] Slot A A_DBUFDIR PC Card *A_CE[2] or 68-pin *A_ENBUF Compact *A_CE[1] Flash with A_ADR[25:12] Adaptor *A_CE[2:1] Interface...

  • Page 119: Design Considerations

    Design Considerations At power-up, all signals to PC Card slots are tri-stated. To enable operation, the system must first write to Configuration Registers I and II to set up this device for system implementation. During Suspend mode or when the PC Card is not present, the PC Card slot is powered down and card V is at 0 volts.

  • Page 120: Single Slot With One 68-Pin Pc Card

    Design Considerations Single Slot With One 68-Pin PC Card Table 9-1. Pin Assignments for Slot A Pin Name I/O Type Function Functional Description Connect Pull-Up Pull-Up to Card to Card to SYS Slot √ A_RESET O–T/5V PC Card reset Provides a hard reset to PC Card and clears Card Configuration –...
  • Page 121 Design Considerations Table 9-2. Multifunction Pin Assignments for Slot A Pin Name Signal Name I/O Type Function Description Connect Pull-Up Pull-Up to Card to Card to SYS Slot √ MFP[35:24] A_ADR[11:0] O–T/5 V PC Card address bus Lower order address bus to PC Card; –...

  • Page 122: Dual Slots With Two 68-Pin Pc Cards

    Design Considerations Dual Slots With Two Pin assignments for slot A are the same as those described in Tables 9-1 through 9-3. 68-Pin PC Cards Pin assignments for slot B are described in Table 9-4. Table 9-4. Multifunction Pin Assignments for Slot B (with External OR Gates) Pin Name Signal Name I/O Type...
  • Page 123 Design Considerations Table 9-4. Multifunction Pin Assignments for Slot B (with External OR Gates) (continued) Pin Name Signal Name I/O Type Function Description Connect Pull-Up Pull-Up to Card to Card to SYS Slot MFP[5] *B_ENBUF O–5V Slot B PC Card address Active low signal controls external address Directly –...

  • Page 124: Dual Slots (A: 68-Pin Pc Card / B: 50-Pin Compactflash)

    Design Considerations Dual Slots (A: 68-Pin PC Card / B: 50-Pin CompactFlash) Table 9-6. Multifunction Pin Assignments for Slot B (with External OR Gates) Pin Name Signal Name I/O Type Function Description Connect Pull-Up Pull-Up to Card to Card to SYS Slot √...
  • Page 125 Design Considerations Table 9-6. Multifunction Pin Assignments for Slot B (with External OR Gates) (continued) Pin Name Signal Name I/O Type Function Description Connect Pull-Up Pull-Up to Card to Card to SYS Slot MFP[6] A_DBUFDIR O–5V Slot A PC Card direction High during a read from the PC Card slot Note 1 –...

  • Page 126: Dual Slots (A: 68-Pin Pc Card / B: 60-Pin Miniature Card)

    Design Considerations Dual Slots For Miniature Card applications, only ROM and flash ROM are supported for DRAMs (A: 68-Pin PC Card / and SRAMs. B: 60-Pin Miniature Card) Table 9-8. Multifunction Pin Assignments for Slot B (With External OR Gates) Pin Name Signal Name I/O Type...

  • Page 127: Package Specifications

    Package Specifications 4171A Companion Chip User’s Manual 10-1...
  • Page 128 Package Specifications Figure 10-1. 208-Pin LQFP ITEM MILLIMETERS INCHES 30.0±0.2 1.181±0.008 +0.009 28.0±0.2 1.102 –0.008 +0.009 28.0±0.2 1.102 –0.008 30.0±0.2 1.181±0.008 1.25 0.049 1.25 0.049 +0.05 0.22 0.009±0.002 –0.04 0.10 0.004 0.5 (T.P.) 0.020 (T.P.) +0.009 1.0±0.2 0.039 –0.008 0.020 +0.008 0.5±0.2 –0.009 +0.055...
  • Page 129 Some of the information contained in this document may vary from country to country. Before using any NEC product in your application, please contact a representative from the NEC office in your country to obtain a list of authorized representatives and...
  • Page 130 The quality grade of NEC devices is “Standard” unless otherwise specified in NEC’s data sheets or data books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.

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