Fujitsu SPARClite MB86860 Series Manuals

Manuals and User Guides for Fujitsu SPARClite MB86860 Series. We have 1 Fujitsu SPARClite MB86860 Series manual available for free PDF download: User Manual

Fujitsu SPARClite MB86860 Series User Manual (130 pages)

Brand: Fujitsu | Category: Computer Hardware | Size: 1 MB

Table of Contents
4
Introduction
7
Features
7
Core Part
7
Debug Support Function
7
Data Buffer Module
7
Address Conversion (TLB) Function (MB86861/MB86862)
7
SDRAM Interface
7
Sparclite Interface
8
Bus-Bridge DMA
8
Power Supply
8
Block Diagram
8
Pin Overview
11
MB86860 Pin Overview
11
MB86861 Pin Overview
14
Outer Package Dimension Drawing
16
Explanation of Pin Functions
17
Sparclite Bus Signals
17
SDRAM-IF Signals
23
Interrupt Signals
24
DMAC, DSU and Sleep Mode Related Signals
24
Other Signals
24
Test Signals
26
Registers
27
IU Status/Control Registers
27
Memory Mapped Registers
28
Processor Core
32
IU (Integer Unit)
34
Register Overview
34
Register Details
36
Caches
45
Cache Memory Assignments
45
Tag/Data Format
46
Operating Functions
47
DSU (Debug Support Unit)
48
Related Pin Overview
48
Register Overview
49
Register Details
49
Explanation of Functions
51
Low Power Consumption Mode
55
Related Pin Overview
55
Register Overview
55
Register Details
55
Explanation of Functions
57
Items Requiring Attention in Sleep Mode
59
Tlb
60
Register Overview
61
Register Details
63
TLB Control Register (TCR)
63
Virtual Word Address Entry Register (VWE0-15)
63
Physical Word Address Entry Register (PWE0-15)
63
Operating Functions
64
Data Buffer Unit
67
Register Overview
68
Register Details
68
Buffer Control Register
70
Operating Functions
70
Instruction Buffers (IB)
70
Read Buffers (RB)
70
Write Buffers (WB)
70
Buffer Link Policy
72
Tag Format
73
Sparclite Bus Interface
75
Register Overview
75
Register Details
76
Address Range Specifier Registers (ARSR0-5)
76
Address Mask Registers (AMR0-5)
76
Wait State Specifier Registers (WSSR0-5)
77
MEXC Parity Error Control Registers (MXPEF)
79
MEXC Parity Error Control Registers
79
Idle Cycle Control Register
80
Operating Functions
81
Operations When CPU Has the Bus Right
81
Access Transparent Mode to SDRAM (MB86861 Only)
93
Sdram-If
99
Pin Overview
99
Register Overview
100
Register Details
101
SDRAM Address Range Specifier Registers (SDARSR0-5)
101
SDRAM Address Mask Registers (SDAMR0-1)
101
SDRAM Configuration Register (SDCFG)
102
Auto Refresh Register (ART)
102
SDRAM Status Register (SSR)
104
SDRAM CS Characteristic Registers (CSCR0-3) (MB86861 Only)
104
SDRAM Start Address Registers (SSAR0-3) (MB86861 Only)
106
SDRAM Address Mask Registers SAMR0-3) (MB86861 Only)
106
Operating Functions
107
SDRAM Connections with SDRAM Buses
107
Timing Diagram
113
Dmac
123
Related Pin Overview
123
Register Overview
123
DMA Control Registers (DCR0-1)
123
DMA Source Address Register
124
DMA Destination Address Register
126
DMA Word Length Register
126
Operating Functions
126
Internal Bus Priority Order
126
Transfer System
128
Register Summary
128
Activation/Termination
128
Exception Processing
128

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Fujitsu SPARClite MB86860 Series Manuals

Fujitsu SPARClite MB86860 Series User Manual (130 pages)

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