Renesas RA4W1 Manuals

Manuals and User Guides for Renesas RA4W1. We have 2 Renesas RA4W1 manuals available for free PDF download: User Manual, Application Note

Renesas RA4W1 User Manual (1317 pages)

32-bit MCU

Brand: Renesas | Category: Microcontrollers | Size: 17 MB

Table of Contents
9
Features

47
1 Overview

48
- Function Outline
  48
- Block Diagram
  54
- Part Numbering
  54
- Function Comparison
  56
- Pin Functions
  57
- Pin Assignments
  60
- Pin Lists
  61
2 Cpu

64
- Overview
  64
  - Debug
    64
  - Operating Frequency
    65
- MCU Implementation Options
  66
- Trace Interface
  66
- JTAG/SWD Interface
  67
- Debug Mode
  67
  - Debug Mode Definition
    67
  - Debug Mode Effects
    67
    
    Low Power Mode
    67
    
    Reset
    67
- Programmers Model
  68
  - Address Spaces
    68
  - Cortex-M4 Peripheral Address Map
    68
  - Coresight ROM Table
    69
    
    ROM Entries
    69
    
    Coresight Component Registers
    69
  - DBGREG Module
    70
    
    Debug Status Register (DBGSTR)
    70
    
    Debug Stop Control Register (DBGSTOPCR)
    71
    
    Trace Control Register (TRACECTR)
    71
    
    DBGREG Coresight Component Registers
    72
  - OCDREG Module
    72
    
    ID Authentication Code Register (IAUTH0 to 3)
    72
    
    MCU Status Register (MCUSTAT)
    73
    
    MCU Control Register (MCUCTRL)
    74
    
    OCDREG Coresight Component Registers
    74
- Coresight ATB Funnel
  75
- Flash Patch and Break Unit
  75
- Systick System Timer
  75
- Coresight Time Stamp Generator
  75
- OCD Emulator Connection
  75
- References
  78
3 Operating Modes

79
- Overview
  79
- Details of Operating Modes
  79
  - Single-Chip Mode
    79
  - SCI Boot Mode
    79
  - USB Boot Mode
    79
- Operating Mode Transitions
  79
  - Operating Mode Transitions as Determined by the Mode-Setting Pin
    79
4 Address Space

80
- Overview
  80
5 Memory Mirror Function (MMF)

81
- Overview
  81
- Register Descriptions
  81
  - Memmirror Special Function Register (MMSFR)
    81
  - Memmirror Enable Register (MMEN)
    82
- Operation
  82
  - MMF Operation
    82
  - Setting Example
    86
6 Resets

87
- Overview
  87
- Register Descriptions
  90
- Operation
  94
  - RES Pin Reset
    94
  - Power-On Reset
    94
  - Voltage Monitor Reset
    95
  - Independent Watchdog Timer Reset
    96
  - Watchdog Timer Reset
    96
  - Software Reset
    97
  - Determination of Cold/Warm Start
    97
  - Determination of Reset Generation Source
    97
7 Option-Setting Memory

99
8 Low Voltage Detection (LVD)

109
9 Clock Generation Circuit

117
10 Clock Frequency Accuracy Measurement Circuit (CAC)

151
- Overview
  151
- Register Descriptions
  152
- Operation
  157
  - Measuring Clock Frequency
    157
  - Digital Filtering of Signals on CACREF Pin
    158
- Interrupt Requests
  159
- Usage Note
  159
  - Settings for the Module-Stop Function
    159
11 Low Power Modes

160
- Overview
  160
- Register Descriptions
  163
- Reducing Power Consumption by Switching Clock Signals
  174
- Module-Stop Function
  174
- Function for Lower Operating Power Consumption
  174
  - Setting Operating Power Control Mode
    174
  - Operating Range
    176
- Sleep Mode
  179
  - Transition to Sleep Mode
    179
  - Canceling Sleep Mode
    179
- Software Standby Mode
  180
- Snooze Mode
  183
  - Transition to Snooze Mode
    183
  - Canceling Snooze Mode
    183
  - Return to Software Standby Mode
    184
  - Snooze Operation Example
    186
- Usage Notes
  189
  - Register Access
    189
  - I/O Port States
    190
  - Module-Stop State of DMAC and DTC
    190
  - Internal Interrupt Sources
    190
  - Transition to Low Power Modes
    190
  - Timing of WFI Instruction
    191
  - Writing WDT/IWDT Registers by DMAC or DTC in Sleep Mode or Snooze Mode
    191
  - Oscillators in Snooze Mode
    191
  - Snooze Mode Entry by RXD0 Falling Edge
    191
  - Using SCI0 in Snooze Mode
    191
  - Conditions of A/D Conversion Start in Snooze Mode
    191
  - Conditions of CTSU in Snooze Mode
    191
  - ELC Event in Snooze Mode
    191
  - Module-Stop Function for ADC140
    192
  - Module-Stop Function for an Unused Circuit
    192
12 Battery Backup Function

193
13 Register Write Protection

209
- Overview
  209
- Register Descriptions
  209
  - Protect Register (PRCR)
    209
14 Interrupt Controller Unit (ICU)

210
- Overview
  210
- Register Descriptions
  211
- Vector Table
  223
  - Interrupt Vector Table
    223
  - Event Number
    224
- Interrupt Operation
  229
  - Detecting Interrupts
    229
  - Selecting Interrupt Request Destinations
    230
    
    CPU Interrupt Request
    230
    
    DTC Activation
    230
    
    DMAC Activation
    231
  - Digital Filter
    231
  - External Pin Interrupts
    232
- Non-Maskable Interrupt Operation
  232
- Return from Low Power Mode
  233
  - Return from Sleep Mode
    233
  - Return from Software Standby Mode
    233
  - Return from Snooze Mode
    233
- Using the WFI Instruction with Non-Maskable Interrupts
  234
- Reference
  234
15 Buses

235
- Overview
  235
- Description of Buses
  236
  - Main Buses
    236
  - Slave Interface
    236
  - Parallel Operation
    236
  - Restriction on Endianness
    237
- Register Descriptions
  237
- Bus Error Monitoring Section
  240
  - Error Type that Occurs by Bus
    240
  - Operation When a Bus Error Occurs
    240
  - Conditions Leading to Illegal Address Access Errors
    241
  - Timeout
    241
- Notes on Using Flash Cache
  242
- References
  242
16 Memory Protection Unit (MPU)

243
17 DMA Controller (DMAC)

274
- Overview
  274
- Register Descriptions
  276
- Operation
  285
  - Transfer Mode
    285
  - Extended Repeat Area Function
    288
  - Address Update Function Using Offset
    290
  - Activation Sources
    294
  - Operation Timing
    294
  - Execution Cycles of DMAC
    295
  - Activating DMAC
    295
  - Starting DMA Transfer
    297
  - Registers During DMA Transfer
    297
  - Channel Priority
    298
- Ending DMA Transfer
  298
- Interrupts
  299
- Event Link
  300
- Low Power Consumption Function
  300
- Usage Notes
  301
18 Data Transfer Controller (DTC)

302
- Overview
  302
- Register Descriptions
  303
  - DTC Mode Register a (MRA)
    304
  - DTC Mode Register B (MRB)
    304
  - DTC Transfer Source Register (SAR)
    305
  - DTC Transfer Destination Register (DAR)
    306
  - DTC Transfer Count Register a (CRA)
    306
  - DTC Transfer Count Register B (CRB)
    307
  - DTC Control Register (DTCCR)
    307
  - DTC Vector Base Register (DTCVBR)
    308
  - DTC Module Start Register (DTCST)
    308
  - DTC Status Register (DTCSTS)
    309
- Activation Sources
  309
  - Allocating Transfer Information and DTC Vector Table
    310
- Operation
  311
  - Transfer Information Read Skip Function
    313
  - Transfer Information Write-Back Skip Function
    313
  - Normal Transfer Mode
    314
  - Repeat Transfer Mode
    315
  - Block Transfer Mode
    316
  - Chain Transfer
    317
  - Operation Timing
    318
  - Execution Cycles of DTC
    320
  - DTC Bus Mastership Release Timing
    320
- DTC Setting Procedure
  320
- Examples of DTC Usage
  321
  - Normal Transfer
    321
  - Chain Transfer
    322
  - Chain Transfer When Counter = 0
    324
- Interrupt Source
  325
- Event Link
  325
- Snooze Control Interface
  325
- Module-Stop Function
  325
- 18.11 Usage Notes
  326
  - Transfer Information Start Address
    326
19 Event Link Controller (ELC)

327
- Overview
  327
- Register Descriptions
  328
- Operation
  333
- Usage Notes
  334
  - Linking DMAC or DTC Transfer End Signals as Events
    334
  - Setting Clocks
    334
  - Module-Stop Function Setting
    334
  - ELC Delay Time
    334
20 I/O Ports

335
21 Key Interrupt Function (KINT)

355
- Overview
  355
- Register Descriptions
  357
- Operation
  358
  - Operation When Not Using Key Interrupt Flag (KRMD = 0)
    358
  - Operation When Using Key Interrupt Flag (KRMD = 1)
    358
- Usage Notes
  360
22 Port Output Enable for GPT (POEG)

361
- Overview
  361
- Register Descriptions
  362
  - POEG Group N Setting Register (Poeggn) (N = A, B)
    362
- Output-Disable Control Operation
  363
- Interrupt Sources
  365
- External Trigger Output to GPT
  365
- Usage Notes
  366
  - Transition to Software Standby Mode
    366
  - Specifying Pins Associated with the GPT
    366
23 General PWM Timer (GPT)

367
24 Asynchronous General Purpose Timer (AGT)

489
- Overview
  489
- Register Descriptions
  491
- Operation
  498
  - Reload Register and Counter Rewrite Operation
    498
  - Reload Register and Compare Register A/B Rewrite Operation
    499
  - Timer Mode
    500
  - Pulse Output Mode
    501
  - Event Counter Mode
    502
  - Pulse Width Measurement Mode
    503
  - Pulse Period Measurement Mode
    504
  - Compare Match Function
    505
  - Output Settings for each Mode
    507
  - Standby Mode
    507
  - Interrupt Sources
    508
  - Event Signal Output to ELC
    508
- Usage Notes
  508
25 Realtime Clock (RTC)

511
26 Watchdog Timer (WDT)

550
- Overview
  550
- Register Descriptions
  551
- Operation
  556
  - Count Operation in each Start Mode
    556
    
    Register Start Mode
    556
    
    Auto Start Mode
    558
  - Controlling Writes to the WDTCR, WDTRCR, and WDTCSTPR Registers
    559
  - Refresh Operation
    560
  - Reset Output
    561
  - Interrupt Sources
    561
  - Reading the Down-Counter Value
    561
  - Associations between Option Function Select Register 0 (OFS0) and WDT Registers
    562
- Link Operation by ELC
  562
- Usage Notes
  562
  - ICU Event Link Setting Register N (Ielsrn) Setting
    562
27 Independent Watchdog Timer (IWDT)

563
- Overview
  563
- Register Descriptions
  564
- Operation
  568
  - Auto Start Mode
    568
  - Refresh Operation
    569
  - Status Flags
    570
  - Reset Output
    571
  - Interrupt Sources
    571
  - Reading the Down-Counter Value
    571
- Link Operation by ELC
  571
- Usage Notes
  572
  - Refresh Operations
    572
  - Clock Division Ratio Setting
    572
28 USB 2.0 Full-Speed Module (USBFS)

573
- Overview
  573
- Register Descriptions
  575
- Operation
  620
  - System Control
    620
    
    Setting Data to the USBFS-Related Registers
    620
    
    Selecting the Controller Function
    620
    
    Controlling the USBFS Data Bus Using Resistors
    620
    
    Example of USB External Connection Circuits
    621
  - Interrupt Sources
    625
  - Interrupt Descriptions
    629
    
    BRDY Interrupt
    629
    
    NRDY Interrupt
    632
    
    BEMP Interrupt
    634
    
    Device State Transition Interrupt (Device Controller Mode)
    635
    
    Control Transfer Stage Transition Interrupt (Device Controller Mode)
    636
    
    Frame Update Interrupt
    637
    
    VBUS Interrupt
    637
    
    Resume Interrupt
    638
    
    OVRCR Interrupt
    638
    
    BCHG Interrupt
    638
    
    DTCH Interrupt
    638
    
    SACK Interrupt
    638
    
    SIGN Interrupt
    638
    
    ATTCH Interrupt
    638
    
    EOFERR Interrupt
    638
    
    Portable Device Detection Interrupt
    639
  - Pipe Control
    639
    
    Pipe Control Register Switching Procedures
    639
    
    Transfer Types
    640
    
    Endpoint Number
    640
    
    Maximum Packet Size Setting
    640
    
    Transaction Counter for Pipes 1 to 5 in the Receiving Direction
    640
    
    Response PID
    641
    
    Data PID Sequence Bit
    642
    
    Response PID = NAK Function
    642
    
    Auto Response Mode
    642
    
    OUT-NAK Mode
    642
    
    Null Auto Response Mode
    643
  - FIFO Buffer Memory
    643
  - FIFO Buffer Clearing
    643
  - FIFO Port Functions
    644
  - DMA Transfers (D0FIFO and D1FIFO Ports)
    645
  - Control Transfers Using DCP
    645
    
    Control Transfers in Host Controller Mode
    646
    
    Control Transfers in Device Controller Mode
    646
  - Bulk Transfers (Pipes 1 to 5)
    647
  - Interrupt Transfers (Pipes 6 to 9)
    647
    
    Interval Counter for Interrupt Transfers in Host Controller Mode
    648
  - Isochronous Transfers (Pipes 1 and 2)
    648
    
    Error Detection in Isochronous Transfers
    648
    
    Data-Pid
    649
    
    Interval Counter
    649
  - SOF Interpolation Function
    655
  - Pipe Schedule
    655
    
    Conditions for Generating Transactions
    655
    
    Transfer Schedule
    656
    
    Enabling USB Communication
    656
  - Battery Charging Detection Processing
    656
    
    Processing in Device Controller Mode
    656
    
    Processing When Host Controller Is Selected
    658
- Usage Notes
  661

Renesas RA4W1 Application Note (20 pages)

Guidelines for 2.4 GHz Wireless Board Design

Brand: Renesas | Category: Motherboard | Size: 0 MB

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Computer Hardware Motherboard Microcontrollers Adapter

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Renesas RA4W1 Manuals

Renesas RA4W1 User Manual (1317 pages)

Table of Contents

Features

1 Overview

2 Cpu

3 Operating Modes

4 Address Space

5 Memory Mirror Function (MMF)

6 Resets

7 Option-Setting Memory

8 Low Voltage Detection (LVD)

9 Clock Generation Circuit

10 Clock Frequency Accuracy Measurement Circuit (CAC)

11 Low Power Modes

12 Battery Backup Function

13 Register Write Protection

14 Interrupt Controller Unit (ICU)

15 Buses

16 Memory Protection Unit (MPU)

17 DMA Controller (DMAC)

18 Data Transfer Controller (DTC)

19 Event Link Controller (ELC)

20 I/O Ports

21 Key Interrupt Function (KINT)

22 Port Output Enable for GPT (POEG)

23 General PWM Timer (GPT)

24 Asynchronous General Purpose Timer (AGT)

25 Realtime Clock (RTC)

26 Watchdog Timer (WDT)

27 Independent Watchdog Timer (IWDT)

28 USB 2.0 Full-Speed Module (USBFS)

Renesas RA4W1 Application Note (20 pages)

Table of Contents

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