Renesas RTK7EKA4W1S00000BJ Manuals

Manuals and User Guides for Renesas RTK7EKA4W1S00000BJ. We have 1 Renesas RTK7EKA4W1S00000BJ manual available for free PDF download: User Manual

Renesas RTK7EKA4W1S00000BJ User Manual (1317 pages)

32-bit MCU

Brand: Renesas | Category: Microcontrollers | Size: 17 MB

Table of Contents
9
Features

47
1 Overview

48
- Function Outline
  48
- Block Diagram
  54
- Part Numbering
  54
- Function Comparison
  56
- Pin Functions
  57
- Pin Assignments
  60
- Pin Lists
  61
2 Cpu

64
- Overview
  64
  - Debug
    64
  - Operating Frequency
    65
- MCU Implementation Options
  66
- Trace Interface
  66
- JTAG/SWD Interface
  67
- Debug Mode
  67
  - Debug Mode Definition
    67
  - Debug Mode Effects
    67
    
    Low Power Mode
    67
    
    Reset
    67
- Programmers Model
  68
  - Address Spaces
    68
  - Cortex-M4 Peripheral Address Map
    68
  - Coresight ROM Table
    69
    
    ROM Entries
    69
    
    Coresight Component Registers
    69
  - DBGREG Module
    70
    
    Debug Status Register (DBGSTR)
    70
    
    Debug Stop Control Register (DBGSTOPCR)
    71
    
    Trace Control Register (TRACECTR)
    71
    
    DBGREG Coresight Component Registers
    72
  - OCDREG Module
    72
    
    ID Authentication Code Register (IAUTH0 to 3)
    72
    
    MCU Status Register (MCUSTAT)
    73
    
    MCU Control Register (MCUCTRL)
    74
    
    OCDREG Coresight Component Registers
    74
- Coresight ATB Funnel
  75
- Flash Patch and Break Unit
  75
- Systick System Timer
  75
- Coresight Time Stamp Generator
  75
- OCD Emulator Connection
  75
- References
  78
3 Operating Modes

79
- Overview
  79
- Details of Operating Modes
  79
  - Single-Chip Mode
    79
  - SCI Boot Mode
    79
  - USB Boot Mode
    79
- Operating Mode Transitions
  79
  - Operating Mode Transitions as Determined by the Mode-Setting Pin
    79
4 Address Space

80
- Overview
  80
5 Memory Mirror Function (MMF)

81
- Overview
  81
- Register Descriptions
  81
  - Memmirror Special Function Register (MMSFR)
    81
  - Memmirror Enable Register (MMEN)
    82
- Operation
  82
  - MMF Operation
    82
  - Setting Example
    86
6 Resets

87
- Overview
  87
- Register Descriptions
  90
- Operation
  94
  - RES Pin Reset
    94
  - Power-On Reset
    94
  - Voltage Monitor Reset
    95
  - Independent Watchdog Timer Reset
    96
  - Watchdog Timer Reset
    96
  - Software Reset
    97
  - Determination of Cold/Warm Start
    97
  - Determination of Reset Generation Source
    97
7 Option-Setting Memory

99
8 Low Voltage Detection (LVD)

109
9 Clock Generation Circuit

117
10 Clock Frequency Accuracy Measurement Circuit (CAC)

151
- Overview
  151
- Register Descriptions
  152
- Operation
  157
  - Measuring Clock Frequency
    157
  - Digital Filtering of Signals on CACREF Pin
    158
- Interrupt Requests
  159
- Usage Note
  159
  - Settings for the Module-Stop Function
    159
11 Low Power Modes

160
- Overview
  160
- Register Descriptions
  163
- Reducing Power Consumption by Switching Clock Signals
  174
- Module-Stop Function
  174
- Function for Lower Operating Power Consumption
  174
  - Setting Operating Power Control Mode
    174
  - Operating Range
    176
- Sleep Mode
  179
  - Transition to Sleep Mode
    179
  - Canceling Sleep Mode
    179
- Software Standby Mode
  180
- Snooze Mode
  183
  - Transition to Snooze Mode
    183
  - Canceling Snooze Mode
    183
  - Return to Software Standby Mode
    184
  - Snooze Operation Example
    186
- Usage Notes
  189
  - Register Access
    189
  - I/O Port States
    190
  - Module-Stop State of DMAC and DTC
    190
  - Internal Interrupt Sources
    190
  - Transition to Low Power Modes
    190
  - Timing of WFI Instruction
    191
  - Writing WDT/IWDT Registers by DMAC or DTC in Sleep Mode or Snooze Mode
    191
  - Oscillators in Snooze Mode
    191
  - Snooze Mode Entry by RXD0 Falling Edge
    191
  - Using SCI0 in Snooze Mode
    191
  - Conditions of A/D Conversion Start in Snooze Mode
    191
  - Conditions of CTSU in Snooze Mode
    191
  - ELC Event in Snooze Mode
    191
  - Module-Stop Function for ADC140
    192
  - Module-Stop Function for an Unused Circuit
    192
12 Battery Backup Function

193
13 Register Write Protection

209
- Overview
  209
- Register Descriptions
  209
  - Protect Register (PRCR)
    209
14 Interrupt Controller Unit (ICU)

210
- Overview
  210
- Register Descriptions
  211
- Vector Table
  223
  - Interrupt Vector Table
    223
  - Event Number
    224
- Interrupt Operation
  229
  - Detecting Interrupts
    229
  - Selecting Interrupt Request Destinations
    230
    
    CPU Interrupt Request
    230
    
    DTC Activation
    230
    
    DMAC Activation
    231
  - Digital Filter
    231
  - External Pin Interrupts
    232
- Non-Maskable Interrupt Operation
  232
- Return from Low Power Mode
  233
  - Return from Sleep Mode
    233
  - Return from Software Standby Mode
    233
  - Return from Snooze Mode
    233
- Using the WFI Instruction with Non-Maskable Interrupts
  234
- Reference
  234
15 Buses

235
- Overview
  235
- Description of Buses
  236
  - Main Buses
    236
  - Slave Interface
    236
  - Parallel Operation
    236
  - Restriction on Endianness
    237
- Register Descriptions
  237
- Bus Error Monitoring Section
  240
  - Error Type that Occurs by Bus
    240
  - Operation When a Bus Error Occurs
    240
  - Conditions Leading to Illegal Address Access Errors
    241
  - Timeout
    241
- Notes on Using Flash Cache
  242
- References
  242
16 Memory Protection Unit (MPU)

243
17 DMA Controller (DMAC)

274
- Overview
  274
- Register Descriptions
  276
- Operation
  285
  - Transfer Mode
    285
  - Extended Repeat Area Function
    288
  - Address Update Function Using Offset
    290
  - Activation Sources
    294
  - Operation Timing
    294
  - Execution Cycles of DMAC
    295
  - Activating DMAC
    295
  - Starting DMA Transfer
    297
  - Registers During DMA Transfer
    297
  - Channel Priority
    298
- Ending DMA Transfer
  298
- Interrupts
  299
- Event Link
  300
- Low Power Consumption Function
  300
- Usage Notes
  301
18 Data Transfer Controller (DTC)

302
- Overview
  302
- Register Descriptions
  303
  - DTC Mode Register a (MRA)
    304
  - DTC Mode Register B (MRB)
    304
  - DTC Transfer Source Register (SAR)
    305
  - DTC Transfer Destination Register (DAR)
    306
  - DTC Transfer Count Register a (CRA)
    306
  - DTC Transfer Count Register B (CRB)
    307
  - DTC Control Register (DTCCR)
    307
  - DTC Vector Base Register (DTCVBR)
    308
  - DTC Module Start Register (DTCST)
    308
  - DTC Status Register (DTCSTS)
    309
- Activation Sources
  309
  - Allocating Transfer Information and DTC Vector Table
    310
- Operation
  311
  - Transfer Information Read Skip Function
    313
  - Transfer Information Write-Back Skip Function
    313
  - Normal Transfer Mode
    314
  - Repeat Transfer Mode
    315
  - Block Transfer Mode
    316
  - Chain Transfer
    317
  - Operation Timing
    318
  - Execution Cycles of DTC
    320
  - DTC Bus Mastership Release Timing
    320
- DTC Setting Procedure
  320
- Examples of DTC Usage
  321
  - Normal Transfer
    321
  - Chain Transfer
    322
  - Chain Transfer When Counter = 0
    324
- Interrupt Source
  325
- Event Link
  325
- Snooze Control Interface
  325
- Module-Stop Function
  325
- 18.11 Usage Notes
  326
  - Transfer Information Start Address
    326
19 Event Link Controller (ELC)

327
- Overview
  327
- Register Descriptions
  328
- Operation
  333
- Usage Notes
  334
  - Linking DMAC or DTC Transfer End Signals as Events
    334
  - Setting Clocks
    334
  - Module-Stop Function Setting
    334
  - ELC Delay Time
    334
20 I/O Ports

335
21 Key Interrupt Function (KINT)

355
- Overview
  355
- Register Descriptions
  357
- Operation
  358
  - Operation When Not Using Key Interrupt Flag (KRMD = 0)
    358
  - Operation When Using Key Interrupt Flag (KRMD = 1)
    358
- Usage Notes
  360
22 Port Output Enable for GPT (POEG)

361
- Overview
  361
- Register Descriptions
  362
  - POEG Group N Setting Register (Poeggn) (N = A, B)
    362
- Output-Disable Control Operation
  363
- Interrupt Sources
  365
- External Trigger Output to GPT
  365
- Usage Notes
  366
  - Transition to Software Standby Mode
    366
  - Specifying Pins Associated with the GPT
    366
23 General PWM Timer (GPT)

367
24 Asynchronous General Purpose Timer (AGT)

489
- Overview
  489
- Register Descriptions
  491
- Operation
  498
  - Reload Register and Counter Rewrite Operation
    498
  - Reload Register and Compare Register A/B Rewrite Operation
    499
  - Timer Mode
    500
  - Pulse Output Mode
    501
  - Event Counter Mode
    502
  - Pulse Width Measurement Mode
    503
  - Pulse Period Measurement Mode
    504
  - Compare Match Function
    505
  - Output Settings for each Mode
    507
  - Standby Mode
    507
  - Interrupt Sources
    508
  - Event Signal Output to ELC
    508
- Usage Notes
  508
25 Realtime Clock (RTC)

511
26 Watchdog Timer (WDT)

550
- Overview
  550
- Register Descriptions
  551
- Operation
  556
  - Count Operation in each Start Mode
    556
    
    Register Start Mode
    556
    
    Auto Start Mode
    558
  - Controlling Writes to the WDTCR, WDTRCR, and WDTCSTPR Registers
    559
  - Refresh Operation
    560
  - Reset Output
    561
  - Interrupt Sources
    561
  - Reading the Down-Counter Value
    561
  - Associations between Option Function Select Register 0 (OFS0) and WDT Registers
    562
- Link Operation by ELC
  562
- Usage Notes
  562
  - ICU Event Link Setting Register N (Ielsrn) Setting
    562
27 Independent Watchdog Timer (IWDT)

563
- Overview
  563
- Register Descriptions
  564
- Operation
  568
  - Auto Start Mode
    568
  - Refresh Operation
    569
  - Status Flags
    570
  - Reset Output
    571
  - Interrupt Sources
    571
  - Reading the Down-Counter Value
    571
- Link Operation by ELC
  571
- Usage Notes
  572
  - Refresh Operations
    572
  - Clock Division Ratio Setting
    572
28 USB 2.0 Full-Speed Module (USBFS)

573
- Overview
  573
- Register Descriptions
  575
- Operation
  620
  - System Control
    620
    
    Setting Data to the USBFS-Related Registers
    620
    
    Selecting the Controller Function
    620
    
    Controlling the USBFS Data Bus Using Resistors
    620
    
    Example of USB External Connection Circuits
    621
  - Interrupt Sources
    625
  - Interrupt Descriptions
    629
    
    BRDY Interrupt
    629
    
    NRDY Interrupt
    632
    
    BEMP Interrupt
    634
    
    Device State Transition Interrupt (Device Controller Mode)
    635
    
    Control Transfer Stage Transition Interrupt (Device Controller Mode)
    636
    
    Frame Update Interrupt
    637
    
    VBUS Interrupt
    637
    
    Resume Interrupt
    638
    
    OVRCR Interrupt
    638
    
    BCHG Interrupt
    638
    
    DTCH Interrupt
    638
    
    SACK Interrupt
    638
    
    SIGN Interrupt
    638
    
    ATTCH Interrupt
    638
    
    EOFERR Interrupt
    638
    
    Portable Device Detection Interrupt
    639
  - Pipe Control
    639
    
    Pipe Control Register Switching Procedures
    639
    
    Transfer Types
    640
    
    Endpoint Number
    640
    
    Maximum Packet Size Setting
    640
    
    Transaction Counter for Pipes 1 to 5 in the Receiving Direction
    640
    
    Response PID
    641
    
    Data PID Sequence Bit
    642
    
    Response PID = NAK Function
    642
    
    Auto Response Mode
    642
    
    OUT-NAK Mode
    642
    
    Null Auto Response Mode
    643
  - FIFO Buffer Memory
    643
  - FIFO Buffer Clearing
    643
  - FIFO Port Functions
    644
  - DMA Transfers (D0FIFO and D1FIFO Ports)
    645
  - Control Transfers Using DCP
    645
    
    Control Transfers in Host Controller Mode
    646
    
    Control Transfers in Device Controller Mode
    646
  - Bulk Transfers (Pipes 1 to 5)
    647
  - Interrupt Transfers (Pipes 6 to 9)
    647
    
    Interval Counter for Interrupt Transfers in Host Controller Mode
    648
  - Isochronous Transfers (Pipes 1 and 2)
    648
    
    Error Detection in Isochronous Transfers
    648
    
    Data-Pid
    649
    
    Interval Counter
    649
  - SOF Interpolation Function
    655
  - Pipe Schedule
    655
    
    Conditions for Generating Transactions
    655
    
    Transfer Schedule
    656
    
    Enabling USB Communication
    656
  - Battery Charging Detection Processing
    656
    
    Processing in Device Controller Mode
    656
    
    Processing When Host Controller Is Selected
    658
- Usage Notes
  661
29 Serial Communications Interface (SCI)

663
1 I 2 C Bus Interface (IIC)

791
- Overview
  791
- Register Descriptions
  794
- Operation
  817
  - Communication Data Format
    817
  - Initial Settings
    818
  - Master Transmit Operation
    819
  - Master Receive Operation
    823
  - Slave Transmit Operation
    828
  - Slave Receive Operation
    831
- SCL Synchronization Circuit
  833
- SDA Output Delay Function
  834
- Digital Noise Filter Circuits
  834
- Address Match Detection
  835
  - Slave-Address Match Detection
    835
  - Detection of General Call Address
    837
  - Device ID Address Detection
    838
  - Host Address Detection
    839
- Wakeup Function
  840
- Automatic Low-Hold Function for SCL
  849
- 30.10 Arbitration-Lost Detection Functions
  852
- 30.11 Start, Restart, and Stop Condition Issuing Function
  856
  - Issuing a Start Condition
    856
  - Issuing a Restart Condition
    856
  - Issuing a Stop Condition
    858
- 30.12 Bus Hanging
  859
  - Timeout Function
    859
  - Extra SCL Clock Cycle Output Function
    860
  - IIC Reset and Internal Reset
    861
- 30.13 Smbus Operation
  861
- 30.14 Interrupt Sources
  863
  - Buffer Operation for Iicn_Txi and Iicn_Rxi Interrupts
    864
- 30.15 State of Registers When Issuing each Condition
  864
- 30.16 Event Link Output
  865
  - Interrupt Handling and Event Linking
    865
- 30.17 Usage Notes
  865
  - Settings for the Module-Stop State
    865
  - Notes on Starting Transfer
    865
31 Controller Area Network (CAN) Module

866
- Overview
  866
- Register Descriptions
  868
- Modes of Operation
  901
  - CAN Reset Mode
    901
  - CAN Halt Mode
    902
  - CAN Sleep Mode
    903
  - CAN Operation Mode (Excluding Bus-Off State)
    903
  - CAN Operation Mode (Bus-Off State)
    904
- Data Transfer Rate Configuration
  905
  - Clock Setting
    905
  - Bit Time Setting
    905
  - Data Transfer Rate
    905
- Mailbox and Mask Register Structure
  906
- Acceptance Filtering and Masking Functions
  907
- Reception and Transmission
  909
  - Reception
    910
  - Transmission
    911
- Interrupt
  912
- Usage Notes
  913
  - Settings for the Module-Stop State
    913
  - Settings for the Operating Clock
    913
32 Serial Peripheral Interface (SPI)

914
- Overview
  914
- Register Descriptions
  917
- Operation
  936
  - Overview of SPI Operations
    936
  - Controlling the SPI Pins
    937
  - SPI System Configuration Examples
    938
    
    Single Master and Single Slave with the MCU Configured as a Master
    938
    
    Single Master and Single Slave with the MCU Configured as a Slave
    938
    
    Single-Master and Multi-Slave with the MCU Configured as a Master
    939
    
    Single Master and Multi-Slave with the MCU Configured as a Slave
    940
    
    Multi-Master and Multi-Slave with the MCU Configured as a Master
    941
    
    Master and Slave in Clock Synchronous Mode with the MCU Configured as
    942
    
    Master and Slave in Clock Synchronous Mode with the MCU Configured as
    943
  - Data Format
    943
    
    Operation When Parity Is Disabled (SPCR2.SPPE = 0)
    944
    
    When Parity Is Enabled (SPCR2.SPPE = 1)
    948
  - Transfer Format
    952
    
    Cpha = 0
    952
    
    Cpha = 1
    953
  - Data Transfer Modes
    954
    
    Full-Duplex Synchronous Serial Communications (SPCR.TXMD = 0)
    954
    
    Transmit-Only Operations (SPCR.TXMD = 1)
    955
  - Transmit Buffer Empty and Receive Buffer Full Interrupts
    955
  - Error Detection
    957
    
    Overrun Errors
    958
    
    Parity Errors
    960
    
    Mode Fault Errors
    961
    
    Underrun Errors
    961
  - Initializing the SPI
    962
    
    Initialization by Clearing the SPE Bit
    962
    
    Initialization by System Reset
    962
  - SPI Operation
    962
    
    Master Mode Operation
    962
    
    Slave Mode Operation
    973
  - Clock Synchronous Operation
    977
    
    Master Mode Operation
    977
    
    Slave Mode Operation
    984
  - Loopback Mode
    985
  - Self-Diagnosis of Parity Bit Function
    986
  - Interrupt Sources
    987
- Event Link Operation
  988
- Usage Notes
  990
33 Cyclic Redundancy Check (CRC) Calculator

991
- Overview
  991
- Register Descriptions
  992
- Operation
  994
  - Basic Operation
    994
  - CRC Snoop
    997
- Usage Notes
  998
  - Settings for the Module-Stop State
    998
  - Notes on Transmission
    998
34 14-Bit A/D Converter (ADC14)

999
35 12-Bit D/A Converter (DAC12)

1071
- Overview
  1071
- Register Descriptions
  1072
  - D/A Data Register 0 (DADR0)
    1072
  - D/A Control Register (DACR)
    1072
  - DADR0 Format Select Register (DADPR)
    1073
  - D/A A/D Synchronous Start Control Register (DAADSCR)
    1073
  - D/A VREF Control Register (DAVREFCR)
    1074
- Operation
  1074
  - Reducing Interference between D/A and A/D Conversion
    1075
  - Notes on Using the Internal Reference Voltage as the Reference Voltage
    1077
- Event Link Operation Setting Procedure
  1077
- Usage Notes on Event Link Operation
  1077
- Usage Notes
  1078
36 Temperature Sensor (TSN)

1079
- Overview
  1079
- Register Descriptions
  1079
  - Temperature Sensor Calibration Data Register H (TSCDRH)
    1079
  - Temperature Sensor Calibration Data Register L (TSCDRL)
    1080
- Using the Temperature Sensor
  1080
  - Preparation for Using Temperature Sensor
    1080
  - Procedure for Using the Temperature Sensor
    1081
37 Operational Amplifier (OPAMP)

1082
- Overview
  1082
- Register Descriptions
  1083
- Operation
  1086
  - State Transitions
    1086
  - Operational Amplifier Control Operation
    1088
- Software Trigger Mode
  1092
- Activation Trigger Mode
  1093
- Activation and A/D Trigger Mode
  1094
- Usage Notes
  1094
38 Low Power Analog Comparator (ACMPLP)

1095
- Overview
  1095
- Register Descriptions
  1098
- Operation
  1101
- Noise Filter
  1103
- ACMPLP Interrupts
  1104
- ELC Event Output
  1105
- Interrupt Handling and ELC Linking
  1105
- Comparator Pin Output
  1105
- Usage Notes
  1105
  - Settings for the Module-Stop State
    1105
  - Relationship with A/D Converter
    1105
39 Bit D/A Converter (DAC8)

1106
- Overview
  1106
- Register Descriptions
  1106
  - D/A Conversion Value Setting Register N (Dacsn) (N = 0, 1)
    1106
  - D/A Converter Mode Register (DAM)
    1107
- Operation
  1107
- Usage Notes
  1107
40 Capacitive Touch Sensing Unit (CTSU)

1109
41 Data Operation Circuit (DOC)

1143
- Overview
  1143
- Register Descriptions
  1144
  - DOC Control Register (DOCR)
    1144
  - DOC Data Input Register (DODIR)
    1145
  - DOC Data Setting Register (DODSR)
    1145
- Operation
  1145
  - Data Comparison Mode
    1145
  - Data Addition Mode
    1146
  - Data Subtraction Mode
    1146
- Interrupt Request and Output to the Event Link Controller (ELC)
  1147
- Usage Notes
  1147
  - Settings for the Module-Stop State
    1147
42 Sram

1148
- Overview
  1148
- Register Descriptions
  1148
- Operation
  1153
  - Low Power Consumption Function
    1153
  - ECC Function
    1153
  - ECC Error Generation
    1154
  - ECC Decoder Testing
    1154
  - Parity Calculation Function
    1155
  - SRAM Error Sources
    1157
  - Access Cycle
    1158
- Usage Notes
  1158
  - Instruction Fetch from SRAM Area
    1158
  - Store Buffer of SRAM
    1158
43 Flash Memory

1159
- Overview
  1159
- Memory Structure
  1160
- Flash Cache
  1161
  - Overview
    1161
  - Register Descriptions
    1162
    
    Flash Cache Enable Register (FCACHEE)
    1162
    
    Flash Cache Invalidate Register (FCACHEIV)
    1162
- Operation
  1163
  - Notice to Use Flash Cache
    1163
- Operating Modes Associated with the Flash Memory
  1163
  - ID Code Protection
    1164
- Overview of Functions
  1164
  - Configuration Area Bit Map
    1166
  - Startup Area Select
    1166
  - Protection by Access Window
    1167
- Programming Commands
  1168
- Suspend Operation
  1168
- Protection
  1168
- 43.10 Serial Programming Mode
  1168
  - SCI Boot Mode
    1169
  - USB Boot Mode
    1169
- 43.11 Using a Serial Programmer
  1170
  - Serial Programming
    1170
  - Programming Environment
    1170
- 43.12 Self-Programming
  1170
  - Overview
    1170
  - Background Operation
    1171
- 43.13 Reading the Flash Memory
  1171
  - Reading the Code Flash Memory
    1171
  - Reading the Data Flash Memory
    1171
- 43.14 Usage Notes
  1171
44 Segment LCD Controller (SLCDC)

1173
- Overview
  1173
- Register Descriptions
  1174
  - LCD Mode Register 0 (LCDM0)
    1174
  - LCD Mode Register 1 (LCDM1)
    1175
  - LCD Clock Control Register 0 (LCDC0)
    1176
- LCD Display Data Registers
  1176
- Selection of LCD Display Data Register
  1177
  - A-Pattern Area and B-Pattern Area Data Display
    1177
  - Blinking Display (Alternately Displaying A-Pattern and B-Pattern Area Data)
    1177
- Setting LCD Controller/Driver
  1178
- Operation Stop Procedure
  1179
- Supplying LCD Drive Voltages VL1, VL2, and VL4
  1180
  - External Resistance Division Method
    1180
- Common and Segment Signals
  1181
- Display Modes
  1186
  - Four-Time-Slice Display Example
    1186
45 Secure Cryptographic Engine (SCE5)

1191
- Overview
  1191
- Operation
  1192
  - Encryption Engine
    1192
  - Encryption and Decryption
    1193
- Usage Notes
  1194
  - Software Standby Mode
    1194
  - Settings for the Module-Stop Function
    1194
46 Bluetooth Low Energy (BLE)

1195
- Overview
  1195
- Operation
  1197
  - State Transitions
    1197
- Interrupts
  1198
- Usage Notes
  1198
  - RF Transceiver Power-Supply
    1198
  - Wireless Standards
    1199
  - Notes on Board Design
    1200
47 Internal Voltage Regulator

1201
- Overview
  1201
- Operation
  1201
48 Electrical Characteristics

1202
- Absolute Maximum Ratings
  1203
- DC Characteristics
  1205
  - Tj/Ta Definition
    1205
  - I/O Vih, Vil
    1205
  - I/O Ioh , Iol
    1207
  - I/O VOH , VOL , and Other Characteristics
    1208
  - I/O Pin Output Characteristics of Low Drive Capacity
    1209
  - I/O Pin Output Characteristics of Middle Drive Capacity
    1211
  - P408, P409 I/O Pin Output Characteristics of Middle Drive Capacity
    1213
  - IIC I/O Pin Output Characteristics
    1215
  - Operating and Standby Current
    1216
  - VCC Rise and Fall Gradient and Ripple Frequency
    1224
- AC Characteristics
  1225
  - Frequency
    1225
  - Clock Timing
    1227
  - Reset Timing
    1230
  - Wakeup Time
    1231
  - NMI and IRQ Noise Filter
    1235
  - I/O Ports, POEG, GPT, AGT, KINT, and ADC14 Trigger Timing
    1236
  - CAC Timing
    1237
  - SCI Timing
    1238
  - SPI Timing
    1244
  - IIC Timing
    1249
  - CLKOUT Timing
    1250
- USB Characteristics
  1252
  - USBFS Timing
    1252
- ADC14 Characteristics
  1254
- DAC12 Characteristics
  1262
- TSN Characteristics
  1264
- OSC Stop Detect Characteristics
  1264
- POR and LVD Characteristics
  1265
- 48.10 VBATT Characteristics
  1269
- 48.11 CTSU Characteristics
  1271
- 48.12 Segment LCD Controller Characteristics
  1272
  - Resistance Division Method
    1272
- 48.13 Comparator Characteristics
  1272
- 48.14 OPAMP Characteristics
  1273
- 48.15 Flash Memory Characteristics
  1274
  - Code Flash Memory Characteristics
    1274
  - Data Flash Memory Characteristics
    1275
- Joint Test Action Group (JTAG)
  1276
  - Serial Wire Debug (SWD)
    1278
- 48.17 BLE Characteristics
  1279
  - Transmission Characteristics
    1279
  - Reception Characteristics (2 Mbps)
    1280
  - Reception Characteristics (1 Mbps)
    1280
  - Reception Characteristics (500 Kbps)
    1281
  - Reception Characteristics (125 Kbps)
    1281
Appendix 1. Port States in each Processing Mode

1282
Appendix 2. Package Dimensions

1284
Appendix 3. I/O Registers

1285
- Peripheral Base Addresses
  1285
- Access Cycles
  1286
- Register Descriptions
  1288
Revision History

1314

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Computer Hardware Motherboard Microcontrollers Adapter

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Renesas RTK7EKA4W1S00000BJ Manuals

Renesas RTK7EKA4W1S00000BJ User Manual (1317 pages)

Table of Contents

Features

1 Overview

2 Cpu

3 Operating Modes

4 Address Space

5 Memory Mirror Function (MMF)

6 Resets

7 Option-Setting Memory

8 Low Voltage Detection (LVD)

9 Clock Generation Circuit

10 Clock Frequency Accuracy Measurement Circuit (CAC)

11 Low Power Modes

12 Battery Backup Function

13 Register Write Protection

14 Interrupt Controller Unit (ICU)

15 Buses

16 Memory Protection Unit (MPU)

17 DMA Controller (DMAC)

18 Data Transfer Controller (DTC)

19 Event Link Controller (ELC)

20 I/O Ports

21 Key Interrupt Function (KINT)

22 Port Output Enable for GPT (POEG)

23 General PWM Timer (GPT)

24 Asynchronous General Purpose Timer (AGT)

25 Realtime Clock (RTC)

26 Watchdog Timer (WDT)

27 Independent Watchdog Timer (IWDT)

28 USB 2.0 Full-Speed Module (USBFS)

29 Serial Communications Interface (SCI)

1 I 2 C Bus Interface (IIC)

31 Controller Area Network (CAN) Module

32 Serial Peripheral Interface (SPI)

33 Cyclic Redundancy Check (CRC) Calculator

34 14-Bit A/D Converter (ADC14)

35 12-Bit D/A Converter (DAC12)

36 Temperature Sensor (TSN)

37 Operational Amplifier (OPAMP)

38 Low Power Analog Comparator (ACMPLP)

39 Bit D/A Converter (DAC8)

40 Capacitive Touch Sensing Unit (CTSU)

41 Data Operation Circuit (DOC)

42 Sram

43 Flash Memory

44 Segment LCD Controller (SLCDC)

45 Secure Cryptographic Engine (SCE5)

46 Bluetooth Low Energy (BLE)

47 Internal Voltage Regulator

48 Electrical Characteristics

Appendix 1. Port States in each Processing Mode

Appendix 2. Package Dimensions

Appendix 3. I/O Registers

Revision History

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