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Acromag XMC-ZU Series User Manual

Xilinx zynq ultrascale+ fpga based xmc modules
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XMC-ZU Series
Xilinx Zynq UltraScale+ FPGA Based XMC Modules
USER'S MANUAL
ACROMAG INCORPORATED
30765 South Wixom Road
Wixom, MI 48393-2417 U.S.A.
Tel: (248) 295-0310
Email: solutions@acromag.com
Copyright 2024, Acromag, Inc., Printed in the USA.
Data and specifications are subject to change without notice.
8501167A

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  • Page 1 Xilinx Zynq UltraScale+ FPGA Based XMC Modules USER’S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road Wixom, MI 48393-2417 U.S.A. Tel: (248) 295-0310 Email: solutions@acromag.com Copyright 2024, Acromag, Inc., Printed in the USA. Data and specifications are subject to change without notice. 8501167A...

  • Page 2: Table Of Contents

    I2C Ports ........................... 19 3.11 DisplayPort ..........................19 3.12 Clocks ............................19 3.13 P1 150 pin AXM Connector ...................... 20 Table 8 AXM Models Supported ......................20 3.14 P2 50 pin AXM Connector ......................20 Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 3 6.0.2 System Monitor Example Bare Metal Demo ................ 61 6.0.3 IO Examples Bare Metal Demo.................... 62 6.0.4 Ethernet Test Bare Metal Demo ..................65 6.0.5 USB Mass Storage Bare Metal Demo ................... 67 6.0.6 DisplayPort Example......................70 6.0.7 eMMC Read/Write Test ....................... 72 Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 4 8.3.3 Isolation ..........................79 8.3.4 Vibration and Shock Standards .................... 79 8.3.5 EMC Directives ........................79 Reliability Prediction ..........................80 Table MTBF of XMC-ZU ......................... 80 Certificate of Volatility ........................... 81 Revision History ............................. 82 Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 5: General Information

    1.3 Product Summary The XMC-ZU series modules are XMC modules designed around Xilinx Zynq UltraScale+ series MPSoCs which feature an APU, RPU, VCU and GPU with reconfigurable FPGA fabric available for parallel computing applications, all in one chip.

  • Page 6: Software Support

    Acromag provides a software product consisting of Linux software. This software (Model PMCSW-API-LNX) is composed of Linux libraries for all Acromag PMC, XMC, and VPX I/O board products, PCI and PCIe I/O cards, and CompactPCI I/O cards. The software supports X86 PCI bus only and is implemented as library of “C”...

  • Page 7: Vxworks

    VPX I/O board products, PCI and PCIe I/O Cards, and CompactPCI I/O Cards. The software is implemented as a library of “C” functions which link with existing user code to make possible simple control of all Acromag PCI and PCIe boards.

  • Page 8: Key Features And Benefits

    Vita 61 Connectors -40 to +85, conduction-cooled 1.6 Key Features and Benefits The XMC-ZU series block diagrams shown in Figure 1 and Figure 2 illustrate the key components and features that are summarized on the following pages. Acromag, Inc. Tel: 248-295-0310...
  • Page 9 Zynq PL are allocated to the XMC P15 connector. These lanes can be used for a 4 lane PCIe (PCI Express) implementation, Serial RapidIO, or 10 Gigabit Ethernet. The example design includes a 4 lane Gen 3 PCIe implementation. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 10: Preparation For Use

    It is important that the user employ satisfactory overall system design. It is understood and agreed by the Buyer and Acromag that this is the Buyer's responsibility. WARNING: This board utilizes static sensitive components and should only be handled at a static-safe workstation.

  • Page 11: Installation Considerations

    If the installation is in an industrial environment and the board is exposed to environmental air, careful consideration should be given to air- filtering. 3. HARDWARE INFORMATION AND CONFIGURATION Figure 3 XMC-ZU5EV Air-Cooled Module Top Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 12: Module Hardware Switch Configuration

    SW1-1 thru SW1-4 selects the boot mode for the Zynq UltraScale+. The default switch setting is set to boot from the MicroSD card. This switch must be set accordingly to boot from JTAG, QSPI or eMMC memory. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 13: Jtag Programming Voltage And Fru Voltage Select Sw2

    P15 connector provides the 4 lane PCI Express interface to the host processor, a JTAG interface, and an I C interface to a serial memory device. XMC-ZU models require 12V and -12V power. All models Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 14: Rear P4 Field I/O Connector

    As LVDS signal pairs, the signals can be grouped as 32 LVDS I/O pairs. The LVDS pairs are arranged in the same row in Table 5. For example, RIO1_P and RIO1_N form a signal pair. The P identifies the Positive input while the N identifies the Negative input. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 15: P16 Secondary Xmc Connector

    The P16 secondary XMC connector connects directly to the user-programmable FPGA for standard I/O user signals from the PL. The user I/O pins are connected to FPGA banks with VCCO pins powered by 1.8 volts. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 16 4.3.2 P16 Input Data Register and 4.3.3 P16 Output Data Register sections can be used to map the LVCMOS signal to the signal names given in this table. The 1.8V I/O standards available are listed in the UltraScale Architecture SelectIO Resources User Guide available from Xilinx. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 17: Ddr4 Memory

    The connector complies with ANSI/VITA 42.3-2006. DDR4 Memory The XMC-ZU series module provides 4GB (512Mb x 64) of DDR4 memory. The memory interfaces to the Zynq UltraScale+ via a 64-bit wide data bus. In the example design, the DDR4 is mapped to AXI address space and accessible through the DMA engine only.

  • Page 18: Quad Spi Flash

    Quad-SPI can be selected as a boot source via SW1 by setting SW1[4:1] to ON-ON-OFF-ON. MicroSD Card Interface The XMC-ZU series modules provide a microSD card socket to interface with the PS MIO pins 46 thru 51. The XMC-ZU ships with a Delkin Devices 16GB industrial MLC microSD card.

  • Page 19: I2C Ports

    Two audio channel with up to 24-bit sampling size with a maximum sample rate of 48 KHz. Supports live 24-bit audio sampling from the PL. 3.12 Clocks The XMC-ZU provides the following system clocks to the Zynq chip. PS_CLK: PS reference clock 33.333MHz Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 20: P1 150 Pin Axm Connector

    Clock 3: 125 MHz available on bank 66 (pins D7 and D6) for user programable FPGA. 3.13 P1 150 pin AXM Connector The P1 AXM connector is used to interface to the Acromag AXM mezzanine modules. The Acromag AXM mezzanine modules supported by the XMC-ZU are listed in the following table.

  • Page 21: Power

    LTC2954, the part initializes and the board DC/DC converters controlled by the EN pin will be held off. To assert the enable output, the power push button must be held low for a minimum of 32ms. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 22: Leds

    PS_ERROR_STATUS DS3 LED when lite (Red) indicates a secure lockdown state. Alternatively, it can be used by the platform management unit firmware to indicate system status. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 23: Reset

    Data Ports. The most important Configuration Registers are the Base Address Registers and the Interrupt Register which must be read to determine the base address assigned to the board and the interrupt request that goes active on a board interrupt request. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 24: Bar0 Memory Map

    DMA/Bridge Subsystem to generate interrupts to the host. Interrupts can be controlled and monitored through the IRQ Block Registers. More information on the IRQ Block Registers is available in the DMA/Bridge Subsystem for PCI Express v4.1 Product Guide. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 25: Bar2 Memory Map

    0x0002_0000→0x0002_FFFF P16 I/O AXI_GPIO (see PG144) P4 Rear I/O AXI_GPIO 0x0003_0000→0x0003_FFFF (see PG144) System Management Wizard 0x0004_0000→0x0004_1FFF (System Monitor) (see PG185) 0x0004_2000→0x0004_FFFF Reserved 0x0005_0000→0x0005_7FFF Block RAM 0x0005_8000→0x0006_7FFF Reserved Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 26: Axm Module Register Space

    P16 output data register at base address plus 0x2_0008. This P16 input data register is a read only register. Channel read operations use 32-bit, 16-bit or 8-bit data transfers. All channels of this register are fixed as input channels. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 27: P16 Output Data Register (Write Only) - (Bar2 + 0X20008)

    P16 input data register at base address plus 0x2_0000. This P16 output data register is a write only register. Channel write operations use 32-bit, 16-bit or 8-bit data transfers. All channels of this register are fixed as output channels. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 28: P4 Rear Input Data Register (Read Only) - (Bar2 + 0X3_0000)

    The rear I/O can also be configured as differential channels with 2 global clock signal pairs. Table 13 Rear Input Data Register (Read Only) - (BAR2 + 0x3_0000) Register Bit Channel VHDL Name Schematic Name RI(0) RIO0_GCLK_P RI(1) RIO1_P RI(2) RIO2_P RI(3) RIO3_P Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 29: P4 Rear Output Data Register (Write Only) - (Bar2 + 0X3_0008)

    Table 14 Rear Output Data Register (Write Only) - (BAR2 + 0x3_0008) Register Bit Channel VHDL Name Schematic Name RO(0) RIO0_GCLK_N RO(1) RIO1_N RO(2) RIO2_N RO(3) RIO3_N RO(4) RIO4_N RO(5) RIO5_N RO(6) RIO6_N Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 30: System Management Wizard (System Monitor)

    ADC can be converted to temperature using the following equation. The 10-bits digitized and output from the ADC can be converted to temperature by using the following equation. �������������� × 509.3140064 ����������������������(°��) = − 280.2308787 1024 Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 31: Block Ram

    Logic (PL) section, all on a single System on Chip (SoC). The Zynq UltraScale+ MPSoC PS block includes engines such as the following: • Quad-core Arm Cortex-A53 based Application Processing Unit (APU) • Dual-core Arm Cortex-R5 based Real Time Processing Unit (RPU) Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 32: Xmc-Zu Testing Hardware Requirements

    The installation and selection window is shown below for the Windows Self Extracting Web Installer. The XMC-ZU module is supported by Vitis WebPack which is free from Xilinx. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 33: Vivado And The Programmable Logic

    DMA/Bridge Subsystem for PCIe, System Monitor, BRAM and GPIO. 5.1.1 XMC-ZU Board Definition Files The Xilinx Vivado tools will need to point the Acromag Board Definition Files. These files are provided in the engineering design kit (EDK) for the XMC-ZU board.

  • Page 34: Xmc-Zu Programmable Logic Block Diagram Overview

    IP Integrator block diagram design. The design_top.vhd file was created by Acromag and can be used to tie in custom design files to the block design. An example of this being done can be seen in the Dxx_A75 AXM project files.
  • Page 35 The block diagram of the example design is shown in the following figure. This shows how the AXI interface is used to link together the Zynq UltraScale MPSoC, DMA/Bridge Subsystem for PCI Express, System Management Wizard, Block RAM and GPIO. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 36 XMC-ZU Series USER’S MANUAL Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 37 Notice that the MIO voltages listed correspond to the voltages supplied to the MIO banks in the design schematics. These values should not be changed. The I/O Configuration tab is where all PS peripherals, besides DDR, are configured and linked to their corresponding MIO pins. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 38 XMC and also facilitates DMA transfers from card-to-host (C2H) and host- to-card (H2C). Double-click the DMA/Bridge Subsystem for PCI Express Block to review its configuration. You can also refer to PG195 for more information on configuration and register mapping. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 39 Interrupts and other miscellaneous configurations are set in the PCIe : MISC tab. The number of DMA channels for the DMA engine is configured in the PCIe : DMA tab. The example design has 4 H2C and 4 C2H channels enabled. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 40 Looking at the address editor, you can see the devices that are accessible by the DMA controller (/xdma_0/M_AXI) interface are the Block RAM, OCM, QSPI and DDR4 memory devices. Similarly, the devices that can be accessed directly by the host PC through PCIe (/xdma_0/M_AXI_BYPASS) are Block Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 41 Translation entered in the DMA_Bridge Subsystem for PCI Express. Block Design Changes If changes are made to the block design, save and then validate the design as follows. File → Save Block Design Select Validate Design Click the Sources tab as see below. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 42 However, to be safe, you can explicitly reset and regenerate the output products manually. Right select the design_1.bd, then select Reset Output Products… Select Reset to confirm resetting the output products. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 43: Xmc-Zu Programmable Logic Design Constraints

    SLEW FAST [get_ports CTRL01_P] # set_property Output Drive Strength in # set_property DRIVE 4|8|12|16 [get_ports CTRL01_P] set_property DRIVE 12 [get_ports CTRL01_P] # set_property Pull-up, Pull-down, and Keeper # set_property PULLTYPE PULLUP|PULLDOWN|KEEPER [get_ports CTRL01_P] set_property PULLTYPE PULLUP [get_ports CTRL01_P] Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 44: Compile And Export Bit Files

    In Vivado, select File → Export → Export Hardware Platform. Be sure to check Include Bitstream in your export. Set the export path to your desired working directory. In this case it is set to MyVitis. Select Finish. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 45: Vitis Integrated Design Environment (Ide)

    When booting the ARM, the psu_init.tcl script is run to initialize the ARM processor registers. Note that by default, the psu_init.tcl will be sourced prior to running your application. That is how the ARM gets initialized for proper operation. The First Stage Boot Loader (FSBL) handles this. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 46: Creating A Hardware Platform Using Vitis

    File → Switch Workspace and then selecting the workspace. Create the platform project by selecting File → New → Platform Project. Enter the Hardware Platform name XMCZU_plat as the Platform Project name as seen below. Select Next Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 47 XMC-ZU Series USER’S MANUAL Select Browse and browse to the design_top.xsa file in the MyVitis folder. Select Open and Finish. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 48 XMC-ZU Series USER’S MANUAL Vitis generates the platform. The files that are generated are displayed in the explorer window as shown in the following figure. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 49 We can add multiple domains to the platform. Add the following libraries by modifying the standalone on psu_cortexa53_0 domain: a) Select Board Support Package under the standalone on psu_cortexa53_0 Board Support Package. b) Click Modify BSP Settings. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 50 On the Overview page, select the xilffs, xilpm, xilsecure and lwip213 (TCP/IP stack configuration) libraries. Only select the lwip213 when using the XMCZU with the Z01 mezzanine. Ethernet is not available with the AXM D01, DXX, A75 mezzanine modules, or XMC-ZU5EV1-xx-50 models. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 51 XMC board while uart 0 connects to the port that is present on the Z01 mezzanine board. d) Select OK. Now build the hardware by right-clicking on XMCZU_plat → Build Project. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 52: Creating A New Application

    The hardware platform is ready. You can write applications using this platform and test on the XMC-ZU hardware. 5.2.2 Creating a New Application Select psu_cortexa53_0 as seen below. Select File → New → Application Project. Select Next Select XMCZU_plat [custom] as a Platform. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 53 XMC-ZU Series USER’S MANUAL Select Next. Enter the Application project name of XMCZU_app and select Next. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 54 The following file will need to be moved to the myVitis/XMCZU_app/src folder if USB application is required. USB will only be available on the Z01 mezzanine. If running a Hello World application the helloworld.c program found at /XMCZU_app/src can be modified as needed. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 55 XMC-ZU Series USER’S MANUAL Now build the hardware by right mouse selecting the XMCZU_app project (in the Explorer section) and select Build project. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 56: Preparing The Boot Image

    XMCZU_app.elf file is generated in the XMCZU_app/Debug folder. 5.2.3 Preparing the Boot Image The next step is to create a nonvolatile boot image. The microSD, for example, is a non-volatile primary bootable source. Right mouse click XMCZU_app_system and select Create Boot Image. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 57 Vivado Block Design. One function of the FSBL is to program the PL. After the PL is configured, the application is loaded. Notice that by default, the output path points to BOOT.bin, which is the bootimage required for SD boot. Select Create Image. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 58 TeraTerm). The COM port device driver must be installed on the host PC prior to establishing communications with the XMC-ZU. Boot up the XMC-ZU. Use Device Manager to determine the COM port for the USB Serial Port under Ports (COM and LPT). Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 59: Steps To Program The Flash

    In addition, add the location for the FSBL file fsbl.elf (it should be located inside the folder .XMCZU_plat/export/XMCZU_plat/sw/XMCZU_plat/boot/fsbl.elf). Finally, make sure to select the correct Flash Type. For the XMC-ZU, it is qspi- x8-dual_parallel. Select the Program button to program. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 60: Xmc-Zu Processing System Bare Metal Software

    The menu shown below is a Putty com port that is linked to the XMCZU via the USB-UART interface. The AXM-Z01 has a Silicon Labs CP2103GM USB-to UART bridge device. This device allows connection of the XMC-ZU module to a host computer with a USB cable. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 61: System Monitor Example Bare Metal Demo

    6.0.2 System Monitor Example Bare Metal Demo To run the System Monitor example, select option 2. The current, maximum, and minimum temperatures will be displayed. This is followed by the reading and display of the current, maximum, and minimum VCCINT Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 62: Io Examples Bare Metal Demo

    P4 connector. Select option 4 by enter of value of 4 followed by selecting return key. Next write 0x33abce77 and select return key. The P4 output register will be written with the value entered. To verify enter value of 5 and select return key. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 63 XMC-ZU Series USER’S MANUAL Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 64 Selecting option 6 by entering a 6 followed by the return key will display the value 0xA000 which is the ID of the AXM-Z01. Also selecting option 7 will display the current AXM-Z01 FPGA firmware revision as seen below. The 41 shown corresponds to an ASCII A. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 65: Ethernet Test Bare Metal Demo

    XMC-ZU Series USER’S MANUAL 6.0.4 Ethernet Test Bare Metal Demo To run the Ethernet example, select option 4. The TCP echo server will be run. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 66 On the external system to which an ethernet cable is connected, using a command prompt (as seen below) enter ping 192.168.1.10. Breakout of the Ethernet test is accomplished by writing 0x567 to BRAM at address BAR2 + 0x5_0000 using PCIe bus example design application. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 67: Usb Mass Storage Bare Metal Demo

    PC the XMC-ZU USB port will be identified as a USB Mass Storage interfere with power up Device under the Universal Serial Bus Controllers (as seen below). sequence requirements of the XMCZU. Disconnect USB port when not in use. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 68 The host PC will ask to format the drive. Enter a Volume label and start the format operation. As a test a text file can be moved to the newly formatted drive. Select Format disk and enter Volume label name. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 69 Test by moving a file like the Document.rtf file shown below to the drive. Breakout of the USB test is accomplished by writing 0x123 to BRAM at address BAR2 + 0x5_0000 using PCIe bus example design application (as seen below). Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 70: Displayport Example

    USER’S MANUAL 6.0.6 DisplayPort Example The Display Port example is a Xilinx provided video example. The software in available in the Xilinx embedded category. This software can be found in the following installation path: C:\Xilinx\Vitis\2022.1\data\embeddedsw\XilinxProcessorIPLib\drivers\dpdma_v1_4\examples xdpdma_video_example.c Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 71 XMC-ZU Series USER’S MANUAL The example displays blue on the bottom half of the image and red on the top half. To run the DisplayPort example, select option 6. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 72: Emmc Read/Write Test

    XMC-ZU Series USER’S MANUAL 6.0.7 eMMC Read/Write Test To run the eMMC Read/Write Test, select option 7. Press ‘c’ key and select return key. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 73: Iic Bare Metal Software

    The bare metal application software illustrates IIC writes, reads to the IIC MAC EEPROM. The default device address is 0x50. This example allows read and write of the MAC EEPROM. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 74 The bare metal application software also illustrates IIC reads to the IIC clock generator device. The default device address is 0x70. The function name is provided in the bare metal application is Si5338ReadExample(). The function Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...
  • Page 75 The default device address is 0x5E. The function name is provided in the bare metal application is PMICReadExample(). The function then reads a page size of five. It performs read of first four byte and checks to verify values read as expected. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 76: Uart1 Test

    Then UART1 can be connected to a separate COM port. The following characters will be displayed. Enter the same 16 characters in the same order show. 0123456789:;<=>? After successfully run the following will be seen. Successfully run Uartps1 low echo example. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 77: Service And Repair

    CAUTION: POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS WHERE TO GET HELP If the problem persists, the next step should be to visit the Acromag website at https://www.acromag.com. Our web site contains the most up-to-date product and software information.

  • Page 78: Specifications

    Note 1: Recommended maximum cold plate temperature is 85 C. The XMC-ZU heatsink also must be held at 85 C. The recommended operating temperature for the Xilinx Zync chip is 100 C. The absolute maximum junction temperature is 125 Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 79: Relative Humidity

    Emissions per EN 61000-6-4: Enclosure Port, per CISPR 16. Low Voltage AC Mains Port, per CISPR 16. Note: This is a Class A product FCC Conformity: This device complies with Part 15, Class A of the FCC rules. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 80: Reliability Prediction

    MTBF (Mean Time Between Failure): MTBF in hours using MIL-HDBK-217F, FN2. Per MIL-HDBK-217, Ground Benign, Controlled, G Table MTBF of XMC-ZU Temperature MTBF (Hours) MTBF (Years) Failure Rate (FIT 25°C 396631 45.2775 2521.23 40°C 263901 30.1257 3789.3 FIT is Failures in 10 hours. Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 81: Certificate Of Volatility

    Storage of MAC ID Clear EEPROM using I2C bus. ■ Yes Storage of Code for □ No IPMI Interface Acromag Representative Name: Title: Email: Office Phone: Office Fax: Russ Nieves Sales and solutions@acromag.com 248-295-0310 248-624-9234 Marketing Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

  • Page 82: Revision History

    XMC-ZU Series USER’S MANUAL 10. Revision History Release Date Version EGR/DOC Description of Revision 09 FEB 2024 LMP/AMM Initial Document Publication Acromag, Inc. Tel: 248-295-0310 https://www.acromag.com...

This manual is also suitable for:

Xmc-zu5ev1-42-30Xmc-zu5ev1-61-30Xmc-zu5ev1-42-50Xmc-zu5ev1-61-50

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