Skanti E5002 Instruction Manual page 41

Ssb exciter
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The only types of PROMs which can be prograrmed by means of the
prograrming unit are the TI-types shorn in table 3al.1¢
Three PROMs Eogecher can contain the information of 32 different
frequency No§.
The three PROMs are placed in SKI,
SK2 and SK3.
Their input word address i§ chosen by nears of the keytoard on
the front panel, thus Selecting cine of the 32 possit)le words in
each of the three PROMs.
A prograrmed output will be greater than 2V (HIGH), and an unpro-
gramed output will be less than 0.8V (LOW).
Half of IC4 is always sensing the voltage level on pin 9 clf SKI.
If this voltage level is HIGH, pin 5 of IC4 will also become HIGH
after the first positive tratisition of the clock pulse at pin 3,
thus disabling IC2 and thereby IC6 and IC8 f ron being activated
by the key S1. This i§ irrelevant in E 5002.
The oiitputs from the six monostable nultivibrators IC2, IC6 and IC8
are combined I)y means o£ 4/6 IC5, 2/4 IC7 and 1/4 IC3 into three
pulse-trains, one for the Vac-pins, one for the enable pins of
the three PROMs and lastly one for the transistor TR1. This tran§i§tor
sinks the programing current from the PROM-output to which the pro-
graming pin is connected.
The three pulse-trains are shoim on the next page.
The two voltage levels of the vac-pins of the PROMs are stabilized
by means of D3 and IC9.
In order to keep the PROMs as cool as possible which i§ very essen-
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tine where no progra"ing takes place. This pulsed operat:ion is cot`-
trolled by a clock-pulse getierated by Icl opening and closi.ng via
2/4 IC3 and 2/6 IC5, the transistor TR2. At the end of each 5 nsec
period the logic levels of pin 9 of SKI and the programing pin are
read into the two D-flip£1ops of IC4; a HIon level, corresponding
to a progratmed bit location uill mke the associated lamp light.
when the key SKI is activated and MONl of IC2 is Criggered, the clock
generator Icl is stopped. Once the prclgraming pulse-trains have
been accoxpli§hed the clock generator i§ allowed to Start again
after a delay of approximately 30 msec.
A delay circuit consisting of R7l, R72. C12 and I)4 prevents the
¥§c;I:::I:=::£e:u::: ±E:: :::::nE:n:::::€yw:::e:::ear::::=:nEoun Lc
IC2o This is acconpli§hed by tuning o££ TR2 via 1/4 IC3 and 2/6 IC5
until all the voltage levels have stabilized.
5-10

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