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The keying signal ac IC2, pin 8 controls, via an inverter, transi-
stor TR9, supplying +12V co the output anplif ier circuit of the
RF translator
302
and activating the keyline to the power pack.
In SIMPLEX it supplies base current to TR8 controlling the muting
of the receiver.
The two-tone alarm §ignaLl generator incorporates the 45 see. timer
the 2lk ascable multivibrator and the 2.2 kHz and 1.3 kHz o§cillacors.
The 45 see. timer is enabled i ron the mode selector in TEST AI.AEN
and TRANSMIT ALARM and can be started by pushing the ALARM START
push-button that applies +12V to teminal 2c. Via the voltage divider
R32 and R33 a keying signal is applied to the key selector. The 2Hz
a§table nultivibrator starts and supplies bage current to TR6 and
:::: ::;::?a:;;:i:i get::di?4S#:a:x::::rthdiBci:::t:I: ::: :i:e:::e
keyer, applied to the receiver audio amplifier.
In the Al mode the 1.5 kHz oscillator is started. The audio sigtlal
is keyed in the sidetone keyer and the tone keyer which are both
controlled from the norse key. Capacitor C8 and adjoining components
at the gain control input of IC7 serve to shape the tone pulses cor-
rectly.
In the A2H mode the 2.2 kHz oscillator as veil as the 1.5 kHz oscil-
lator are on. R54 is connected to ground in IC4 thereby reducing the
peak level of the audio sigaal ac the tone keyer input Co the Same
level as when only otie totie is present. The sidetone keyer is con-
nected to the I.5 kllz oscillator only aB TR12 is tuned off by means
of D24.
when the TUNE-button of the transmitter power anplifier is activated
terminal l8c i9 LOW. A2H is selected by means of Dl Sad I)3 the trans-
nitcer is keyed via IC2 pin 9, and the sidetone keyer i8 Cumed o££
by. tnean§ of IC3 pia I.
5.5.5.
bffi
Divider
There are three divider chaing, their asgociated buffer aplifier§
and tuo phase/freq. detectors located on this board.
The ref erence divider produces the 2 kHz ref erence I requetlcy I or the
phase/£req. detector 1
and the 10 kHz refereace signal for the phase/
freq. detector 2 from a 1.4 rmlz signal derived from the TCXO.
The variable divider chains are coaposed of prograrmable up-counters
and their associated external gating logic. The dividing action is
acconpli§hed by presetting (programing) these councer® rich the data
blocks corregponding to the contents in the displays at the ead of
each counting cycle. The data blocks contain the BCI} 9's complenenc
code of the corresponding digit.
In the loop 1 divider chain the WT nodes infomation (e.g. A1, A2H
and F1) is used to control the associated extemal Sating logic. Ia
the lrr orodes this chain counts 15 clockpulses less than in any other
rode before concluding a coimting cycle. Thus the contetlts of the
data blocks are independent of the mode.
S-6
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