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The loop 2 divider chain counts independent of the receiving node
and adds by means of the external gacing logic 370 extra clock
cycles [o what is determined by the three nose important digits
before concluding a counting cycle.
The outputs from the variable dividers are led to their respective
phase/freq. detectors and are here compared Co the fixed reference
frequency. In case of a frequency difference the detector will pro-
duce a DC error voltage which will adjust the agsociated VCO to
establish the wanted frequency equality.
5.5.6.
5.5.7.
Translator
This circuit board contains one half of loop 3, nanely the frequency
comparacor ~ 200 divider, the loop 3 mixer, with its associated 1.5
MHz lotrpass i ilter and phase/freq. detector 3.
The VC0i output i requency is divided by 200 and fed as a variable
reference frequency Co one of the two input ports of phase/freq.
:::;c:::e:.v:::eo::i:: i:::::::Z ::g:::3i:i:::::eEy£::mi;c::: =ethe
sun frequency from this mixing process i5 removed in a 13-order
1.5 mlz low-pass filter thus allowing otlly the difference frequency
to pass on via the following buffer amplif ier to the other port of
phase/freq. detector 3. This detector is almost identical to the
detect:ors mentioned in the description of board
207 .
::e:::n¥;°3i:::::tb;I:8u::C¥h:Sb:;!=:n:h:: gea:a:::::i::ro:u:::: 3
this loop will end in a stable, unlocked condition. To avoid this
;t:i:rt:: :::q:::C±i: :::a::¥t::ei;1:iv:::a€::q:%::y i:£ t¥::ge::dt:; the
latch following the tva divider chains and via the phase/£req. detect-
or 3 the frequency of VC03 is forced to rige thus pulling loop 3 out
of this unwanted condition.
The output pulse from the detector is §noothed by means of a sinple
RC-i ilcer before leaving this circuit board.
=`=`9`
VC0| and VC02
The loop f ilter and volt:age controlled oscillator of both loop 1 arid
loop 2 are located on this board.
Both of these i ilters are active 3rd order lotirpass types with atl
integrated function iticorporated. The purpose of the loop f ilters
i8 to remove the pulses from the output of tbe phage/freq. detector
and allow only the DC-infomation to pass on to the vari-cap diode9
of the voltage controlled oscillators. By use of the phase error adjust-
ment pocentioneter the phase error pulse width can be rininized. Once
adjusted this width will renaia unchanged throughout the whole fre-
quency range of the VCO, due to the use of an integrator in the loop
filter. Both of the VCO'8 are amplitude regulated.
£:I:::e:::o3yo:e::: :: :h:e:::::gb::::u{: ::±cEfic92 ±S operating £S
5-7
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