Output Stage - Avtech AV-1002-C-KMP2 Instructions Manual

the range switch. The output of the 10198 is an inverted ECL pulse, whose width is equal
to the delay between the SYNC OUT pulse and the main output (plus various other
propagation delays.) This output drives the next stage.
PULSE WIDTH CIRCUIT
The first part of the pulse width circuit is almost identical to the delay circuit. The rising
edge of the delay circuit output triggers the 10198 (IC8) to generate a non-inverted ECL
pulse of variable duration. The duration sets the instrument's output pulse width. The range
and vernier controls operate as in the delay section. The output of the 10198 is then
transmitted through an AND gate (IC9), and the output of this gate in ANDed with its input.
This serves to shave several nanoseconds off of the pulse, by taking advantage of the first
AND gate's propagation delay. The two outputs of the second AND gate (it has both
inverting and non- inverting outputs) drive the following sections.
LOGIC OUTPUTS
The two ECL outputs of the pulse width section are buffered by two CLC110 fast integrated
circuit buffers (IC11 and IC 13), so as to be able to drive 50Q loads. Also, the two PW
section outputs are translated to TTL levels, and these TTL pulses are buffered to drive
509 by two CLC404 op amps (IC 12 and IC 14). This gives four signal: a TTL pulse, and its
complement, and an ECL pulse and its complement. To feed the two LOGIC outputs on
the front panel, an MT-2-5V-C93401 double-pole double-throw relay (RLY1)is used to
select between these four outputs. One relay switch is used to selected between the
non-inverted TTL and ECL signals. When the TTL/ECL switch is in the TTL position, the
relay is activated, and selects the TTL signal as output for the LOGIC connector. When in
the ECL position, the relay disengages, and selects the ECL signal. The other relay switch
selects between the inverting outputs in a similar fashion, for transmission to the other
LOGIC output.
OUTPUT STAGE
The output stage takes advantages of several high speed buffers and op amps. The input
is buffered by aCLC110 buffer (IC16), to drive 50Q. The output of the buffer is fed into an
MT-2-5V-C94301 relay (RLY2), which either sends the signal through an inverting buffer
(the CLC404 op amp, IC17), or bypasses the buffer. If the POLARITY switch is set to "+",
the op amp is bypassed, giving an output which swings between 0 and -2V. If the
POLARITY switch is in the "-" position, the relay switches revert to the other condition,
sending the signal through the op amp to give an output that swings between OV and
+2V. This output is fed into a 50Q potentiometer (R65), which serves as the AMPLITUDE
vernier. A second relay then varies the gain-setting resistor of the SL50 output op amp
(IC18). In the 5V and 10V amplitude ranges, the relay is closed, giving a total resistance
of about 2702 (R66). In the 1V range, the relay is open, so there is a series resistance of
about 1.5kQ. (The second gain-setting resistor for the SL50 op amp, a 1.5kQ resistor, is
contained inside the op amp case.) The SL50 op amp is set up in an inverting op amp
configuration, with offset. The offset is determined by a front-panel potentiometer voltage,