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When the next clock pulse enters the controller and starts the timing chain, at
t3 the FF at TP
~
sets but cannot clear, since the Data FF cannot set.
The
cleared output of the t3 FF (logic gate
[!])
disables the Read Data Reply path
so that attempts to read throughout the remainder of this punched card will
result in Rejects to the computer.
After this card leaves the read station
and a new card enters, read operations may be resumed (the leading edge pulse
of the RSE signal clears the FF at 4l-B02-l9).
5-9
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