Control Data 1700 Maintenance Manual page 51

Assuming normal operations, the Reply to the computer drops the Write signal
which, in turn, sets the Data Write FF (page 17) and clears the Reply FF (page
13). With the Data Write FF set, a Data status bit (17-C14-B) is sent to the
Common Synchronizer, an interrupt on data is enabled (AND gate
~,
214 module,
page 17) and a Data Write signal is applied to 13-C16-22. At this point, Data
Write operations can commence whenever the computer performs an output data
transfer to the station 1 Holding Register.
WRITE DATA OPERATION
When the 1704 executes an Output instruction to the TTY, a Write signal appears
at 13-B19-24. This generates Write Enable signals from module 213 if the Write
Mode and Write Data FFs are set. The Write Enable signals cause:
(1) a Reply to the 1704 after a 1 usec delay_
(2) transfer of data bits from the 1704 A Register to the Holding Register
(page 21).
(3)
setting of the mech Busy FF and the Start Motor FF (page 23).
(4) setting of the Clock Control FF (page 19).
If the Write Enable signal cannot be generated (Write Mode FF or Data Write FF
clear), a Reject is sent to the 1704. Receipt of either a Reply or Reject by
the 1704 will cause the Write signal to drop while the computer continues at the
appropriate program step. When the Write signal drops, the Write Data FF
(page 17) clears.
Setting of the Clock Control FF (page 19) will cause the Clock FF to set. This
generates a 100 nsec Clock 1 pulse which advances the Timing Chain (page 21) to
time 1 (tl). The Clock FF also starts a 4.5 msec time delay. At time 1, a
Start Pulse (2l-COB-7) is generated which sends a Start signal
(110 11 )
to the Printer
2-24
4