Control Data 1700 Maintenance Manual page 19

Rev. A
The logical one from 5-B14-l3 goes to the 204 module, page 7, where it causes
logical zeros to leave the module at pins 22 and 27. The logical "0" from
7-B13-27 connects bits 00 through 03 of the P. T. Reader data lines to bits 00
through 03 of the data line inputs to the A Register. The logical "0" from
7-B13-22 connects bits 04 through 07 of the P. T. Reader data lines to bits 04
through 07 of the data line inputs to the A Register. An 8-bit data transfer
path from station 2 controller to the A Register fan-in gates has now been
established.
The logical "1" output of 7-B13-l2 goes to the 201 module, page 3, where it
enables the Reply and Reject logic. If station 2 responds to the Read Data
Command, it will place data on the lines and send a Reply signal to the Common
Synchronizer. The Reply signal enters ll-B06-7 where it passes on to 3-B16-l8.
This will satisfy an AND gate which generates a Reply signal to the computer.
Receipt of the Reply signal by the computer causes:
(1) the computer timing chain to start up (from time 200).
(2) the Input to A
FF
(page 31) to set, gating the character into AOO-A07.
(3)
the clearing of the Input
FF
(page 75) which drops the Read signal to
3-B17-2 in the Common Synchronizer.
When the Read signal drops, it causes the Read Data signal to drop. Loss of the
Read Data signal to the P. T. Reader controller will cause its Reply signal to
drop. The computer continues with its program at P
+
1.
If station 2 cannot respond to the Read Data request, it will not place data on
the lines and will send a Reject signal to the Cornmon Synchronizer. The Reject
signal enters ll-B06-l where it passes on to 3-B16-l5. This will satisfy an
AND gate which generates
a
Reject signal to the computer. Receipt of the Reject
signal by the computer causes:
1-8