Control Data 1700 Maintenance Manual page 45

Rev. A
After a 4.5 msec time delay, the set output of the Clock FF (page 19) causes the
Strobe FF to set. This has no effect upon the Data Holding Register at this
time since the Receive Enable Strobe circuit (page 19) is disabled by the logical
"0" (space) from the keyboard line (logic
0 '
219 module, page 23).
After a delay of 4.5 msec, the set output of the Strobe
FF
(page 19) clears the
Clock FF. This causes a 100 nsec Clock 2 pulse (19-C05-20) to be applied to the
Timing Chain (page 21). This sets the second
FF
in addition to the first, giving
time 2 (t2) of the Timing Chain. At t2, the Start Detector logic (page 23) is
disabled by the logical "0" from 2l-C08-15. Also at t2, transfer of bit 00 from
the keyboard line into the lowest bit of the Data Holding Register is enabled
(110
11
from 2l-C08-4) as soon as the next Receive Enable Strobe signal is generated.
The receive Enable Strobe signal will be produced when the Strobe
FF
clears
(page 19) if the next code bar monitored sends a "111 into the controller via the
keyboard line (23-Cll-4). If the code bar sends a "0" into the controller, no
transfer is needed since the
FF
is already cleared.
The clock control circuits (page 19) continue advanCing the Timing Chain and
generating transfer pulses into the Data Holding Register until the 7-bit
character code and the parity bit (even) have been transferred. The Timing
Chain advances by setting each FF left to right, then clearing each FF left to
right. Each time a
FF
changes state, a new time is generated. Considering the
first change to be tl, the second change t2, etc., the folloWing table summarizes
the events which occur with each time generated from tl until the timing chain
is returned to an all-cleared status (t12).
2-18