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(1)
the computer timing chain (page 7) to start up (from time 200).
(2)
the set input of the Input to A FF (page 31) to become disabled,
thereby preventing any transfer into the A Register.
(3)
the clearing of the Input FF (page 75), which drops the Read signal to
3-B17-2 in the Common Synchronizer.
(4)
the formation of P
+
A
with the result going to P.
When the Read signal drops, it
causes the Read Data signal to drop.
Loss of a
Read Data signal to station 2 controller will cause its Reject signal to drop.
The computer continues with its program at P
+
1 (which is, in reality, the
original contents of P
+ A +
1).
READ DATA, STATION 0
What would happen if a Read Data request was made from station O?
There would
be an automatic Reject directly from the Common Synchronizer.
Any attempt to
Read Data from station 0 would satisfy the AND gate off input pin 13 of the
ZOI module, page 3.
The B term on the AND gate translates as (Read
+
Write)
(Reply).
Any time low speed Read or a Write signal is generated by the computer
and a Reply is not generated, logic gate
0
outputs a logical "1".
If the
station code is 0, the AND gate becomes satisfied and generates a Reject signal
to the computer.
At first glance this may seem to contradict our capability of performing a status
from station 0, but this is not the case.
It should be recalled that any status
operation gives an immediate logical "0" out of logic gate
0
on the ZOI
module.
This wi 11 prevent logic gate
0
from outputting a "1".
It should be noted that there are only five ways of getting a Reject signal
to
the computer, the one just discussed or a reject signal from the four controllers.
1-9
Rev. A
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