Kenwood NXR-1800 Service Manual page 18

2.5.6.1 MPU/DSP
2.5.6.1.1 MPU
The MPU/DSP (IC33) consist of ARM Cortex-A15 RISC processor and floating-point VLIM DSP, and equipped with peripheral
function. This MPU operates at 1.4GHz clock and power supply voltage is controlled by the power management IC (PWR MNG: IC1).
The MPU/DSP controls the flash memory, DDR3, eMMC, FPGA, and various control circuits.
2.5.6.1.2 DSP
The DSP circuit consists of the MPU/DSP (IC33) and processes the baseband signal. The DSP operates at 750MHz clock, the I/O
section operates at 3.3V and power supply voltage is controlled by the power management IC (PWR MNG: IC1).
The DSP performs the following processes:
 Digital processing
· 4-Level FSK and Baseband filter processing
· Vocoder processing between audio codecs, USB audio, audio over IP and modulation/demodulation
· CAI processing, such as error correction encoding/decoding and interleaving
· AFC loop control
· Frame synchronization and Time tracking
 Analog FM processing
· Pre-emphasis/De-emphasis
· QT/DQT encoding/decoding
 Audio or Modulation function
· Audio AGC processing for USB microphone
· Audio soft mute processing
· Modulation level processing
· Squelch filtering
 Other function
· Courtesy tone
· Repeater operating
· Analog/Digital mixed mode
· Voting pilot tone
· CWID
2.5.6.2 RTC (Real-time clock) circuit
The clock function is based on a real-time clock IC (RTC: IC4) and 32.768kHz crystal resonator (X4).
When the power supply is off, it is backed up by an internal secondary lithium battery.
2.5.6.3 FPGA circuit
The FPGA circuit consists of a FPGA (IC60). The FPGA operates on an external clock of 20MHz, and the I/O section and the core
section operates at 3.3V.
The FPGA performs the following processes:
(1) Interface between MPU/DSP and various devices
(IF_IC, PLL_IC, LED, CODEC_IC, OLED, ADC/DAC, D-SUB 25-pin, KNOB, and FAN)
(2) Control of various power enable
(3) Power sequence control
2.5.6.4 Memory circuit
This repeater consist of three types of memory IC.
The MPU/DSP (IC33) control DDR3 memories (Lower DDR3: IC47, Upper DDR3: IC48), Serial NOR Flash memory (NOR FLASH:
IC52) and eMMC (IC520).
2.5.6.4.1 DDR3 memory
IC47 and IC48 are 4G-bits DDR3 SDRAM, organized as 32M x 16bits x 8banks. DDR3 memory is used for work memory for program
execution of the MPU/DSP. The DDR3 memory operates at 666MHz.
2.5.6.4.2 Serial NOR Flash memory
Serial NOR Flash memory has SPI interface controlled by the MPU/DSP.
IC52 is 128M bits Serial NOR Flash memory that used for boot program memory of the MPU/DSP.
2.5.6.4.3 eMMC
IC520 is 8G byte eMMC.
The eMMC (IC520) has High Speed JC64 DDR interface controlled by the MPU/DSP.
The eMMC (IC520) contains all the programs and data (including tuning data) for the MPU/DSP.
1-18 (No.RA094<Rev.002>)