Kenwood NXR-1800 Service Manual page 15

2.5.4.4 CM Coupler circuit
CM coupler circuit is a line for detecting forward wave and reflected wave. Forward wave is detected by IC3027 and is converted into
DC voltage. If an abnormal antenna load is connected, reflected wave is detected by D3081 and converted into DC voltage.
2.5.4.5 Filter circuit
This circuit is removes harmonics from the transmitter output and sends filtered signal to the antenna.
2.5.4.6 APC circuit
The automatic transmission power control (APC) circuit stabilizes the transmitter output power at a pre-determined level. The forward
RF signal from CM coupler circuit is detected to FWD DC voltage by PA control (PA CTL: IC3027) and fed to DC amplifier (DC AMP:
IC3026 (2/2)). DC amplifier (DC AMP: IC3026 (2/2)) compares the APC control voltage generated by D/A converter (DAC: IC78) and
FWD DC voltage from PA control (PA CTL: IC3027) to control the gate bias voltage for the pre-drive amplifier 2 (PRE DRV AMP2:
Q3067), drive amplifier (DRV AMP: Q3065) and final amplifier (FINAL AMP: Q3069).
2.5.4.7 High temperature detector circuit
To prevent thermal destruction of the final amplifier (FINAL AMP: Q3069) or the components on the low-pass filter (LPF), this circuit
reduces the APC control voltage when temperature rises. The MPU/DSP (IC33) detects the temperature with the thermistor (TH3001)
for final amplifier (Q3069) and the thermistor (TH3000) for low-pass filter and controls the APC voltage.
PRE DRV
TX VCO
AMP
2.5.5 PLL Frequency Synthesizer System
This model has independent two PLL systems, RX VCO/ RX PLL and TX VCO/ TX PLL.
2.5.5.1 TCXO (X900)
TCXO (X900) generates a common reference frequency of 20.0MHz for the two PLL frequency synthesizers. The reference signal is
buffered by IC900 and IC901, and distributed to RX PLL (IC1001), TX PLL (IC2000), IF IC (IC700), MPU/DSP (IC33) and FPGA (IC60).
The frequency adjustment is achieved by adjusting a D/A converter (DAC: IC78) output in the voltage of the control terminal of TCXO.
2.5.5.2 RX VCO/ RX PLL
2.5.5.2.1 VCO circuit
RX VCO consists of two VCOs, RX_L VCO and RX_H VCO.
RX_L VCO and RX_H VCO are switched by DC switches (DC SW: Q1002 and Q1003), according to the operating frequency.
RX VCO generates the 1st local signal for the receiver and the frequency range is 355 to 425MHz (E2 type), or 405 to 475MHz (E type).
RX_L VCO (Q1004) oscillation frequency range is 355 to 390MHz (E2 type), or 405 to 440MHz (E type), and RX_H VCO (Q1005)
oscillation frequency range is 390 to 425MHz (E2 type), or 440 to 475MHz (E type).
The voltage control terminal "CV" is controlled by RX PLL (IC1001), and the voltage control terminal "ASSIST" is controlled by D/A
converter (DAC: IC78).
2.5.5.2.2 PLL circuit
RX PLL (IC1001) compares the difference in phases of the VCO oscillation signal and the TCXO reference frequency. And it returns
the difference voltage to the VCO CV terminal and realizes the "Phase Locked Loop". This allows the VCO oscillation frequency to
accurately match (lock) the desired frequency.
When the frequency is controlled by the PLL, the frequency convergence time increases as the frequency difference increases when
the set frequency is changed. To supplement this, the MPU/DSP (IC33) is used before control by the PLL to bring the VCO oscillation
frequency close to the desired frequency. As a result, the VCO CV voltage does not change and is always stable at approximate 2.5V.
The desired frequency is set for the PLL by the FPGA (IC60) through the 3-line "DT", "CLK ", "/CS" serial bus for PLL. MPU/DSP
monitors through the "RX_LO1_LOCK", whether the PLL is locked or not. If the VCO does not lock to desired frequency (unlock), the
"RX_LO1_LOCK" logic is low.
IC3023 Q3067 Q3065
PRE DRV
DRV AMP
AMP2
APC
Fig.3 Transmitter system
Q3069
FINAL
COUPLER
AMP
FWD
PA
IC3027
Gate Bias CTL
DC
IC3026 (2/2)
AMP
DC
LPF
AMP
IC3025 IC3024
TX ANT
LPF
REV
REV
PWR D3081
DET
DC
IC3026 (1/2)
AMP
(No.RA094<Rev.002>)1-15