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Schematic Diagrams
Processor 4/7
D
Sheet 5 of 74
Processor 4/7
C
B
11,38,39,59
39
A
B - 6 Processor 4/7
5
4
NEAR CPU
1.0V_VCCST
R285
100_04
59
H_CPU_SVIDDAT
59
H_CPU_SVIDALRT#
59
H_CPU_SVIDCLK
H_PROCHOT#
59
H_PROCHOT#
57
DDR_VTT_PG_CTRL
VCCST_PW RGD
R297
20_1%_04
32
H_PM_DOW N
32
PCH_PECI
TO EC
39
H_PECI
32
PCH_THERMTRIP#
34
H_SKTOCC_N
R620
FLOAT FOR SKL
GND FOR CNL
1.0V_VCCST
VDD3
R258
1K_04
VCCST_PWRGD
VCCST_PW RGD
R267
100K_04
D
5
G
C444
S
Q24B
*0.01u_16V_X7R_04
MTDK3S6R
D
R268
*0402_short
2
G
ALL_SYS_PW RGD
S
Q24A
MTDK3S6R
C462
*0.1u_10V_X7R_04
1.0DX_VCCSTG
H_PROCHOT#
R242
1K_04
Q20
C416
G
47p_50V_NPO_04
H_PROCHOT_EC
2SK3018S3
R254
100K_04
CAD Note: Capacitor need to be placed
close to buffer output pin
5
4
3
U113E
KABYLAKE_HALO
BGA1440
B31
35
PCH_CPU_BCLK_R_DP
BCLKP
R286
A32
35
PCH_CPU_BCLK_R_DN
BCLKN
56.2_1%_04
D35
35
PCH_CPU_PCIBCLK_R_DP
PCI_BCLKP
C36
35
PCH_CPU_PCIBCLK_R_DN
PCI_BCLKN
E31
35
CPU_24MHZ_R_DP
CLK24P
D31
35
CPU_24MHZ_R_DN
CLK24N
R287
220_04
CPU_VIDALERT_N
BH31
VIDALERT#
BH32
VIDSCK
BH29
VIDSOUT
R249
499_1%_04
H_PROCHOT#_R
BR30
PROCHOT#
BT13
DDR_VTT_CNTL
R255
60.4_1%_04
VCCST_PW RGD_CPU
H13
VCCST_PWRGD
BT31
33
H_PW RGD
PROCPWRGD
BP35
32
PLTRST_CPU_N
RESET#
PROC_TDO
BM34
32
H_PM_SYNC
PM_SYNC
H_PM_DOW N_R
BP31
PM_DOWN
PROC_TMS
H_PECI_R
R291
*12.1_1%_04
BT34
PECI
PROC_TCK
J31
R292
*0402_short
THERMTRIP#
PROC_TRST#
H_SKTOCC_N
BR33
SKTOCC#
PROC_PREQ#
*0_04
BN1
PROC_SELECT#
PROC_PRDY#
BM30
CATERR#
CFG_RCOMP
5 OF 14
REV = 1
QLM5
PCIE PORT BIFURCATION STRAPS
CFG[6:5]
DEFENSIVE PULL DOWN SITE
CFG7
27,30,33,36,38,39,42,44,48,50,51,52,53,54,55,56,58,61,62,63,66
3
2
1
CFG[0]: Stall reset sequence after PCU
PLL lock until de-asserted:
— 1 = (Default) Normal Operation;
No stall.
— 0 = Stall.
CFG[1]: Reserved configuration lane.
?
CFG[2]: PCI Express* Static x16 Lane
Numbering Reversal.
BN25
CFG0
R296
*1K_04
CFG[0]
— 1 = Normal operation
BN27
CFG1
R289
*1K_04
CFG[1]
— 0 = Lane numbers reversed.
BN26
CFG2
R293
*1K_04
CFG[2]
BN28
CFG[3]: Reserved configuration lane.
CFG3
R288
*1K_04
CFG[3]
BR20
CFG4
R625
1K_04
CFG[4]: eDP enable:
CFG[4]
BM20
CFG5
R295
*1K_04
— 1 = Disabled.
CFG[5]
BT20
CFG6
R621
*1K_04
— 0 = Enabled.
CFG[6]
BP20
CFG7
R624
*1K_04
CFG[6:5]: PCI Express* Bifurcation
CFG[7]
BR23
— 00 = 1 x8, 2 x4 PCI Express*
CFG[8]
BR22
— 01 = reserved
CFG[9]
BT23
CFG[10]
— 10 = 2 x8 PCI Express*
BT22
CFG[11]
— 11 = 1 x16 PCI Express*
BM19
CFG[12]
BR19
CFG[7]: PEG Training:
CFG[13]
BP19
— 1 = (default) PEG Train
CFG[14]
BT19
immediately following RESET# de
CFG[15]
assertion.
BN23
— 0 = PEG Wait for BIOS for
CFG[17]
BP23
training.
CFG[16]
BP22
CFG[19]
CFG[19:8]: Reserved configuration
BN22
CFG[18]
lanes.
SKL_XDP_MBP_0
BR27
BPM#[0]
BT27
SKL_XDP_MBP_1
BPM#[1]
BM31
SKL_MBP_2
BPM#[2]
BT30
SKL_MBP_3
BPM#[3]
BT28
H_TDO
BL32
PROC_TDI
BP28
H_TCK
BR28
H_TDO
R622
51_04
BP30
H_TRST#
BL30
H_PREQ#
H_TCK
R623
51_04
BP27
H_PRDY#
BT25
CFG_RCOMP
H_SKTOCC_N
R619
R290
100K_04
?
49.9_1%_04
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
1: (DEFAULT)NORMAL OPERATION;
LANE# DEFINITION MATCHES
CFG2
SOCKET PIN MAP DEFINITION
0: LANE REVERSAL
DISPLAY PORT PRESENCE STRAP
1: DISABLED;
NO PHYSICAL DISPLAY PORT ATTACHED
TO EMBEDDED DISPLAY PORT
0: ENABLED;
AN EXTERNAL DISPLAY PORT DEVICE
CFG4
IS CONNECTED TO THE EMBEDDED
DISPLAY PORT
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
Title
Title
Title
[05]Processor 4/7-CLK/JTAG/MISC
[05]Processor 4/7-CLK/JTAG/MISC
[05]Processor 4/7-CLK/JTAG/MISC
7,53
1.0DX_VCCSTG
7,32,33,58,59
1.0V_VCCST
Size
Size
Size
Document Number
Document Number
Document Number
6-71-P9500-D03
6-71-P9500-D03
6-71-P9500-D03
30,31,32,33,34,36,38,52
3.3VA
A3
A3
A3
P955HQx
P955HQx
P955HQx
VDD3
Date:
Date:
Date:
Friday, June 23, 2017
Friday, June 23, 2017
Friday, June 23, 2017
Sheet
Sheet
Sheet
2
1
D
1.0V_VCCST
C
3.3VA
B
A
Rev
Rev
Rev
D03
D03
D03
5
5
5
of
of
of
74
74
74
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