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The board support package (BSP) is provided with the system and includes support for U-Boot and the Linux operating system. The figure below shows the LS1088A processor block diagram. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
Most Significant Bit Phased Lock Loop Parts per Million Reset Configuration Word RGMII Reduced General Media Independent Interface Read Only Memory Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
One DDR4 uDIMM/RDIMM connector featuring: • 72-bit (8-bit ECC) • four chip-selects • speeds up to 2133 MT/s The supplied DDR4 memory module is: Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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Runs from hot power rails, allowing operation while system is off Clocks SYSCLK Fixed at 100 MHz. DIFF_SYSCLK Fixed at 100 MHz DDRCLK Fixed at 100 MHz Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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Note that several power supplies have on-board low-pass filters, to prevent board switching noise from coupling into sensitive analog supplies. The following figure shows the filters used. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
Vendor Description 0.90/1.00/1.025 V LTC3882 (controller Linear Tech Supplies power to the LS1088A cores. DC- DC converter that produces: 25 A Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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NOTE: Jumper-enabled OVDD also powers: PROG_MTR TA_PROG_SFP These fuse-programming jumpers are normally removed. EVDD 1.80 V or 3.3 V FPF1320 SDHC IO Power. Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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(controller #2) controller CPLD IO 5.0 A 1V0_SB 0.9 / 1.0 V MAX8902B Power supply for TA_BB_VDD (tamper detection block) NOTE: Must follow SVDD 150 mA setting. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
Drive “Power Enable” to: t + 330 ms Tier #3 Stable All tier 3 supplies report “Power Good”. If not, stall. Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
2.2 Clocks The LS1088ARDB-PB provides all the required clocks for the processor as well as other devices. The following figure shows the overall clock architecture. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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All the clocks are fixed frequency, and most are produced by the SiliconLabs Si5341B (or a buffered copy of its outputs) or the IDT IDT9FGV0641. The following table summarizes the specifications of each clock and the component that provides it. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
• One 288-pin JEDEC DDR4 DIMM connector supporting single and dual rank industry-standard, uDIMM or RDIMM modules • 64-bit data • 8-bit ECC QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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NXP cannot validate all combinations available in the market; therefore, the system is shipped with a representative uDIMM. The following figure shows the DDR memory architecture QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
One exception is the retimer on SerDes 1 lane “C”; these retimers default to CPRI rates and need to be programmed before use. To automate this, the self- QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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Program I2C mux to connect to I2C_CH5 (where the Retimer is located). 0x18 0xFF 0x0C Send writes to Channel A (TX) and B (RX). 0x60 0x00 0x61 0xB0 0x62 0x90 0x63 0xB3 0x64 0xCD QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
The LS1088ARDB-PB supports the use of external QSPI NOR programmers or emulators using a 20-pin 0.05” pitch header, SamTec TFM-110-02-L-D-DS-K or equivalent. The pinout is shown in the figure below. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
NAND is always on IFC_CS0_B, and its RB# signal is always on IFC_RB0_B. Programming details include: • MSEL = NAND machine • Speed: 90 ns Programmed timing values vary depending on the SYSCLK and RCW values chosen. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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MMC HS200 DDR Bootable eMMC interface. 8-bit interface. The following figure shows the SDHC interface (as well as the SPI block, which is partially usable by SDHC). QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
• SDHC CD_B and WP signals are managed by the CPLD for cases where eMMC is used, which do not provide those signals. NOTE The eMMC devices are 8 bits; when using eMMC, the SPI bus is not available. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
The LS1088ARDB-PB supports two USB 3.0 controllers, with each port connected to a different type of USB connector for maximum flexibility. The table below describes the USB ports. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
The following figure shows the LS1088ARDB-PB USB interface. Figure 2-13. USB architecture Each USB connector has an LED nearby (“USB1” and “USB2”) which are active when USB +5V power is enabled. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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I2C devices categorized by function (clock, SerDes, slots, etc.). The I2C devices indirectly available on I2C1 are shown in the following figure. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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PCA9547 I2C Bus Multiplexer First-level multiplexer. 0x50 RCW + PBL Atmel AT24C512 4KiB EEPROM: Stores RCW and PBLOADER data. Write protectable. Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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“7b” addresses do not include the R/W bit as an address member, though some datasheets might do so. For consistency, all I2C addresses are 7 bits of address only. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
• System alert monitoring and status display • Remapping of system boot devices • Control and status registers The following figures show the system controller architectural details. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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The system controller is powered continuously by 3.3 V and 1.8 V regulators, powered from the +5V standby power (from an LT8612). This allows it to control all aspects of board bring-up, including initial power sequencing. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
Apply power to group 1. Enable group 1 power supplies, wait for all members to report “power good” (if supported): DVDD Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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Registers which default to switch values are set now. Drive configuration values. Reset-sampled configurations signals are driven: CFG_RCW_SRC[8:0] CFG_RSP_DIS CFG_SVR[0:1] CFG_ENG_USE[0:2] CFG_SOC_USE Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
LEDs. The CPLD uses the THERM signals to power down the system, to protect the LS1088A from over-temperature damage. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
JTAG, so this allows systems to update the CPLD (if necessary) without requiring purchase of a third-party programmer. The resulting JTAG architecture is shown in the following figure. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
The board has a stacked conventional DB9M connector, so that two serial ports are simultaneously available. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
TXD3/TXD4, while CTS1_B/CTS2_B becomes RXD3/RXD4. To evaluate UART3 and/or UART4, a custom DB9 interface cable must be created, as shown in the figure below. Figure 2-22. 4-Wire to 2-Wire UART adapter QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
(PTP) which works in tandem with the ETH controller to time-stamp the incoming packets. A 12-pin header is provided on the RDB to allow support of 1588 protocol. The following figure shows the organization of the IEEE 1588 system. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
The LS1088A has no dedicated GPIO pins. For the LS1088ARDB-PB, GPIO access is provided via IRQ pins IRQ[3:10], but only when those pin are not used for IRQ purposes. The following figure shows the GPIO access header. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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GPIO_4[6] IRQ[9] Reserved GPIO_4[7] IRQ[10] Reserved GPIO_4[8] Note that all IRQ signals have a weak pull-up, so GPIO pins programmed to input mode will default to “1”. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
Power Event Trace (PWR_EVENT) 00000000b 024h Power Status 0 (PWR_MSTAT) 110010xxb 025h Power Status 1 (PWR_STAT1) xx111111b 026h Power Status 2 (PWR_STAT2) xx111111b Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
An undefined register address does not have any defined register value. Reads and writes to such addresses should be avoided. If you attempt to read such addresses, undefined data is returned. Undefined register addresses may be defined in the future. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
3.3 Identification Registers The ID block of registers contain values which identify the board, including major revisions to the board and/or system controller FPGA or CPLD. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
The ID number remains same for all board revisions. 3.4.3 Diagram Bits NONE 3.4.4 Fields Field Function The board-specific identifier for the system. 39h= LS1088ARDB 4Ah= LS1088ARDB 3.5 Board Version (VER) QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
The BRD field lets end users determine the version of the board. Software can use this field to print board version identification. For example: printf("Board Version: %c", (get_pixis( VER ) & 0Fh) + 'A' - 1 ); QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
3.6.3 Diagram Bits QVER NONE 00000001 3.6.4 Fields Field Function Qixis version as a decimal value: QVER 1= Version 1 2= Version 2 3.7 Programming Model (MODEL) QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
Programming Model Type: 0= Normal Qixis register set. 1= Minimal Qixis register set (QixMin). Reserved. Reserved. Programming model version: MODEL 1= Version 1 2= Version 2 etc. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
Other information can be obtained by writing the corresponding address and reading the register. Reserved fields are found only in QDS QTAG but are present for compatibility. Contents are as follows: QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
This block of registers control the operation of Qixis itself (or other operations which do not constitute controlling the board or the DUT, which are managed with BRDCFG/ DUTCFG registers) or monitor the status of various things. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
0= FAIL LED is not asserted due to software (it might still be on due to hardware failures). 1= FAIL LED is forced on. Generally, this indicates a software-diagnosed error. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
1= The system has been reconfigured by software. ASLEEP Reporting: ASLEEP 0= At least one core is actively operating. 1= All cores are in sleep mode. Reserved. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
VCC/Core Power Supply Temperature Warning: 0= The VCC power supply temperature is within normal limits. 1= The VCC power supply temperature has exceeded warning limits. Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
The STAT_PRES1 detects the installation of various devices/cards. 3.14.3 Diagram Bits CPU_ID NONE 3.14.4 Fields Field Function Processor Present: 0= A processor is detected (soldered-in or socketed). Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
Direct control of the LEDs is possible only when CTL[LED] is set to 1; otherwise Qixis uses them to display general system activity. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
1= LED M[bitno] is on. 3.17 Reconfiguration Registers --------------------------------------------------------------------------- 3.18 Reconfiguration Control (RCFG) 3.18.1 Address Register Offset RCFG 010h 3.18.2 Function The RCFG_CTL register is used to control the reconfiguration sequencer. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
Reconfiguration Start: 0= Reconfiguration sequencer is idle. 1= On the 0-to-1 transition, the reconfiguration process begins. 3.19 Loss Of Signal (LOS_STAT) 3.19.1 Address Register Offset LOS_STAT 01Dh QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
The PWR_CTL2 register is used to control system power-on/power-off events. 3.22.3 Diagram Bits CRST 0000000 3.22.4 Fields Field Function Toggle System Power 0= No action. Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
This field contains the previous value stored in the PEVENT field. Power Event: PEVENT The field will contain one of the following codes, indicating the event which caused the power change: QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
The PWR_MSTAT register monitors the overall power status of the board, including that of the main (ATX or other) power supply used to power all other rails. 3.24.3 Diagram Bits ATXON ATXGD FAULT PWROK SSTATE NONE QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
The PWR_STATn registers are used to monitor the status of individual power supplies. If a bit is set to '1', the respective power supply is operating correctly. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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Values in the CLK_SPD1 register are used by boot software accurately initialize timing- dependent parameters, such as for UART baud rates, I2C clock rates, and DDR memory timing. 3.28.3 Diagram Bits DDRCLK SYSCLK NONE 0000 0000 QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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The CLK_ID register is used to identify the arrangement of the clock control registers. Software should check CLK_ID register before attempting to interpret/control the clock control registers. 3.29.3 Diagram Bits NONE 0000 0100 QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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3.31 Reset Control (RST_CTL) 3.31.1 Address Register Offset RST_CTL 040h 3.31.2 Function The RST_CTL register is used configure or trigger reset actions. 3.31.3 Diagram Bits REQMD DDRLK ARST CRST SW_RSTMD QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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1= Upon transition from 0 to 1, restart the reset sequence. 3.32 Reset Status (RST_STAT) 3.32.1 Address Register Offset RST_STAT 041h 3.32.2 Function The RST_STAT register reports the current status of various reset-related signals. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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0100= Reset switch (chassis or on-board) was pushed. 0101= RCFG_CTL[GO] (that is, reconfiguration reset) was asserted. 0110= RESET_REQ_B assertion (from processor) was asserted. 1111= No event recorded yet. 3.34 Reset Force 1 (RST_FORCE1) QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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EPHY1 GRST 3.34.4 Fields Field Function Reserved. 1= Assert RST_QSPI_B. QSPI 1= Assert RST_I2C_B. 1= Assert RST_EPHY3_B EPHY3 1= Assert RST_EPHY2_B Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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HRST PORST GRST 3.35.4 Fields Field Function 1= Assert RST_IEEE_B / RST_1588_B for IEEE-1588 test cards. IEEE 1= Assert RST_RETIMER_B RTIME Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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NOTE: This bit only asserts the signal to the DUT; it is not intended to be used as a general system reset. 3.36 Reset Force 3 (RST_FORCE3) 3.36.1 Address Register Offset RST_FORCE3 045h 3.36.2 Function Assert selected reset sources. See RST_FORCE1 for details. 3.36.3 Diagram Bits GRST 00000 QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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Note that RST_MASK bits are cleared on AUX reset, and so are usually only cleared by software. This is very different from the RST_FORCE registers. 3.37.3 Diagram Bits QSPI EPHY3 EPHY2 EPHY1 ARST QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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Valid for Rev B boards or later only. SVDD Voltage Selection: SVDDVSEL 0= 1.0V 1= 0.9V PCI Express Spread-Spectrum Enable: PEXSS Controls the net labelled CFG_PEXSS or CFG_SPREAD_EN. Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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0= I2C2 connect to CPLD for SDHC_CD_B/SDHC_WP signals. 1= reserved. Controls I2C3 routing: I2C3 0= I2C3 connect to USB2 for USB2_DRVBUS/USB2_PWRFAULT signals. Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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1= EVDD is forced to 1.8V always. 3.46 Board Configuration 6 (BRDCFG6) 3.46.1 Address Register Offset BRDCFG6 056h 3.46.2 Function BRDCFG6 controls PCIe M.2 resources for the LS1088ARDB-PB. It is QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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Enables transmit of an SFP module by controlling the TX_DISABLE pin (net nSFP_TX_EN). SFP_TX 0= SFP transmit enabled. 1= SFP transmit disabled. The default value is based on the serdes protocol selected. Reserved. 3.48 DUT Configuration Registers QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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RCW location setting (cfg_rcw_src). 3.49.3 Diagram Bits RCWSRC RRST SW_RCRSRC 3.49.4 Fields Field Function RCW Source Location: RCWSRC The 8 most-significant bits of the RCW location configuration (cfg_rcw_src[8:1]). QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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NOTE: Only DDR4 is supported, but the configuration value varies depending on the device. Reserved. IFC Transceiver Enable: Controls cfg_te. Reserved. RCW Source Location (additional): RSRC8 Controls cfg_rcw_src[0] (the LSB of the 9-bit value). QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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Controls cfg_svr[0:1] (note the bit order). SVR01 Controls processor pin 'TESTSEL_B'. TEST NOTE: Unlike all other DUTCFG bits, this one is static (always driven). 3.52 DUT Configuration 6 (DUTCFG6) QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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DUTCFG registers, unlike BRDCFG registers, are not always driven - they are driven only during the reset configuration sampling interval (PORESET_B assertion), and remain tri-stated thereafter. Refer to the device hardware specification for hardware pin- sampled timing parameters. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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: Image of SW1..SWn Ranges not listed are reserved. A standard use of the CMSA/CMSD port is to read the state of configuration switches, as follows: Qixis_Set_Reg( CMS_A, 00h ); QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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CMSD contains the value of a CMS register selected by CMSA. See CMSA for details. 3.57.3 Diagram Bits DATA ARST 00000000 3.57.4 Fields Field Function Read/write internal CMS registers selected with CMS_A. DATA QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
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How to Reach Us: Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or Home Page: fabricate any integrated circuits based on the information in this document. NXP reserves the right to nxp.com make changes without further notice to any products herein.
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