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NXP Semiconductors QorIQ LS1088A Reference Manual

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QorIQ LS1088A Reference Design
Board (LS1088ARDB-PB) Reference
Manual
Document Number: LS1088ARDB-PBRM
Rev. 0, 09/2018

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Summary of Contents for NXP Semiconductors QorIQ LS1088A

  • Page 1 QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual Document Number: LS1088ARDB-PBRM Rev. 0, 09/2018...
  • Page 2 QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 3: Table Of Contents

    2.4.3 SerDes Configuration............................39 EMI - Ethernet Management Interface........................... 41 Integrated Flash Controller (IFC)........................... 41 2.6.1 QSPI NOR Flash..............................43 2.6.2 QSPI NOR Emulator............................43 2.6.3 NAND Flash..............................44 QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 4 Resets....................................69 3.2.1 Reset Actions..............................69 Identification Registers..............................69 Identification (ID)................................70 3.4.1 Address................................70 3.4.2 Function................................70 3.4.3 Diagram................................70 3.4.4 Fields.................................. 70 Board Version (VER)..............................70 3.5.1 Address................................70 QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 5 3.10 General Control (CTL)..............................75 3.10.1 Address................................76 3.10.2 Function................................76 3.10.3 Diagram................................76 3.10.4 Fields.................................. 76 3.11 Auxiliary (AUX)................................77 3.11.1 Address................................77 3.11.2 Function................................77 3.11.3 Diagram................................77 3.11.4 Fields.................................. 77 QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 6 3.16 LED Control (LED)................................ 82 3.16.1 Address................................82 3.16.2 Function................................82 3.16.3 Diagram................................82 3.16.4 Fields.................................. 83 3.17 Reconfiguration Registers...............................83 3.18 Reconfiguration Control (RCFG)........................... 83 3.18.1 Address................................83 3.18.2 Function................................83 QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 7 3.23.2 Function................................88 3.23.3 Diagram................................88 3.23.4 Fields.................................. 88 3.24 Power Status 0 (PWR_MSTAT).............................89 3.24.1 Address................................89 3.24.2 Function................................89 3.24.3 Diagram................................89 3.24.4 Fields.................................. 89 3.25 Power Status 1 (PWR_STAT1)............................90 QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 8 3.30 Reset Control Registers..............................95 3.31 Reset Control (RST_CTL)..............................95 3.31.1 Address................................95 3.31.2 Function................................95 3.31.3 Diagram................................95 3.31.4 Fields.................................. 96 3.32 Reset Status (RST_STAT)..............................96 3.32.1 Address................................96 3.32.2 Function................................96 QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 9 3.36.4 Fields.................................. 101 3.37 Reset Mask 1 (RST_MASK1)............................102 3.37.1 Address................................102 3.37.2 Function................................102 3.37.3 Diagram................................102 3.37.4 Fields.................................. 103 3.38 Reset Mask 2 (RST_MASK2)............................103 3.38.1 Address................................103 QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 10 3.43 Board Configuration 2 (BRDCFG2)..........................107 3.43.1 Address................................107 3.43.2 Function................................108 3.43.3 Diagram................................108 3.43.4 Fields.................................. 108 3.44 Board Configuration 4 (BRDCFG4)..........................108 3.44.1 Address................................109 3.44.2 Function................................109 3.44.3 Diagram................................109 3.44.4 Fields.................................. 109 QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 11 3.50 DUT Configuration 1 (DUTCFG1)..........................114 3.50.1 Address................................115 3.50.2 Function................................115 3.50.3 Diagram................................115 3.50.4 Fields.................................. 115 3.51 DUT Configuration 2 (DUTCFG2)..........................116 3.51.1 Address................................116 3.51.2 Function................................116 QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 12 3.56.2 Function................................120 3.56.3 Diagram................................120 3.56.4 Fields.................................. 120 3.57 Core Management Data (CMSD)........................... 121 3.57.1 Address................................121 3.57.2 Function................................121 3.57.3 Diagram................................121 3.57.4 Fields.................................. 121 3.58 Switch Manager Registers.............................. 121 QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 13 3.59 Switch Control (SWS_CTL)............................122 3.59.1 Address................................122 3.59.2 Function................................123 3.59.3 Diagram................................123 3.59.4 Fields.................................. 123 3.60 Switch Sample Status (SWS_STAT)..........................123 3.60.1 Address................................123 3.60.2 Function................................124 3.60.3 Diagram................................124 3.60.4 Fields.................................. 124 QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 14 QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 15 The board support package (BSP) is provided with the system and includes support for U-Boot and the Linux operating system. The figure below shows the LS1088A processor block diagram. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 16: Related Documents

    Contains LS1088A information on Pin assignments, Electrical characteristics, Hardware Advanced Multicore design, considerations, Package information, and Ordering information. Processor Data Sheet Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 17: Acronyms

    Most Significant Bit Phased Lock Loop Parts per Million Reset Configuration Word RGMII Reduced General Media Independent Interface Read Only Memory Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 18: Features

    One DDR4 uDIMM/RDIMM connector featuring: • 72-bit (8-bit ECC) • four chip-selects • speeds up to 2133 MT/s The supplied DDR4 memory module is: Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 19 Runs from hot power rails, allowing operation while system is off Clocks SYSCLK Fixed at 100 MHz. DIFF_SYSCLK Fixed at 100 MHz DDRCLK Fixed at 100 MHz Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 20: Ls1088Ardb-Pb Block Diagram

    • 1.8 for eSPI • 3.3 V eSDHC • 1.0 V for Secure monitor (TA_BB) 1.4 LS1088ARDB-PB Block Diagram The figure below shows the LS1088ARDB-PB block diagram QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 21 QSPI 2 x 64MB Emulator RF Antenna(x8) S25FS512SDSMF USB 3.0 PWR supply POWER SUPPLIES type A (VDD, GVDD, etc.) USB 3.0 micro AB FANS Figure 1-2. LS1088ARDB-PB block diagram QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 22 LS1088ARDB-PB Block Diagram QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 23: Functional Description

    Thermal Management Thermal Management JTAG Port JTAG Port Serial Ports Serial Ports (DUART) Ethernet Controllers Ethernet (ETH) Controller Interface IEEE-1588 PTP IEEE 1588™ PTP Support GPIO GPIO Access QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 24 5.0V @ 10A PS_5V0_PG to CPLD 5V0_SB LT8612 5.0V @ 5A 12V0 LT8612 PS_3V3_EN 3.3V @ 5A PS_3V3_PG 12V0 PS_3V3_M2 3V3_M2PCIE LT8612 PCIE_EN 3.3V @ 5A PS_3V3_M2PCIE_PG to CPLD QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 25 Chapter 2 Functional Description Figure 2-1. LS1088ARDB-PB power supplies QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 26 Note that several power supplies have on-board low-pass filters, to prevent board switching noise from coupling into sensitive analog supplies. The following figure shows the filters used. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 27: Primary Power Supply

    Vendor Description 0.90/1.00/1.025 V LTC3882 (controller Linear Tech Supplies power to the LS1088A cores. DC- DC converter that produces: 25 A Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 28 NOTE: Jumper-enabled OVDD also powers: PROG_MTR TA_PROG_SFP These fuse-programming jumpers are normally removed. EVDD 1.80 V or 3.3 V FPF1320 SDHC IO Power. Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 29 (controller #2) controller CPLD IO 5.0 A 1V0_SB 0.9 / 1.0 V MAX8902B Power supply for TA_BB_VDD (tamper detection block) NOTE: Must follow SVDD 150 mA setting. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 30: Power Sequencing

    Drive “Power Enable” to: t + 330 ms Tier #3 Stable All tier 3 supplies report “Power Good”. If not, stall. Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 31: Auxiliary Power Supplies

    2.2 Clocks The LS1088ARDB-PB provides all the required clocks for the processor as well as other devices. The following figure shows the overall clock architecture. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 32 All the clocks are fixed frequency, and most are produced by the SiliconLabs Si5341B (or a buffered copy of its outputs) or the IDT IDT9FGV0641. The following table summarizes the specifications of each clock and the component that provides it. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 33: Ddr Memory

    • One 288-pin JEDEC DDR4 DIMM connector supporting single and dual rank industry-standard, uDIMM or RDIMM modules • 64-bit data • 8-bit ECC QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 34 NXP cannot validate all combinations available in the market; therefore, the system is shipped with a representative uDIMM. The following figure shows the DDR memory architecture QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 35 Chapter 2 Functional Description Figure 2-5. LS1088ARDB-PB DDR interface QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 36: Ddr Power

    SerDes Lane Connectivity Ports Block 3 / “A” NXP F104 Quad PHY #2 100M / 1G 4x 100M/1G RJ45 MagJacks ETH4..ETH7 Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 37 2 / “C” PCIe (Gen3) x2 M.2 Slot 2 (Key E, 2230 card) 3 / “D” The following figure shows the SerDes 1 and 2 connectivity for the LS1088ARDB-PB. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 38: Mac Assignment

    RF Antenna(x8) CFG_MUX _SLOT 2 from CPLD Figure 2-6. SerDes connectivity 2.4.1 MAC Assignment The LS1088A associates MACs with Ethernet ports as shown in the table below. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 39: Connectors

    One exception is the retimer on SerDes 1 lane “C”; these retimers default to CPRI rates and need to be programmed before use. To automate this, the self- QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 40 Program I2C mux to connect to I2C_CH5 (where the Retimer is located). 0x18 0xFF 0x0C Send writes to Channel A (TX) and B (RX). 0x60 0x00 0x61 0xB0 0x62 0x90 0x63 0xB3 0x64 0xCD QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 41: Emi - Ethernet Management Interface

    IFC interface, with the following features: • Primary QSPI boot image • Secondary (recovery) QSPI boot image • ONFI 2.2-compatible NAND flash • Off-board SPI/QSPI emulation support QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 42 The table below summarizes the devices and chip-select connections. Table 2-11. IFC Device Table Device Details Size Memory Addressing: SW_QMAP[2:0] Controller Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 43: Qspi Nor Flash

    The LS1088ARDB-PB supports the use of external QSPI NOR programmers or emulators using a 20-pin 0.05” pitch header, SamTec TFM-110-02-L-D-DS-K or equivalent. The pinout is shown in the figure below. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 44: Nand Flash

    NAND is always on IFC_CS0_B, and its RB# signal is always on IFC_RB0_B. Programming details include: • MSEL = NAND machine • Speed: 90 ns Programmed timing values vary depending on the SYSCLK and RCW values chosen. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 45 MMC HS200 DDR Bootable eMMC interface. 8-bit interface. The following figure shows the SDHC interface (as well as the SPI block, which is partially usable by SDHC). QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 46: Serial Peripheral Interface (Spi)

    • SDHC CD_B and WP signals are managed by the CPLD for cases where eMMC is used, which do not provide those signals. NOTE The eMMC devices are 8 bits; when using eMMC, the SPI bus is not available. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 47: Usb Interfaces

    The LS1088ARDB-PB supports two USB 3.0 controllers, with each port connected to a different type of USB connector for maximum flexibility. The table below describes the USB ports. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 48: I2C Ports

    The following figure shows the LS1088ARDB-PB USB interface. Figure 2-13. USB architecture Each USB connector has an LED nearby (“USB1” and “USB2”) which are active when USB +5V power is enabled. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 49 I2C devices categorized by function (clock, SerDes, slots, etc.). The I2C devices indirectly available on I2C1 are shown in the following figure. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 50 PCA9547 I2C Bus Multiplexer First-level multiplexer. 0x50 RCW + PBL Atmel AT24C512 4KiB EEPROM: Stores RCW and PBLOADER data. Write protectable. Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 51 “7b” addresses do not include the R/W bit as an address member, though some datasheets might do so. For consistency, all I2C addresses are 7 bits of address only. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 52: Interrupts

    AQR105 PHY Interrupt: IRQ_AQR105_B -- AQR105 #1 IRQ3_B Reserved for GPIO use Attached to 1x8 GPIO header (J68). IRQ4_B IRQ5_B IRQ6_B IRQ7_B IRQ8_B IRQ9_B IRQ10_B IRQ11_B Unused Reserved QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 53: System Controller

    • System alert monitoring and status display • Remapping of system boot devices • Control and status registers The following figures show the system controller architectural details. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 54 25 MHz ALT_HOT_CLK 25 MHz PCB_REV[2:0] 000 = “Rev A” 3.3V LVCMOS 001 = “Rev B” Selectively DNP resistors to encode PCB rev Figure 2-17. System controller architecture QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 55 The system controller is powered continuously by 3.3 V and 1.8 V regulators, powered from the +5V standby power (from an LT8612). This allows it to control all aspects of board bring-up, including initial power sequencing. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 56: System Configuration

    TEST_SEL_B TEST_SEL_B SW3[1] DUTCFG2[0] Silicon variations. CFG_ENG_USE0 IFC_WE_0_B SW5[1:3] DUTCFG11[7:5 Optional features. CFG_ENG_USE1 IFC_OE_B CFG_ENG_USE2 IFC_WP_B CFG_SOC_USE ASLEEP DUTCFG6[0] Undefined option. Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 57: System Startup

    Apply power to group 1. Enable group 1 power supplies, wait for all members to report “power good” (if supported): DVDD Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 58 Registers which default to switch values are set now. Drive configuration values. Reset-sampled configurations signals are driven: CFG_RCW_SRC[8:0] CFG_RSP_DIS CFG_SVR[0:1] CFG_ENG_USE[0:2] CFG_SOC_USE Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 59: Thermal Management

    LEDs. The CPLD uses the THERM signals to power down the system, to protect the LS1088A from over-temperature damage. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 60: Jtag Port

    JTAG, so this allows systems to update the CPLD (if necessary) without requiring purchase of a third-party programmer. The resulting JTAG architecture is shown in the following figure. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 61: Serial Ports (Duart)

    The board has a stacked conventional DB9M connector, so that two serial ports are simultaneously available. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 62: Quad Serial Port Support

    TXD3/TXD4, while CTS1_B/CTS2_B becomes RXD3/RXD4. To evaluate UART3 and/or UART4, a custom DB9 interface cable must be created, as shown in the figure below. Figure 2-22. 4-Wire to 2-Wire UART adapter QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 63: Ethernet (Eth) Controller Interface

    (PTP) which works in tandem with the ETH controller to time-stamp the incoming packets. A 12-pin header is provided on the RDB to allow support of 1588 protocol. The following figure shows the organization of the IEEE 1588 system. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 64: Gpio Access

    The LS1088A has no dedicated GPIO pins. For the LS1088ARDB-PB, GPIO access is provided via IRQ pins IRQ[3:10], but only when those pin are not used for IRQ purposes. The following figure shows the GPIO access header. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 65 GPIO_4[6] IRQ[9] Reserved GPIO_4[7] IRQ[10] Reserved GPIO_4[8] Note that all IRQ signals have a weak pull-up, so GPIO pins programmed to input mode will default to “1”. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 66 GPIO Access QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 67: Qixis Programming Model

    Power Event Trace (PWR_EVENT) 00000000b 024h Power Status 0 (PWR_MSTAT) 110010xxb 025h Power Status 1 (PWR_STAT1) xx111111b 026h Power Status 2 (PWR_STAT2) xx111111b Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 68: Register Conventions

    An undefined register address does not have any defined register value. Reads and writes to such addresses should be avoided. If you attempt to read such addresses, undefined data is returned. Undefined register addresses may be defined in the future. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 69: Reserved Bits

    3.3 Identification Registers The ID block of registers contain values which identify the board, including major revisions to the board and/or system controller FPGA or CPLD. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 70: Identification (Id)

    The ID number remains same for all board revisions. 3.4.3 Diagram Bits NONE 3.4.4 Fields Field Function The board-specific identifier for the system. 39h= LS1088ARDB 4Ah= LS1088ARDB 3.5 Board Version (VER) QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 71: Function

    The BRD field lets end users determine the version of the board. Software can use this field to print board version identification. For example: printf("Board Version: %c", (get_pixis( VER ) & 0Fh) + 'A' - 1 ); QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 72: Qixis Version (Qver)

    3.6.3 Diagram Bits QVER NONE 00000001 3.6.4 Fields Field Function Qixis version as a decimal value: QVER 1= Version 1 2= Version 2 3.7 Programming Model (MODEL) QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 73: Function

    Programming Model Type: 0= Normal Qixis register set. 1= Minimal Qixis register set (QixMin). Reserved. Reserved. Programming model version: MODEL 1= Version 1 2= Version 2 etc. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 74: Minor Revision (Minor)

    Other information can be obtained by writing the corresponding address and reading the register. Reserved fields are found only in QDS QTAG but are present for compatibility. Contents are as follows: QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 75: Diagram

    This block of registers control the operation of Qixis itself (or other operations which do not constitute controlling the board or the DUT, which are managed with BRDCFG/ DUTCFG registers) or monitor the status of various things. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 76: General Control (Ctl)

    0= FAIL LED is not asserted due to software (it might still be on due to hardware failures). 1= FAIL LED is forced on. Generally, this indicates a software-diagnosed error. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 77: Auxiliary (Aux)

    3.11.3 Diagram Bits ARST 00000000 3.11.4 Fields Field Function User-defined value. 3.12 System Status (STAT_SYS) QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 78: Function

    1= The system has been reconfigured by software. ASLEEP Reporting: ASLEEP 0= At least one core is actively operating. 1= All cores are in sleep mode. Reserved. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 79: Address

    VCC/Core Power Supply Temperature Warning: 0= The VCC power supply temperature is within normal limits. 1= The VCC power supply temperature has exceeded warning limits. Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 80: Presence Detect 1 (Stat_Pres1)

    The STAT_PRES1 detects the installation of various devices/cards. 3.14.3 Diagram Bits CPU_ID NONE 3.14.4 Fields Field Function Processor Present: 0= A processor is detected (soldered-in or socketed). Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 81: Presence Detect 2 (Stat_Pres2)

    3.15 Presence Detect 2 (STAT_PRES2) 3.15.1 Address Register Offset STAT_PRES2 00Ch 3.15.2 Function The STAT_PRES2 detects the installation of cards in various PCI Express or SGMII slots. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 82: Diagram

    Direct control of the LEDs is possible only when CTL[LED] is set to 1; otherwise Qixis uses them to display general system activity. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 83: Fields

    1= LED M[bitno] is on. 3.17 Reconfiguration Registers --------------------------------------------------------------------------- 3.18 Reconfiguration Control (RCFG) 3.18.1 Address Register Offset RCFG 010h 3.18.2 Function The RCFG_CTL register is used to control the reconfiguration sequencer. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 84: Fields

    Reconfiguration Start: 0= Reconfiguration sequencer is idle. 1= On the 0-to-1 transition, the reconfiguration process begins. 3.19 Loss Of Signal (LOS_STAT) 3.19.1 Address Register Offset LOS_STAT 01Dh QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 85: Function

    1= The SFP tranceiver is reporting a receive loss. SFP TX FAULT: TXFLT 0= The SFP tranceiver is transmitting normally. 1= The SFP tranceiver is reporting a transmit fault. Reserved. 3.20 Watchdog (WATCH) QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 86: Address

    Watchdog timer value, as determined by the formula: WATCH time-out = [ WATCH * (2.0sec) ] + 2.0sec Examples: 11111111= 8 min 00111111= 2 min 00001111= 32 sec 00000011= 8 sec 00000000= 2 sec QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 87: Power Control/Status Registers

    The PWR_CTL2 register is used to control system power-on/power-off events. 3.22.3 Diagram Bits CRST 0000000 3.22.4 Fields Field Function Toggle System Power 0= No action. Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 88: Power Event Trace (Pwr_Event)

    This field contains the previous value stored in the PEVENT field. Power Event: PEVENT The field will contain one of the following codes, indicating the event which caused the power change: QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 89: Power Status 0 (Pwr_Mstat)

    The PWR_MSTAT register monitors the overall power status of the board, including that of the main (ATX or other) power supply used to power all other rails. 3.24.3 Diagram Bits ATXON ATXGD FAULT PWROK SSTATE NONE QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 90: Fields

    The PWR_STATn registers are used to monitor the status of individual power supplies. If a bit is set to '1', the respective power supply is operating correctly. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 91 Function Reserved. XVDD (SerDes IO Voltage) Monitor. XVDD TA_BB Monitor TA_BB Reserved. VCC_0.85V Monitor. V0.85 DDR4 Interface VPP Monitor Core Power Monitor 3.26 Power Status 2 (PWR_STAT2) QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 92 VCC_2V5 VTT1 GVDD NONE 3.26.4 Fields Field Function Reserved. VCC_1.2V Monitor VCC1P2 OVDD Monitor OVDD Reserved. 2V5 Monitor VCC_2V5 DDR termination power #1 VTT1 DDR Power. GVDD QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 93 Values in the CLK_SPD1 register are used by boot software accurately initialize timing- dependent parameters, such as for UART baud rates, I2C clock rates, and DDR memory timing. 3.28.3 Diagram Bits DDRCLK SYSCLK NONE 0000 0000 QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 94 The CLK_ID register is used to identify the arrangement of the clock control registers. Software should check CLK_ID register before attempting to interpret/control the clock control registers. 3.29.3 Diagram Bits NONE 0000 0100 QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 95 3.31 Reset Control (RST_CTL) 3.31.1 Address Register Offset RST_CTL 040h 3.31.2 Function The RST_CTL register is used configure or trigger reset actions. 3.31.3 Diagram Bits REQMD DDRLK ARST CRST SW_RSTMD QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 96 1= Upon transition from 0 to 1, restart the reset sequence. 3.32 Reset Status (RST_STAT) 3.32.1 Address Register Offset RST_STAT 041h 3.32.2 Function The RST_STAT register reports the current status of various reset-related signals. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 97 1= PORESET_B is asserted. RESET_REQ_B status: RREQ 0= RESET_REQ_B is not asserted. 1= RESET_REQ_B is asserted. 3.33 Reset Event Trace (RST_REASON) 3.33.1 Address Register Offset RST_REASON 042h QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 98 0100= Reset switch (chassis or on-board) was pushed. 0101= RCFG_CTL[GO] (that is, reconfiguration reset) was asserted. 0110= RESET_REQ_B assertion (from processor) was asserted. 1111= No event recorded yet. 3.34 Reset Force 1 (RST_FORCE1) QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 99 EPHY1 GRST 3.34.4 Fields Field Function Reserved. 1= Assert RST_QSPI_B. QSPI 1= Assert RST_I2C_B. 1= Assert RST_EPHY3_B EPHY3 1= Assert RST_EPHY2_B Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 100 HRST PORST GRST 3.35.4 Fields Field Function 1= Assert RST_IEEE_B / RST_1588_B for IEEE-1588 test cards. IEEE 1= Assert RST_RETIMER_B RTIME Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 101 NOTE: This bit only asserts the signal to the DUT; it is not intended to be used as a general system reset. 3.36 Reset Force 3 (RST_FORCE3) 3.36.1 Address Register Offset RST_FORCE3 045h 3.36.2 Function Assert selected reset sources. See RST_FORCE1 for details. 3.36.3 Diagram Bits GRST 00000 QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 102 Note that RST_MASK bits are cleared on AUX reset, and so are usually only cleared by software. This is very different from the RST_FORCE registers. 3.37.3 Diagram Bits QSPI EPHY3 EPHY2 EPHY1 ARST QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 103 1= Mask RST_MEM_B (DDR slots, etc.) 3.38 Reset Mask 2 (RST_MASK2) 3.38.1 Address Register Offset RST_MASK2 04Ch 3.38.2 Function Mask selected reset sources. See RST_FORCE1 for details. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 104 1= Mask RST_CLK. Reserved. 1= Mask RST_EMMC_B. EMMC Reserved. 1= Mask DUT_HRESET_B. HRST 1= Mask DUT_PORESET_B. PORST 3.39 Reset Mask 2 (RST_MASK3) 3.39.1 Address Register Offset RST_MASK3 04Dh QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 105 3.40 Board Configuration Registers The reset control register group handles reset behavior configuration and general monitoring of resets. 3.41 Board Configuration 0 (BRDCFG0) 3.41.1 Address Register Offset BRDCFG0 050h QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 106 ========== ========== 000= DEV #0 DEV #1 001= DEV #1 DEV #0 010= DEV #0 011= DEV #1 100= DEV #0 Reserved. 3.42 Board Configuration 1 (BRDCFG1) QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 107 Function Reserved. DDRCLK Frequency Selection: DDRCLK 01= 100.00 MHz (fixed) Other values are reserved. SYSCLK Frequency Selection: SYSCLK 0010= 100.000000 MHz (fixed) 3.43 Board Configuration 2 (BRDCFG2) QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 108 00= 100.000 MHz (fixed, SW_SPREAD=0) 11= 100.000 MHz (spread-spectrum enabled, SW_SPREAD=1) SerDes2 Clock #2 Rate: SD2CK2 00= 100.000 MHz (fixed, SW_SPREAD=0) 11= 100.000 MHz (spread-spectrum enabled, SW_SPREAD=1) QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 109 Valid for Rev B boards or later only. SVDD Voltage Selection: SVDDVSEL 0= 1.0V 1= 0.9V PCI Express Spread-Spectrum Enable: PEXSS Controls the net labelled CFG_PEXSS or CFG_SPREAD_EN. Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 110 0= I2C2 connect to CPLD for SDHC_CD_B/SDHC_WP signals. 1= reserved. Controls I2C3 routing: I2C3 0= I2C3 connect to USB2 for USB2_DRVBUS/USB2_PWRFAULT signals. Table continues on the next page... QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 111 1= EVDD is forced to 1.8V always. 3.46 Board Configuration 6 (BRDCFG6) 3.46.1 Address Register Offset BRDCFG6 056h 3.46.2 Function BRDCFG6 controls PCIe M.2 resources for the LS1088ARDB-PB. It is QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 112 0= Gbit WIFI mode disabled. 1= Gbit WIFI mode enabled. M.2 #1 WIFI Enable (net PCIE1_WDISABLE_B): P2DIS 0= WIFI disabled. 1= WIFI enabled. 3.47 Board Configuration 9 (BRDCFG9) QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 113 Enables transmit of an SFP module by controlling the TX_DISABLE pin (net nSFP_TX_EN). SFP_TX 0= SFP transmit enabled. 1= SFP transmit disabled. The default value is based on the serdes protocol selected. Reserved. 3.48 DUT Configuration Registers QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 114 RCW location setting (cfg_rcw_src). 3.49.3 Diagram Bits RCWSRC RRST SW_RCRSRC 3.49.4 Fields Field Function RCW Source Location: RCWSRC The 8 most-significant bits of the RCW location configuration (cfg_rcw_src[8:1]). QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 115 NOTE: Only DDR4 is supported, but the configuration value varies depending on the device. Reserved. IFC Transceiver Enable: Controls cfg_te. Reserved. RCW Source Location (additional): RSRC8 Controls cfg_rcw_src[0] (the LSB of the 9-bit value). QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 116 Controls cfg_svr[0:1] (note the bit order). SVR01 Controls processor pin 'TESTSEL_B'. TEST NOTE: Unlike all other DUTCFG bits, this one is static (always driven). 3.52 DUT Configuration 6 (DUTCFG6) QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 117 RSPDS Configures cfg_rsp_dis: 0 : Reset Sequencer Pause 1 : Reset Sequencer Normal Reserved. Controls cfg_soc_use: 0 : (system-dependent) 1 : (system-dependent) 3.53 DUT Configuration 11 (DUTCFG11) QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 118 1= Processor uses single-ended SYSCLK input. Reserved (cfg_enguse1): ENGUSE1 1= Default value for unassigned pins. Reserved (cfg_enguse2): ENGUSE2 1= Default value for unassigned pins. Reserved. 3.54 DUT Configuration 12 (DUTCFG12) QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 119 DUTCFG registers, unlike BRDCFG registers, are not always driven - they are driven only during the reset configuration sampling interval (PORESET_B assertion), and remain tri-stated thereafter. Refer to the device hardware specification for hardware pin- sampled timing parameters. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 120 : Image of SW1..SWn Ranges not listed are reserved. A standard use of the CMSA/CMSD port is to read the state of configuration switches, as follows: Qixis_Set_Reg( CMS_A, 00h ); QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 121 CMSD contains the value of a CMS register selected by CMSA. See CMSA for details. 3.57.3 Diagram Bits DATA ARST 00000000 3.57.4 Fields Field Function Read/write internal CMS registers selected with CMS_A. DATA QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 122: Address

    (i = 1; i <= nr; i++) { Qixis_Set_Reg( CMS_A, i ); printf("SW%1d = %02X\\ n", i, Qixis_Get_Reg( CMS_D )); 3.59 Switch Control (SWS_CTL) 3.59.1 Address Register Offset SWS_CTL 0DCh QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 123: Function

    POLL 0= Polling is disabled. 1= Polling is enabled; the switches are sampled continually. Reserved. Reserved. 3.60 Switch Sample Status (SWS_STAT) 3.60.1 Address Register Offset SWS_STAT 0DDh QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 124: Function

    SWS_STAT reports on update activity from the serial switch sampler. 3.60.3 Diagram Bits NONE 000000 3.60.4 Fields Field Function Updated: 0= (reserved) 1= The switches were updated. Reserved. Reserved. QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 125 Appendix A Revision history The table below summarizes revisions to this document. Table A-1. Revision history Revision Date Topic cross-reference Change description Rev. 0 09/2018 Initial release QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 126 QorIQ LS1088A Reference Design Board (LS1088ARDB-PB) Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 127 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or Home Page: fabricate any integrated circuits based on the information in this document. NXP reserves the right to nxp.com make changes without further notice to any products herein.

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