Power Supply Trigger Indicator - Tektronix DD 501 Instruction Manual

Theory
of
Operation—
DD
501
Least Significant Digit
Detector
AND
gate
U210C, an
AND
gate with
an
inverting
output
compose
this
stage.
This stage detects only the
BCD
9
count from
the
output of
counter U270.
When
the
most
significant
digits
have
all
been counted,
or there are
none
to
be counted,
pin
4 of
U210A
is
driven
HI.
At an 8 count,
pin 5 of
U210A
is
driven HI,
pin 2 drives pin
13of
U210C
HI.
At a 9 count pin 12
is
driven HI
and
pin 9
drives pin 7 of
U270 LO, thereby enabling pin 7 of
the counter. Pin 15
of
U210C
drives pin
6
of
U210B
HI.
Carry
Gate
Inverter
U215D,
OR
gate
U215C, and
translator
Q280
compose
this
stage.
A LO
state
enables
U215D
and
the
resultant HI
output enables pin
13
of
U215C. With
pin
1
2of
U215C
LO, pin 9
drives the
base
of
0280
HI.
With
pin 12 HI,
the signals
at
pin
13
will
not pass on
to
the
base
of
0280.
When
the collector of
0280 goes LO, the
negative-going
LO
triggers pin
8
of
U265.
0280
takes the
ECL
level
signal
from
pin
9
of
U215C and
provides
an
inverted,
TTL
compatible signal for
U265.
Most
Significant Digits
Counters
Four
programmed
decade counters,
U250, U255, U260,
and U265
compose
this
stage. All
four of the
counting
devices use
pin
1
for preset,
and
pin 8 to
increment the
count on
a
falling
(negative-going)
LO.
The
front
panel
thumbwheel
switch,
S410A,
B, C, D,
and E provides the
preset inputs
to
pins
4,
10,
3,
and
11
with a
9's
complement
in
binary
coded decimal form.
The
9's
complement
of a
number
can be defined as the value that
must be added
to
the
number
to yield
9.
For example,
the
9's
complement
of
7
is 2.
A
9 count
produces a HI state
on
all
pins 5
and
12.
Most
Significant Digits
Detector
Eight-input
NAND
gate
U290 comprises
this stage.
This stage detects the
BCD
9
count from the
most
significant digit
counters.
One
or
more
inputs of
U290
are
driven
LO
by the
most
significant
digits
counters
will
produce a HI
state at pin
8.
When
all
inputs of
U290
are
driven HI, pin 8 of
U290 enables
pin 2 of
U200 and
sets the
base
of
0290
to
a
LO
state.
Most
Significant Digits
Counter Reset
OR
gate U200,
monostable
multivibrator
U340B, and
0205 compose
this stage.
When
U290
drives pin 2
of
U200
LO,
pin 3
places pin 10
of
U340B
LO.
A
Hi state pulse
from
pin
9
of
U340B
sets pin
1
of
U200
HI
for
approximately 50
nanoseconds, and
the
U200
50
nanosecond
pulse sets pin
10 of
U340B
HI.
In
the
quiescent
state,
the collector of
0205
is
HI with
pin
9
LO
and
pin
8 HI of
U340B.
A
positive-going trigger
applied
to pin
1 1
of
U340B changes
pin
8
LO
and
pin 9 HI.
With
C204 charged
positive at pin 8
(when
the
change
of
state
occurs) the
base
of
0205
is
placed
at
approximately
"5
volts.
With
pin 9 HI,
0204
is
charged
positive
through
R204
with
a
time constant of
approximately 50
nanoseconds.
When
the junction of
0204
and R204
charges
to
about
-1-0.6
volt,
0205
is
turned
on.
This places
pin
13
of
U340B
LO,
and
resets
U340B
to
the
quiescent
state.
Most
Significant Digits
Latch
Translator 0290, inverter
U240D,
OR
gate
U240C, and
bistable multivibrator
U240A, U215A, and
U215B com-
pose
this
stage. Pin 8 of
LI290
goes
low, thereby setting pin
12 of
U240C and
pin 10, 11
of inverter
U240D
HI. Pin
9
of
U240C goes
to
a HI
state
and enables
U215C
and U210A.
Inverter
U240D
disables
U240A
with a
LO
state at
pin 4 of
U240A.
The
output
of
U240A
enables
U215B
which
drives
the output
of
U215B
LO
and the output of
U215A
HI.
The
output of
U215A
will
go
LO
as the input
(pin 5)
goes
HI.
Final
Count
Detector
AND
gate
U21
OB,
NOR
gate U240B, and
flipflop
U230B
compose
this
stage.
AND
gate
U210B
is
enabled by
the HI
state
output
at
pin 2 of
U230A and
pin
15
of
U210C,
thereby establishing a HI
output to pin
10,
U230B.
Pin
6of
U240B
is
HI
and
pin 3
is
LO
and remains
LO
until
an events
trigger
pulse
drives pin
7 HI
and the positive-going pulse
triggers pin
11
of
U230B.
Flipfiop
U230B
output changes
state
with the positive-going trigger to pin
1 1
,
driving pin
14
LO
and
pin
15
HI.
The
LO
output
to
0340 base
is
the
delayed trigger output signal.
The
HI
output from
pin
1
5
of
U230B
resets
start
trigger
gate
U230A.
When
the negative-
going
transition of
the events
trigger
pulse
from
U280C
drives pin
7
of
U240B
LO,
pin
3 output
drives pin
13
of
U230B
HI,
and
resets
U230B.
Manual
Reset
Translator 0200,
inverter
U280D
and
buffer
U210D
compose
this stage.
Front panel
pushbutton
RESET
switch
S240 grounds
LO
for
manual
reset.
A LO
on
pins 10
and
1 1
of
U280D
produces a
reset
pulse
to pin
5 of
U280A,
pin
13 of
U280C,
pins 10
and
11
of
U210D
and
the
base
of
0200. As
the reset
pulse from
U280D
drives the
base
of
0200
HI,
the collector
assumes
a
LO
state.
As
the collector
changes
to HI,
the positive-going HI triggers pin 11 of
U340B, Pins 10 and
11 of
U210D
are driven HI
and
pin
14
resets
U230A.
POWER
SUPPLY
&
TRIGGER INDICATOR
Start
Trigger
Lamp
Multivibrator
Inverter
0330 and monostable multivibrator
U325B and
0335 compose
this stage.
When
the
base
of
0330
is
driven
3-7