Below) - Tektronix DD 501 Instruction Manual

Theory
of
Operation—
DD
501
instant that
the
Event pulse
goes
low,
U230B
is
reset
by
its
own
low
Q
output
and
the
low Event
signal,
through
NAND
gate U240B.
When
flipflop
U232B
is
set
by an Event
pulse as
explained
in
the preceding paragraph,
it
promptly resets
itself
with the high
from
its
Q
output.
As
it
resets,
the
positive-going
edge
from
its
Q
output
sets flipflop
U232A,
which,
in turn,
activates
the
LSD Load
gates
in
U272.
U232A
promptly
resets itself
with
its
own
Q
output, but
has
remained
set
long
enough
to
load the
LSD
counter.
With the
arrival
of
the
second
Start pulse, flipflop
U230A
again sets
and
enables
AND
gates
U273A
and
U273B
to
pass the Event pulses
to the
LSD
counter. This
counting cycle
and
all
following cycles
(until
RESET
is
again pressed)
starts
with the correct
9's
complement
loaded
Into
the
LSD
counter.
When
the
count
in
the
LSD
counter reaches lOOOa.the
output
on
pin 2 of
U271 goes high (see Fig. 3-2).
The
high
from U271 pin 2
is
inverted to a
low by
U215D
and
is
applied to
one
input
of
OR
gate
U215C. Since
the
9's
decoder has not detected
all
9s, its
output
is
high,
which
causes pin 12
of
U240C
to
be low; pin
13
of
U240C
is
held
low by
flipflop
U215A/B
at this
time.
Therefore, the other
input to
U215C
is
a low from
U240C, so the output of
U21
5C
goes low and biases transistor
Q280
on.
The
output
of
U271
pin 2
remains high
for
2 Events,
then
goes
low;
the
resulting
negative-going signal
at
the collector of
Q280
increments U265, the
10'
counter.
As each counter
overflows,
it
increments the next.
When
the
count reaches
99999, the output
of
U290
pin 8
goes
low.
The
low from
U290 causes the output of
OR
gate
U200
to
go
low
and
set
flipflop
U340B.
The
Q
output
of
U340B goes low
and
re-loads the
thumbwheels
into
the
four
MSD
counter. (After
a delay
determined by C204,
transistor
Q205
resets
U340B.)
The low from U290
is
also
inverted
by
Q290
and
applied
through inverter
U240D
to
one
input of
NOR
gate
U240A.
With lows
on both
its
inputs,
the output of
U240A
pin
2
goes
high
and
resets
the
flipflop
consisting of
U215A
and U215B.
The
output
of
U215A
pin
2
goes high and (through
OR
gate
U240C)
activates
AND
gate
U210A.
The
output
of
U210A
pin
2 activates
AND/NAND
gate
U210C, which
firstly
inhibits
U273 and
stops the Events from incrementing the
LSD
counter,
and
secondly enables
AND
gate
U210B.
U210B
Is
now
ac-
tivated
and
the
LSD
is
re-loaded as previously explained.
When U210B
is
activated,
it
puts a high
on the
D
inputs
of
U230B
and
U274.
U274
resets
U230A
and thereby
removes
the
activating input
from U210B.
The
Q
output of
U230B
causes the
LSD
from
the
thumbwheels
to
be loaded
into
U271
as previously explained.
The
Q
output of
U230B
activates negative-input
NAND
gate
U240B,
whose
output
resets the
flipflop
consisting
of
U215A
and U215B.
The
output
of
U240B
also resets
U230B.
With
the
counters re-loaded, the
output
of
99999
Detector
U290
goes
high.
The
high
from U290,
after
inversion
by Q290, removes
the
activating inputs from
OR
gate
U240C and
AND
gate
U210A. As
a result,
the inverted
output
of
U210C
goes
high
and enables
U273D
to
pass
Event pulses
to
increment
the
LSD
counter.
With the
arrival of
the next Start
and
Event pulses,
AND
gates
U273A
and
U273D
are again activated
and pass the Event
pulses
to
increment the
LSD
counter.
Fig.
3-3
is
a timing
diagram
of
the events
that
occur during the processing
of
a count.
COUNTER
CIRCUIT
^
(SN B020529 and below)
start
T
rigger
Gate
Flipflop
U230A comprises
this
stage.
A
HI state at pin
4
of
U230A produces
a HI
on
pin
3
and
disables
counter
U270.
A
plus trigger
at pin
6
of
U230A produces
a
LO
on
pin
3,
thereby enabling counter U270
and
inverter
Q330.
Events Delay
Inverter
U280B,
NOR
gate
U280A
and
OR
gate
U280C
compose
this
stage. Positive-going triggers
from
U44A
or
U44C
drive pins 6
and
7
of
U280B.
A LO
from pin 3
of
U280B
drives pin 4 of
U280A
and
inverter
Q320.
Pin 5 of
U280A
is
normally
LO
and
is
driven HI
during counter
reset.
When
pin
4of
U280A
is
LO,
pin
12of
U280C
is
driven
HI
allowing the HI output
from
pin
9
to
enable
U240B,and
U270
starts
counting.
The
overall
delay through
this
stage
is
approximately 6
nanoseconds
to
ensure
that
the
start
trigger
has occurred
before the events are counted.
Least Significant Digit
Counter
Programmed decade counter U270
comprises
this
stage.
Pins
7,
10,
and 13 determine the operation of the
counter: pin 7
LO
to preset, pin
10
LO
to
enable
counting,
and
pin 13
(during a positive transition) to initiate
a count.
The
front
panel
thumbwheel
switch,
S410E,
loads the
program input
to pins
5, 6,
11,
and 12 with
a 9's
complement
In
binary
coded
decimal form.
The
9's
complement
of
a
number
can be defined as the value that
must
be
added
to the
number
to yield
9.
For example, the
9's
complement
of
7
is
2.
When
at
a 9 count, pins
3
and
1
of
U270
yield
HI
state
outputs.
REV.
A,
NOV
1975
3-5