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General Description
1.5.5.4
Level 3 Host Processor Interrupt.
Logic is included in the 990/10A design to allow multiple
processor boards to operate together in a single chassis with the processor in slot 1 acting as a
_ host processor. This requires attention and acknowledge interrupts between the host processor and
the auxiliary processors. The host processor can interrupt the auxiliary through a TPCS register. The
auxiliary can acknowledge that interrupt by generating an interrupt back to the host. In a similar
fashion, the auxiliary can generate an attention interrupt to the host and the host can acknowledge
by setting a bit that interrupts the auxiliary. Either of these interrupts can be masked on the remote
processor through the TPCS registers.
1.5.5.5
Level 5 or 15 Interrupt (Real-Time Clock).
A line frequency synchronized oscillator on the
power supply is an input to the 990/10A processor. On every cycle of the oscillator (either 8.33 or 10.0
milliseconds depending on the line frequency) the real-time clock interrupt signal is generated. This
signal can be connected by a jumper on the processor board to interrupt level 5 or level 15, or it can
be disconnected. The clock on (CKON) and clock off (CKOF) instructions enable or disable the real-
time clock interrupt independently of the interrupt mask.
1.5.5.6
Level 8 (EIA Port Interrupt).
The interrupt from the EIA port on the processor board is
jumpered to level 8. This interrupt is enabled or disabled by setting a specified CRU output bit and is
disconnected by removing a jumper on the processor board (see Section 2 for jumper descriptions).
1.5.5.7
External
Interrupts.
Interrupt
requests
from
other
boards
can
be wired
by
backpanel
jumpers to any of the 13 interrupt request lines (levels 3 through 15). These lines form 13 separate
wired-OR interrupt buses. Each interrupt request signal must be an active low signal driven by an
open coilector TTL gate. The request signal must remain active until it is reset by software com-
munication.
When operated ina
slot other than slot 1, only the internally generated interrupts can, in general, be
received by the processor. There is one exception that might be exploited for some
applications.
That exception occurs because the backpanel connector P2 pin 66 is normally an output for TILINE
or CRU devices to send interrupts to the interrupt jumper plug. This pin, on a 990/10A is actually an
input to interrupt level 14. Therefore it is possible, by modifying the backpanel jumper plug, to direct
one external interrupt into the 990/10A at level 14 while operating as an auxiliary processor.
When
in slot 1, all interrupts are received by the processor. Those interrupts that are allotted to in-
ternal processor board functions share a particular wired-OR interrupt level with the external inter-
rupts unless disconnected by removing the jumper.
1.5.5.8
Nonmaskable Interrupt (NMI).
The function referred to as the nonmaskable interrupt is
equivalent to the load function in other 990 family microprocessors. NMI cannot be disabled by the
interrupt mask logic and is therefore always executed as soon as the current instruction is com-
pleted. NMI causes execution to begin with the WP at location >FFFC
and the PC at location
> FFFE. NMI is activated by the restart signal. This signal can result from the execution of an LREX
instruction, from the HALT switch on the front panel, or from power-up.
When
an NMI occurs, the NMI
handler in the loader/self-test ROM
determines
the sequence
that
follows the NMI. This sequence depends on whether the central processing unit (CPU) is a host or
auxiliary, a front panel is present, and the NMI occurred as a result of power-up. A flowchart of the
NMI handler is shown
in Figure 1-3.
2302633-9701
1°13
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